Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 8a81954..4576925 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -102,6 +102,7 @@
wire [1:0] reg_cfg_we = (simple_spi_master_reg_cfg_sel) ?
(wb_sel_i[1:0] & {2{wb_we_i}}): 2'b00;
wire reg_dat_we = (simple_spi_master_reg_dat_sel) ? (wb_sel_i[0] & wb_we_i): 1'b0;
+ wire reg_dat_wait;
wire [31:0] mem_wdata = wb_dat_i;
wire reg_dat_re = simple_spi_master_reg_dat_sel && !wb_sel_i && ~wb_we_i;
@@ -388,3 +389,4 @@
end // always
endmodule
+`default_nettype wire
