In spite of many errors that still need fixing, this is a major advance
over the previous commit. All verilog modules are in place more or less
as intended, with various functions such as the housekeeping SPI placed
on user area pads, with the ability to switch to user control from the
configuration. The pad control bits are local to the pads and loaded
via serial shift register, so that there are not hundreds of control wires
feeding into the user space. The user has three basic controls over each
pad: in, out, and outenb. Two timer/counters and an SPI master have been
added to the SoC. The SPI master shares I/O with the housekeeping SPI, so
that all housekeeping SPI registers can be accessed from the SoC directly.
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index de6ac2a..dad5471 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -82,6 +82,7 @@
output csb, // SPI chip select
output sck, // SPI clock
output sdo, // SPI output
+ output sdoenb, // SPI output enable
output irq // interrupt output
);
@@ -175,13 +176,16 @@
wire irq_out;
wire sck;
wire sdo;
+ wire sdoenb;
// Define behavior for inverted SCK and inverted CSB
- assign csb = (invcsb) ? ~icsb : icsb;
- assign sck = (invsck) ? ~isck : isck;
+ assign csb = (enable == 1'b0) ? 1'bz : (invcsb) ? ~icsb : icsb;
+ assign sck = (enable == 1'b0) ? 1'bz : (invsck) ? ~isck : isck;
// No bidirectional 3-pin mode defined, so SDO is enabled whenever CSB is low.
- assign sdo = icsb ? 1'bz : isdo;
+ assign sdoenb = icsb;
+ // assign sdo = (enable == 1'b0) ? 1'bz : icsb ? 1'bz : isdo;
+ assign sdo = isdo;
assign irq_out = irqena & done;
