Revised the clocking scheme in several ways: (1) Removed the output
clock divider from the PLL to the clocking module; (2) changed the
clock divider from a power-of-2 divider to an integer-N divider;
(3) added an enable to the PLL separate from the bypass, so that the
PLL can be started and have time to settle before being switched in.
(4) Made some attempts at glitch-free clock switching when changing
to and from the PLL, and when changing output divider values.
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll.c b/verilog/dv/caravel/mgmt_soc/pll/pll.c
index dd8e0d6..b74860b 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll.c
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll.c
@@ -63,15 +63,20 @@
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x11; // Write 0x11 (start address)
- reg_spimaster_data = 0x02; // Write 0x02 to PLL select
+ reg_spimaster_data = 0x08; // Write 0x18 (start address)
+ reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x08; // Write 0x08 (start address)
- reg_spimaster_data = 0x00; // Write 0x00 to turn off DCO mode
- reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL
+ reg_spimaster_data = 0x11; // Write 0x11 (start address)
+ reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x09; // Write 0x09 (start address)
+ reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write checkpoint
@@ -80,7 +85,7 @@
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x12; // Write 0x12 (start address)
- reg_spimaster_data = 0x03; // Write 0x03 to divider (was 0x04)
+ reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write checkpoint
@@ -89,7 +94,7 @@
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x11; // Write 0x11 (start address)
- reg_spimaster_data = 0x03; // Write 0x03 to PLL select
+ reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0x2102; // Release housekeeping SPI
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 5fc90d4..79830be 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -41,12 +41,13 @@
`include "mgmt_soc.v"
`include "housekeeping_spi.v"
`include "digital_pll.v"
-`include "caravel_clkrst.v"
+`include "caravel_clocking.v"
`include "mgmt_core.v"
`include "mprj_io.v"
`include "chip_io.v"
`include "user_id_programming.v"
`include "gpio_control_block.v"
+`include "clock_div.v"
`include "simple_por.v"
/*------------------------------*/
@@ -339,7 +340,6 @@
.porb(porb_l),
// Clocks and reset
.clock(clock_core),
- .pll_clk16(pll_clk16),
.core_clk(caravel_clk),
.core_rstn(caravel_rstn),
// Logic Analyzer
diff --git a/verilog/rtl/caravel_clkrst.v b/verilog/rtl/caravel_clkrst.v
deleted file mode 100644
index af40b8f..0000000
--- a/verilog/rtl/caravel_clkrst.v
+++ /dev/null
@@ -1,35 +0,0 @@
-module caravel_clkrst(
-`ifdef LVS
- input vdd1v8,
- input vss,
-`endif
- input ext_clk_sel,
- input ext_clk,
- input pll_clk,
- input resetb,
- input ext_reset, // NOTE: positive sense reset
- output core_clk,
- output resetb_sync
-);
-
- // Clock assignment (to do: make this glitch-free)
- assign core_clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
-
- // Reset assignment. "reset" comes from POR, while "ext_reset"
- // comes from standalone SPI (and is normally zero unless
- // activated from the SPI).
-
- // Staged-delay reset
- reg [2:0] reset_delay;
-
- always @(posedge core_clk or negedge resetb) begin
- if (resetb == 1'b0) begin
- reset_delay <= 3'b111;
- end else begin
- reset_delay <= {1'b0, reset_delay[2:1]};
- end
- end
-
- assign resetb_sync = ~(reset_delay[0] | ext_reset);
-
-endmodule
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
new file mode 100644
index 0000000..db249d2
--- /dev/null
+++ b/verilog/rtl/caravel_clocking.v
@@ -0,0 +1,75 @@
+// This routine synchronizes the
+
+module caravel_clocking(
+`ifdef LVS
+ input vdd1v8,
+ input vss,
+`endif
+ input resetb, // Master (negative sense) reset
+ input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock
+ input ext_clk, // External pad (slow) clock
+ input pll_clk, // Internal PLL (fast) clock
+ input [2:0] sel, // Select clock divider value (0=thru, 1=divide-by-2, etc.)
+ input ext_reset, // Positive sense reset from housekeeping SPI.
+ output core_clk, // Output core clock
+ output resetb_sync // Output propagated and buffered reset
+);
+
+ wire pll_clk_sel;
+ reg use_pll_first;
+ reg use_pll_second;
+ reg ext_clk_syncd_pre;
+ reg ext_clk_syncd;
+
+ assign pll_clk_sel = ~ext_clk_sel;
+
+ // Note that this implementation does not guard against switching to
+ // the PLL clock if the PLL clock is not present.
+
+ always @(posedge pll_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ use_pll_first <= 1'b0;
+ use_pll_second <= 1'b0;
+ ext_clk_syncd <= 1'b0;
+ end else begin
+ use_pll_first <= pll_clk_sel;
+ use_pll_second <= use_pll_first;
+ ext_clk_syncd_pre <= ext_clk; // Sync ext_clk to pll_clk
+ ext_clk_syncd <= ext_clk_syncd_pre; // Do this twice (resolve metastability)
+ end
+ end
+
+ // Apply PLL clock divider
+
+ clock_div #(
+ .SIZE(3)
+ ) divider (
+ .in(pll_clk),
+ .out(pll_clk_divided),
+ .N(sel),
+ .resetb(resetb)
+ );
+
+ // Multiplex the clock output
+
+ assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
+ assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
+
+ // Reset assignment. "reset" comes from POR, while "ext_reset"
+ // comes from standalone SPI (and is normally zero unless
+ // activated from the SPI).
+
+ // Staged-delay reset
+ reg [2:0] reset_delay;
+
+ always @(posedge core_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ reset_delay <= 3'b111;
+ end else begin
+ reset_delay <= {1'b0, reset_delay[2:1]};
+ end
+ end
+
+ assign resetb_sync = ~(reset_delay[0] | ext_reset);
+
+endmodule
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
new file mode 100644
index 0000000..01d03a8
--- /dev/null
+++ b/verilog/rtl/clock_div.v
@@ -0,0 +1,195 @@
+/* Integer-N clock divider */
+
+module clock_div #(
+ parameter SIZE = 3 // Number of bits for the divider value
+) (
+ in, out, N, resetb
+);
+ input in; // input clock
+ input [SIZE-1:0] N; // the number to be divided by
+ input resetb; // asynchronous reset (sense negative)
+ output out; // divided output clock
+
+ wire out_odd; // output of odd divider
+ wire out_even; // output of even divider
+ wire not_zero; // signal to find divide by 0 case
+ wire enable_even; // enable of even divider
+ wire enable_odd; // enable of odd divider
+
+ reg [SIZE-1:0] syncN; // N synchronized to output clock
+ reg [SIZE-1:0] syncNp; // N synchronized to output clock
+
+ assign not_zero = | syncN[SIZE-1:1];
+
+ assign out = (out_odd & syncN[0] & not_zero) | (out_even & !syncN[0]);
+ assign enable_odd = syncN[0] & not_zero;
+ assign enable_even = !syncN[0];
+
+ // Divider value synchronization (double-synchronized to avoid metastability)
+ always @(posedge out or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ syncN <= 'd2; // Default to divide-by-2 on system reset
+ syncNp <= 'd2; // Default to divide-by-2 on system reset
+ end else begin
+ syncNp <= N;
+ syncN <= syncNp;
+ end
+ end
+
+ // Even divider
+ even even_0(in, out_even, syncN, resetb, not_zero, enable_even);
+ // Odd divider
+ odd odd_0(in, out_odd, syncN, resetb, enable_odd);
+
+endmodule // clock_div
+
+/* Odd divider */
+
+module odd #(
+ parameter SIZE = 3
+) (
+ clk, out, N, resetb, enable
+);
+ input clk; // slow clock
+ output out; // fast output clock
+ input [SIZE-1:0] N; // division factor
+ input resetb; // synchronous reset
+ input enable; // odd enable
+
+ reg [SIZE-1:0] counter; // these 2 counters are used
+ reg [SIZE-1:0] counter2; // to non-overlapping signals
+ reg out_counter; // positive edge triggered counter
+ reg out_counter2; // negative edge triggered counter
+ reg rst_pulse; // pulse generated when vector N changes
+ reg [SIZE-1:0] old_N; // gets set to old N when N is changed
+ wire not_zero; // if !not_zero, we devide by 1
+
+ // xor to generate 50% duty, half-period waves of final output
+ assign out = out_counter2 ^ out_counter;
+
+ // positive edge counter/divider
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ counter <= N;
+ out_counter <= 1;
+ end else if (rst_pulse) begin
+ counter <= N;
+ out_counter <= 1;
+ end else if (enable) begin
+ if (counter == 1) begin
+ counter <= N;
+ out_counter <= ~out_counter;
+ end else begin
+ counter <= counter - 1'b1;
+ end
+ end
+ end
+
+ reg [SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
+ wire [SIZE:0] interm_3; // from the positive edge counter in order to
+ assign interm_3 = {1'b0,N} + 2'b11; // guarante 50% duty cycle.
+
+ // Counter driven by negative edge of clock.
+
+ always @(negedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ // reset the counter at system reset
+ counter2 <= N;
+ initial_begin <= interm_3[SIZE:1];
+ out_counter2 <= 1;
+ end else if (rst_pulse) begin
+ // reset the counter at change of N.
+ counter2 <= N;
+ initial_begin <= interm_3[SIZE:1];
+ out_counter2 <= 1;
+ end else if ((initial_begin <= 1) && enable) begin
+
+ // Do normal logic after odd calibration.
+ // This is the same as the even counter.
+ if (counter2 == 1) begin
+ counter2 <= N;
+ out_counter2 <= ~out_counter2;
+ end else begin
+ counter2 <= counter2 - 1'b1;
+ end
+ end else if (enable) begin
+ initial_begin <= initial_begin - 1'b1;
+ end
+ end
+
+ //
+ // reset pulse generator:
+ // __ __ __ __ _
+ // clk: __/ \__/ \__/ \__/ \__/
+ // _ __________________________
+ // N: _X__________________________
+ // _____
+ // rst_pulse: __/ \___________________
+ //
+ // This block generates an internal reset for the odd divider in the
+ // form of a single pulse signal when the odd divider is enabled.
+
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ rst_pulse <= 0;
+ end else if (enable) begin
+ if (N != old_N) begin
+ // pulse when reset changes
+ rst_pulse <= 1;
+ end else begin
+ rst_pulse <= 0;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ // always save the old N value to guarante reset from
+ // an even-to-odd transition.
+ old_N <= N;
+ end
+
+endmodule // odd
+
+/* Even divider */
+
+module even #(
+ parameter SIZE = 3
+) (
+ clk, out, N, resetb, not_zero, enable
+);
+ input clk; // fast input clock
+ output out; // slower divided clock
+ input [SIZE-1:0] N; // divide by factor 'N'
+ input resetb; // asynchronous reset
+ input not_zero; // if !not_zero divide by 1
+ input enable; // enable the even divider
+
+ reg [SIZE-1:0] counter;
+ reg out_counter;
+ wire [SIZE-1:0] div_2;
+
+ // if N=0 just output the clock, otherwise, divide it.
+ assign out = (clk & !not_zero) | (out_counter & not_zero);
+ assign div_2 = {1'b0, N[SIZE-1:1]};
+
+ // simple flip-flop even divider
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ counter <= 1;
+ out_counter <= 1;
+
+ end else if (enable) begin
+ // only use switching power if enabled
+ if (counter == 1) begin
+ // divide after counter has reached bottom
+ // of interval 'N' which will be value '1'
+ counter <= div_2;
+ out_counter <= ~out_counter;
+ end else begin
+ // decrement the counter and wait
+ counter <= counter-1; // to start next transition.
+ end
+ end
+ end
+
+endmodule //even
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index d4fe6ff..77cce42 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -9,35 +9,31 @@
vdd,
vss,
`endif
- resetb, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim);
+ resetb, enable, osc, clockp, div, dco, ext_trim);
`ifdef LVS
input vdd;
input vss;
`endif
- input resetb; // Sense negative reset
- input extclk_sel; // External clock select (acts as 2nd reset)
- input osc; // Input oscillator to match
- input [4:0] div; // PLL feedback division ratio
- input [2:0] sel; // Core clock select
- input dco; // Run in DCO mode
+ input resetb; // Sense negative reset
+ input enable; // Enable PLL
+ input osc; // Input oscillator to match
+ input [4:0] div; // PLL feedback division ratio
+ input dco; // Run in DCO mode
input [25:0] ext_trim; // External trim for DCO mode
- output clockc; // Selected core clock output
output [1:0] clockp; // Two 90 degree clock phases
- output [3:0] clockd; // Divided clock (2, 4, 8, 16)
- wire [25:0] itrim; // Internally generated trim bits
- wire [25:0] otrim; // Trim bits applied to the ring oscillator
- wire [3:0] nint; // Internal divided down clocks
- wire resetbb; // Internal buffered negative sense reset
- wire creset; // Controller reset
- wire ireset; // Internal reset (external reset OR extclk_sel)
+ wire [25:0] itrim; // Internally generated trim bits
+ wire [25:0] otrim; // Trim bits applied to the ring oscillator
+ wire creset; // Controller reset
+ wire ireset; // Internal reset (external reset OR disable)
- assign ireset = ~resetb | extclk_sel;
+ assign ireset = ~resetb | ~enable;
// In DCO mode: Hold controller in reset and apply external trim value
+
assign itrim = (dco == 1'b0) ? otrim : ext_trim;
assign creset = (dco == 1'b0) ? ireset : 1'b1;
@@ -55,53 +51,4 @@
.trim(otrim)
);
- // Select core clock output
- assign clockc = (sel == 3'b000) ? clockp[0] :
- (sel == 3'b001) ? clockd[0] :
- (sel == 3'b010) ? clockd[1] :
- (sel == 3'b011) ? clockd[2] :
- clockd[3];
-
- // Derive internal negative-sense reset from the input negative-sense reset
-
- sky130_fd_sc_hd__buf_8 irbb (
- .A(resetb),
- .X(resetbb)
- );
-
- // Create divided down clocks. The inverted output only comes
- // with digital standard cells with inverted resets, so the
- // reset has to be inverted as well.
-
- sky130_fd_sc_hd__dfrbp_1 idiv2 (
- .CLK(clockp[1]),
- .D(clockd[0]),
- .Q(nint[0]),
- .Q_N(clockd[0]),
- .RESET_B(resetbb)
- );
-
- sky130_fd_sc_hd__dfrbp_1 idiv4 (
- .CLK(clockd[0]),
- .D(clockd[1]),
- .Q(nint[1]),
- .Q_N(clockd[1]),
- .RESET_B(resetbb)
- );
-
- sky130_fd_sc_hd__dfrbp_1 idiv8 (
- .CLK(clockd[1]),
- .D(clockd[2]),
- .Q(nint[2]),
- .Q_N(clockd[2]),
- .RESET_B(resetbb)
- );
-
- sky130_fd_sc_hd__dfrbp_1 idiv16 (
- .CLK(clockd[2]),
- .D(clockd[3]),
- .Q(nint[3]),
- .Q_N(clockd[3]),
- .RESET_B(resetbb)
- );
endmodule
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 42677d4..879aff8 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -37,14 +37,14 @@
// with via programming. Via programmed with a script to match
// each customer ID.
//
-// Register 8: PLL enable (1 bit)
+// Register 8: PLL enables (2 bits)
// Register 9: PLL bypass (1 bit)
// Register 10: IRQ (1 bit)
// Register 11: reset (1 bit)
// Register 12: trap (1 bit) (readonly)
// Register 13-16: PLL trim (26 bits)
-// Register 17: PLL output select (3 bits)
-// Register 18: PLL divider (5 bits)
+// Register 17: PLL output divider (3 bits)
+// Register 18: PLL feedback divider (5 bits)
//------------------------------------------------------------
module housekeeping_spi(
@@ -52,7 +52,7 @@
vdd, vss,
`endif
RSTB, SCK, SDI, CSB, SDO, sdo_enb,
- pll_dco_ena, pll_div, pll_sel,
+ pll_ena, pll_dco_ena, pll_div, pll_sel,
pll_trim, pll_bypass, irq, reset, trap,
mask_rev_in, pass_thru_reset,
pass_thru_mgmt_sck, pass_thru_mgmt_csb,
@@ -74,6 +74,7 @@
output SDO; // to padframe
output sdo_enb; // to padframe
+ output pll_ena;
output pll_dco_ena;
output [4:0] pll_div;
output [2:0] pll_sel;
@@ -101,6 +102,7 @@
reg [4:0] pll_div;
reg [2:0] pll_sel;
reg pll_dco_ena;
+ reg pll_ena;
reg pll_bypass;
reg reset_reg;
reg irq;
@@ -175,7 +177,7 @@
(iaddr == 8'h06) ? mask_rev[15:8] : // Mask rev (metal programmed)
(iaddr == 8'h07) ? mask_rev[7:0] : // Mask rev (metal programmed)
- (iaddr == 8'h08) ? {7'b0000000, pll_dco_ena} :
+ (iaddr == 8'h08) ? {6'b0000000, pll_dco_ena, pll_ena} :
(iaddr == 8'h09) ? {7'b0000000, pll_bypass} :
(iaddr == 8'h0a) ? {7'b0000000, irq} :
(iaddr == 8'h0b) ? {7'b0000000, reset} :
@@ -195,16 +197,18 @@
// Set trim for PLL at (almost) slowest rate (~90MHz). However,
// pll_trim[12] must be set to zero for proper startup.
pll_trim <= 26'b11111111111110111111111111;
- pll_sel <= 3'b000;
- pll_div <= 5'b00100; // Default divide-by-8
+ pll_sel <= 3'b010; // Default output divider divide-by-2
+ pll_div <= 5'b00100; // Default feedback divider divide-by-8
pll_dco_ena <= 1'b1; // Default free-running PLL
- pll_bypass <= 1'b1; // NOTE: Default bypass mode (don't use PLL)
+ pll_ena <= 1'b0; // Default PLL turned off
+ pll_bypass <= 1'b1; // Default bypass mode (don't use PLL)
irq <= 1'b0;
reset_reg <= 1'b0;
end else if (wrstb == 1'b1) begin
case (iaddr)
8'h08: begin
- pll_dco_ena <= idata[0];
+ pll_ena <= idata[0];
+ pll_dco_ena <= idata[1];
end
8'h09: begin
pll_bypass <= idata[0];
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 297b76a..8435a5e 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -32,7 +32,6 @@
input porb,
// Clocking
input clock,
- output pll_clk16,
// LA signals
input [127:0] la_input, // From Mega-Project to cpu
output [127:0] la_output, // From CPU to Mega-Project
@@ -75,20 +74,21 @@
input [31:0] mask_rev
);
wire ext_clk_sel;
- wire pll_clk;
+ wire pll_clk, pll_clk90;
wire ext_reset;
wire hk_connect;
- caravel_clkrst clkrst(
+ caravel_clocking clocking(
`ifdef LVS
.vdd1v8(vdd1v8),
.vss(vss),
`endif
.ext_clk_sel(ext_clk_sel),
- .ext_clk(clock), // Should be better handled. . .
+ .ext_clk(clock),
.pll_clk(pll_clk),
.resetb(resetb),
- .ext_reset(ext_reset),
+ .sel(spi_pll_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
.core_clk(core_clk),
.resetb_sync(core_rstn)
);
@@ -123,9 +123,6 @@
.vdd1v8(vdd1v8),
.vss(vss),
`endif
- .pll_clk(pll_clk),
- .ext_clk(clock),
- .ext_clk_sel(ext_clk_sel),
.clk(core_clk),
.resetn(core_rstn),
.trap(trap),
@@ -205,13 +202,10 @@
.vss(vss),
`endif
.resetb(resetb),
- .extclk_sel(ext_clk_sel),
+ .enable(spi_pll_ena),
.osc(clock),
- .clockc(pll_clk),
- .clockp({pll_clk_core0, pll_clk_core90}),
- .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}),
+ .clockp({pll_clk, pll_clk90}),
.div(spi_pll_div),
- .sel(spi_pll_sel),
.dco(spi_pll_dco_ena),
.ext_trim(spi_pll_trim)
);
@@ -240,6 +234,7 @@
.pll_dco_ena(spi_pll_dco_ena),
.pll_sel(spi_pll_sel),
.pll_div(spi_pll_div),
+ .pll_ena(spi_pll_ena),
.pll_trim(spi_pll_trim),
.pll_bypass(ext_clk_sel),
.irq(irq_spi),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 5f1050d..91dfbd5 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -50,10 +50,6 @@
inout vdd1v8, /* 1.8V domain */
inout vss,
`endif
- input pll_clk,
- input ext_clk,
- input ext_clk_sel,
-
input clk,
input resetn,
@@ -319,7 +315,9 @@
irq[11] = irq_counter_timer1;
end
- // Assumption : no syscon module and wb_clk is the clock coming from the chip pin ?
+ // Assumption : no syscon module and wb_clk is the clock coming from the
+ // caravel_clocking module
+
assign wb_clk_i = clk;
assign wb_rst_i = ~resetn; // Redundant
