Vast and substantial changes: Removed the old GPIO control with the new one
that implements a shift register around the perimeter of the chip, to control
most aspects of each GPIO pad locally to avoid excessive wiring. Added modules
for the metal-programmed user ID, two counter-timers, and a general-purpose SPI
master. The SPI master can be internally directly connected to the SPI slave,
so the processor can access the housekeeping SPI in the same way as an external
host. Most signals other than 1 GPIO pin and the SPI flash controller pins were
remapped to pads in the user area, where they are active on startup and until
they are programmed for user use from the management processor. There are
several known syntax issues that need to be fixed; this is a work in progress.
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
new file mode 100644
index 0000000..4e80555
--- /dev/null
+++ b/verilog/rtl/user_id_programming.v
@@ -0,0 +1,36 @@
+// This module represents an unprogrammed mask revision
+// block that is configured with via programming on the
+// chip top level. This value is passed to the block as
+// a parameter
+
+module user_id_programming #(
+ parameter [ 0:0] USER_PROJECT_ID = 32'h0
+) (
+ output [31:0] mask_rev
+);
+ wire [31:0] mask_rev;
+ wire [31:0] user_proj_id_high;
+ wire [31:0] user_proj_id_low;
+
+ // For the mask revision input, use an array of digital constant logic cells
+
+ sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
+ `ifdef LVS
+ .vpwr(vdd1v8),
+ .vpb(vdd1v8),
+ .vnb(vss),
+ .vgnd(vss),
+ `endif
+ .HI(user_proj_id_high),
+ .LO(user_proj_id_low)
+ );
+
+ genvar i;
+ generate
+ for (i = 0; i < 32; i = i+1) begin
+ assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
+ user_proj_id_high[i] : user_proj_id_low[i];
+ end
+ endgenerate
+
+endmodule
