LINSORTER - LinearINsertion SORTER

Block diagram of the LinearINsertion SORTER is given below and detailed explanation of the each block is given inside submodules lis and wb2axip.

This directory contains following submodules and directories:

• Submodule lis - contains a linear insertion sorter (LIS) generator written in Chisel hardware design language. It comprises description of three types of the linear insertion sorter, parameter definition, setup explanation and many other useful information related to blocks that are depicted at presented global block scheme.
• Submodule wb2axip - contains wishbone to AXI4 bridge. Current submodule is forked version of the ZipCPU/wb2axip. While all blocks inside LINSORTER use AXI4 memory mapped bus, this bridge was necessary to attach so that correct connection between processor and linear insertion sorters is established.
• doc - contains global block scheme of the LINSORTER in svg and png format.
• top/dv/LISTest - contains verilog testbenches for LINSORTER integrated with Caravel
• top/rtl/LISTest - contains user_proj_example.v which is the top level verilog file for LINSORTER
• Makefile - has targets for verilog and test generation

Useful commands

In order to generate verilog file LISTest.v which contains verilog code for LinearINsertion SORTER, run command:

$ make verilog_lis

To run chisel tests, run command:

$ make test_lis

In order to run verilog tests for LINSORTER connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click here. To check if paths are set, run command:

$ make check-env

In order to test LINSORTER attached to the Caravel, run command:

$ make test_top

To clean data generated by verilog testbenches, run:

$ make clean_top

Address space for LINSORTER

User address space       0x3000_0000
    ├── in_split:      0x3000_0000
    ├── lisFifo:       0x3000_1000
    ├── lisFifo_mux:   0x3000_1100
    ├── lisFixed:      0x3000_2000
    ├── lisFixed_mux:  0x3000_2100
    ├── lisInput:      0x3000_3000
    ├── lisInput_mux:  0x3000_3100
    ├── bist:          0x3000_4000
    ├── bist_split:    0x3000_4100
    ├── out_mux:       0x3000_5000
    ├── uart:          0x3000_6000
    └── uart_split:    0x3000_6100