| commit | c0cd7c226d540e6fc75150ae3236116f12341734 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Tue Nov 24 20:36:36 2020 -0500 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Tue Nov 24 20:36:36 2020 -0500 |
| tree | f9593aad1d4d1dd91a6552d0168bf9d4738ebb9b | |
| parent | 99dbc249f8d9b17242220a367a68379643e3ada7 [diff] |
Moved the simple_por ngspice simulations into directory ngspice/simple_por/. Added new directory ngspice/digital_pll/ containing simulation testbenches for the digital PLL and trimmable ring oscillator. Added qflow directories for both; this was done only to get a valid xspice file for the controller and a valid SPICE netlist for the ring oscillator.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: