commit | bb3cd69b4ddc706fd7c4f828fb85044152a6bbc5 | [log] [tgz] |
---|---|---|
author | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 09 22:00:23 2020 -0400 |
committer | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 09 22:00:23 2020 -0400 |
tree | b81451f1f1495e75a21ad4ae4f38ed4f69268c21 | |
parent | 8115320f43c8069cbf52bdc6deb34b44bf520a5b [diff] |
Added a behavioral model for the ring oscillator, and a testbench for running the PLL (in behavioral mode), specifically for switching to and from PLL bypass mode from the processor itself.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: