| VERSION 5.8 ; |
| DIVIDERCHAR "/" ; |
| BUSBITCHARS "[]" ; |
| DESIGN mgmt_protect_hv ; |
| UNITS DISTANCE MICRONS 1000 ; |
| DIEAREA ( 0 0 ) ( 25000 25000 ) ; |
| ROW ROW_0 unithv 480 4070 FS DO 50 BY 1 STEP 480 0 ; |
| ROW ROW_1 unithv 480 8140 N DO 50 BY 1 STEP 480 0 ; |
| ROW ROW_2 unithv 480 12210 FS DO 50 BY 1 STEP 480 0 ; |
| ROW ROW_3 unithv 480 16280 N DO 50 BY 1 STEP 480 0 ; |
| TRACKS X 240 DO 52 STEP 480 LAYER li1 ; |
| TRACKS Y 240 DO 52 STEP 480 LAYER li1 ; |
| TRACKS X 185 DO 68 STEP 370 LAYER met1 ; |
| TRACKS Y 185 DO 68 STEP 370 LAYER met1 ; |
| TRACKS X 240 DO 52 STEP 480 LAYER met2 ; |
| TRACKS Y 240 DO 52 STEP 480 LAYER met2 ; |
| TRACKS X 370 DO 34 STEP 740 LAYER met3 ; |
| TRACKS Y 370 DO 34 STEP 740 LAYER met3 ; |
| TRACKS X 480 DO 26 STEP 960 LAYER met4 ; |
| TRACKS Y 480 DO 26 STEP 960 LAYER met4 ; |
| TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ; |
| TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ; |
| VIAS 4 ; |
| - via_1600x510 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 245 180 55 180 + ROWCOL 1 4 ; |
| - via2_1600x510 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 155 100 65 + ROWCOL 1 4 ; |
| - via3_1600x510 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 100 60 100 155 + ROWCOL 1 4 ; |
| - via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 400 400 400 ; |
| END VIAS |
| COMPONENTS 25 ; |
| - mprj2_logic_high_hvl sky130_fd_sc_hvl__conb_1 + PLACED ( 480 8140 ) N ; |
| - mprj2_logic_high_lv sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 4800 8140 ) N ; |
| - mprj_logic_high_hvl sky130_fd_sc_hvl__conb_1 + PLACED ( 21120 8140 ) N ; |
| - mprj_logic_high_lv sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 12960 8140 ) N ; |
| - FILLER_0_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 480 4070 ) FS ; |
| - FILLER_0_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 4320 4070 ) FS ; |
| - FILLER_0_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 8160 4070 ) FS ; |
| - FILLER_0_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 12000 4070 ) FS ; |
| - FILLER_0_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15840 4070 ) FS ; |
| - FILLER_0_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19680 4070 ) FS ; |
| - FILLER_0_48 sky130_fd_sc_hvl__fill_2 + PLACED ( 23520 4070 ) FS ; |
| - FILLER_1_5 sky130_fd_sc_hvl__decap_4 + PLACED ( 2880 8140 ) N ; |
| - FILLER_1_48 sky130_fd_sc_hvl__fill_2 + PLACED ( 23520 8140 ) N ; |
| - FILLER_2_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 480 12210 ) FS ; |
| - FILLER_2_8 sky130_fd_sc_hvl__fill_1 + PLACED ( 4320 12210 ) FS ; |
| - FILLER_2_43 sky130_fd_sc_hvl__decap_4 + PLACED ( 21120 12210 ) FS ; |
| - FILLER_2_47 sky130_fd_sc_hvl__fill_2 + PLACED ( 23040 12210 ) FS ; |
| - FILLER_2_49 sky130_fd_sc_hvl__fill_1 + PLACED ( 24000 12210 ) FS ; |
| - FILLER_3_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 480 16280 ) N ; |
| - FILLER_3_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 4320 16280 ) N ; |
| - FILLER_3_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 8160 16280 ) N ; |
| - FILLER_3_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 12000 16280 ) N ; |
| - FILLER_3_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15840 16280 ) N ; |
| - FILLER_3_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19680 16280 ) N ; |
| - FILLER_3_48 sky130_fd_sc_hvl__fill_2 + PLACED ( 23520 16280 ) N ; |
| END COMPONENTS |
| PINS 4 ; |
| - mprj2_vdd_logic1 + NET mprj2_vdd_logic1 + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 21360 23000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ; |
| - mprj_vdd_logic1 + NET mprj_vdd_logic1 + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ; |
| - VPWR + NET VPWR + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 20350 ) N + LAYER met1 ( -12000 -255 ) ( 12000 255 ) ; |
| - VGND + NET VGND + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 16280 ) N + LAYER met1 ( -12000 -255 ) ( 12000 255 ) ; |
| END PINS |
| SPECIALNETS 2 ; |
| - VPWR ( PIN VPWR ) ( * VPWR ) ( * VPB ) ( * LVPWR ) + USE POWER |
| + ROUTED met4 0 + SHAPE STRIPE ( 20513 17865 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 12500 17865 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 4487 17865 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 20513 12245 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 12500 12245 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 4487 12245 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 20513 6625 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 12500 6625 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 4487 6625 ) via4_1600x1600 |
| NEW met3 0 + SHAPE STRIPE ( 20513 20350 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 20513 20350 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 20513 20350 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 12500 20350 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 12500 20350 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 12500 20350 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 4487 20350 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 4487 20350 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 4487 20350 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 20513 12210 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 20513 12210 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 20513 12210 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 12500 12210 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 12500 12210 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 12500 12210 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 4487 12210 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 4487 12210 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 4487 12210 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 20513 4070 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 20513 4070 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 20513 4070 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 12500 4070 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 12500 4070 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 12500 4070 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 4487 4070 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 4487 4070 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 4487 4070 ) via_1600x510 |
| NEW met5 1600 + SHAPE STRIPE ( 480 17865 ) ( 24480 17865 ) |
| NEW met5 1600 + SHAPE STRIPE ( 480 12245 ) ( 24480 12245 ) |
| NEW met5 1600 + SHAPE STRIPE ( 480 6625 ) ( 24480 6625 ) |
| NEW met4 1600 + SHAPE STRIPE ( 20513 3815 ) ( 20513 20605 ) |
| NEW met4 1600 + SHAPE STRIPE ( 12500 3815 ) ( 12500 20605 ) |
| NEW met4 1600 + SHAPE STRIPE ( 4487 3815 ) ( 4487 20605 ) |
| NEW met1 510 + SHAPE FOLLOWPIN ( 480 20350 ) ( 24480 20350 ) |
| NEW met1 510 + SHAPE FOLLOWPIN ( 480 12210 ) ( 24480 12210 ) |
| NEW met1 510 + SHAPE FOLLOWPIN ( 480 4070 ) ( 24480 4070 ) ; |
| - VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND |
| + ROUTED met4 0 + SHAPE STRIPE ( 16506 15055 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 8493 15055 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 16506 9435 ) via4_1600x1600 |
| NEW met4 0 + SHAPE STRIPE ( 8493 9435 ) via4_1600x1600 |
| NEW met3 0 + SHAPE STRIPE ( 16506 16280 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 16506 16280 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 16506 16280 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 8493 16280 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 8493 16280 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 8493 16280 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 16506 8140 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 16506 8140 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 16506 8140 ) via_1600x510 |
| NEW met3 0 + SHAPE STRIPE ( 8493 8140 ) via3_1600x510 |
| NEW met2 0 + SHAPE STRIPE ( 8493 8140 ) via2_1600x510 |
| NEW met1 0 + SHAPE STRIPE ( 8493 8140 ) via_1600x510 |
| NEW met5 1600 + SHAPE STRIPE ( 480 15055 ) ( 24480 15055 ) |
| NEW met5 1600 + SHAPE STRIPE ( 480 9435 ) ( 24480 9435 ) |
| NEW met4 1600 + SHAPE STRIPE ( 16506 3815 ) ( 16506 20605 ) |
| NEW met4 1600 + SHAPE STRIPE ( 8493 3815 ) ( 8493 20605 ) |
| NEW met1 510 + SHAPE FOLLOWPIN ( 480 16280 ) ( 24480 16280 ) |
| NEW met1 510 + SHAPE FOLLOWPIN ( 480 8140 ) ( 24480 8140 ) ; |
| END SPECIALNETS |
| NETS 4 ; |
| - mprj2_vdd_logic1 ( PIN mprj2_vdd_logic1 ) ( mprj2_logic_high_lv X ) + USE SIGNAL ; |
| - mprj_vdd_logic1 ( PIN mprj_vdd_logic1 ) ( mprj_logic_high_lv X ) + USE SIGNAL ; |
| - mprj2_vdd_logic1_h ( mprj2_logic_high_lv A ) ( mprj2_logic_high_hvl HI ) + USE SIGNAL ; |
| - mprj_vdd_logic1_h ( mprj_logic_high_lv A ) ( mprj_logic_high_hvl HI ) + USE SIGNAL ; |
| END NETS |
| END DESIGN |