| commit | 08d9a76d636e986cdfdf0c4abe4668a827ccef98 | [log] [tgz] |
|---|---|---|
| author | Mohamed Kassem <mkkassem@users.noreply.github.com> | Wed Dec 02 04:01:55 2020 -0800 |
| committer | GitHub <noreply@github.com> | Wed Dec 02 04:01:55 2020 -0800 |
| tree | 5ca2dbff08d843342ff608dc80e146091c44332e | |
| parent | 8f79732050ff516fd8234190f8547e3900f3311a [diff] |
Update README.md
diff --git a/verilog/dv/README.md b/verilog/dv/README.md index 2f4a77d..1c316a7 100644 --- a/verilog/dv/README.md +++ b/verilog/dv/README.md
@@ -5,7 +5,7 @@ * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus <pre> -├── harness +├── caravel │ ├── mgmt_soc │ ├── user_proj_example └── wb_utests