1. b52d3b9 Merge pull request #20 from Manarabdelaty/fix_gl_testbenches by Manar · 4 years, 3 months ago
  2. f87daf5 Update caravel top-level views by Ahmed Ghazy · 4 years, 3 months ago
  3. 8717024 Update chip_io by Ahmed Ghazy · 4 years, 3 months ago
  4. acdf29d Removed duplicate GL testbenches by manarabdelaty · 4 years, 3 months ago
  5. ec0584c Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 4 years, 3 months ago
  6. 8e065f2 Update README.md by Mohamed Kassem · 4 years, 3 months ago
  7. 08d9a76 Update README.md by Mohamed Kassem · 4 years, 3 months ago
  8. 8f79732 Updated mgmt_core gl netlist by manarabdelaty · 4 years, 3 months ago
  9. 31c3465 First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 4 years, 3 months ago
  10. 9e230f8 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 4 years, 3 months ago
  11. 8839d6a Correct instance names that iverilog doesn't like by Ahmed Ghazy · 4 years, 3 months ago
  12. 19ffc21 Overwrote mgmt_core.v.gz from the source by Ahmed Ghazy · 4 years, 3 months ago
  13. 65065c6 Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years, 3 months ago
  14. a115bdd Added GL simulations by manarabdelaty · 4 years, 3 months ago
  15. c941188 [DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml by agorararmard · 4 years, 3 months ago
  16. 83fc685 [DATA] Signal-routed caravel (at 0 TR vios) by Ahmed Ghazy · 4 years, 3 months ago
  17. f0456f3 [DATA]sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped views by Ahmed Ghazy · 4 years, 3 months ago
  18. cdb18cd [DATA] mgmt_core re-hardened (1 short) by Ahmed Ghazy · 4 years, 3 months ago
  19. 1d1679d Wrap lsbufhv2lv to eliminate li1 pins at the top by Ahmed Ghazy · 4 years, 3 months ago
  20. 740defb [DATA] WIP mgmt_core rehardening by agorararmard · 4 years, 3 months ago
  21. 8b742b8 [DATA] reharden DFFRAM with the updated RTL by agorararmard · 4 years, 3 months ago
  22. 48f1adb [DATA] reharden digital pll by agorararmard · 4 years, 3 months ago
  23. 499896a [DATA] Update signal-routed version of caravel by Ahmed Ghazy · 4 years, 3 months ago
  24. 14645b9 Merge branch 'develop' into new_wrapper by ax3ghazy · 4 years, 3 months ago
  25. 886f48b Merge pull request #9 from ax3ghazy/develop-fork by ax3ghazy · 4 years, 3 months ago
  26. fe9c3bb Add two more missing USE_POWER_PINS guards by Ahmed Ghazy · 4 years, 3 months ago
  27. 27200e9 Add more missing USE_POWER_PINS by Ahmed Ghazy · 4 years, 3 months ago
  28. 365f5d7 Add a final user_id_programming by Ahmed Ghazy · 4 years, 3 months ago
  29. df4dd88 Minor RTL fixes, switching to wrapped GPIOV2 by Ahmed Ghazy · 4 years, 3 months ago
  30. bd9efb0 Merge branch 'master' into develop by Ahmed Ghazy · 4 years, 3 months ago
  31. 5b3db63 Merge pull request #8 from ax3ghazy/new_dimensions by ax3ghazy · 4 years, 3 months ago
  32. 678b0dd [DATA] re-compress data using the latest Makefile by Ahmed Ghazy · 4 years, 3 months ago
  33. bc03551 Split the high voltage part of the mgmt_protect.v module into its own by Tim Edwards · 4 years, 3 months ago
  34. c2f0867 Revert platform specific changes by Dan Rodrigues · 4 years, 3 months ago
  35. 4ce2d70 Testbench and Makefile fixes to get sims running by Dan Rodrigues · 4 years, 3 months ago
  36. 1070832 Added ngspice netlist and testbenches for the power-on-reset circuit. by Tim Edwards · 4 years, 3 months ago
  37. 4518c62 Corrected the logic in mgmt_protect; also corrected a problem in the la_test2 by Tim Edwards · 4 years, 3 months ago
  38. 43e5c60 Corrections to the management protection buffer block, and a couple of corrections by Tim Edwards · 4 years, 3 months ago
  39. 24c2085 Updates to the Makefiles for easier passing of user-specific variables, by Tim Edwards · 4 years, 3 months ago
  40. 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 3 months ago
  41. 10b5b0c [DATA] Push updated views as per the latest pad frame dimensions by Ahmed Ghazy · 4 years, 3 months ago
  42. 64c17e8 Add missing USE_POWER_PINS in other modules by Ahmed Ghazy · 4 years, 3 months ago
  43. 69663c7 Eliminate the two inverters at the top level by Ahmed Ghazy · 4 years, 3 months ago
  44. 336e082 add missing signals by Matt Venn · 4 years, 3 months ago
  45. 08cd6eb add default nettype none by Matt Venn · 4 years, 3 months ago
  46. d4cc669 [DATA] Add full runs of almost all blocks by Ahmed Ghazy · 4 years, 3 months ago
  47. 297a6cf Merge pull request #38 from Manarabdelaty/update_custom_mem by R. Timothy Edwards · 4 years, 3 months ago
  48. 8f13179 Updated custom memory by Manar · 4 years, 3 months ago
  49. 7c9cea0 Add sky130_fd_io__top_xres4v2 stub by Ahmed Ghazy · 4 years, 3 months ago
  50. 61dce92 Renamed lvs guard to use_power_pins by Manar · 4 years, 3 months ago
  51. ffe6cad Updated storage area by Manar · 4 years, 3 months ago
  52. e5ac00f Merge pull request #33 from Manarabdelaty/custom_mem by R. Timothy Edwards · 4 years, 3 months ago
  53. 50b0ea0 Merge pull request #32 from dan-rodrigues/user_proj_wb_ack by R. Timothy Edwards · 4 years, 3 months ago
  54. c3b9da4 Updated Makefiles to have lvs defined to use the power pins by Manar · 4 years, 3 months ago
  55. 68e0363 Added power pins to the custom memory cells by Manar · 4 years, 3 months ago
  56. 2517fa8 Add USE_CUSTOM_DFFRAM guard by Ahmed Ghazy · 4 years, 3 months ago
  57. b9a8c91 user_proj_example: fix wbs_ack_o wiring by Dan Rodrigues · 4 years, 3 months ago
  58. 5586f1b Add the custom DFF RAM by Ahmed Ghazy · 4 years, 4 months ago
  59. cd4cff7 Connected WB MI A port outputs to the wb bus by Manar · 4 years, 4 months ago
  60. 6bedda9 Added localparam for calculating mem address bits by Manar · 4 years, 4 months ago
  61. db08adb Updated default number of sram blocks for the user area by Manar · 4 years, 4 months ago
  62. cd41a1d Merge pull request #27 from ax3ghazy/conflict_warnings_fix by R. Timothy Edwards · 4 years, 4 months ago
  63. 706c312 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 4 months ago
  64. f46273f Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 4 months ago
  65. 55ec369 Connected storage area to mgmt_core by Manar · 4 years, 4 months ago
  66. 0cefb93 Seperated mgmt and user storage blocks base addresses by Manar · 4 years, 4 months ago
  67. 14f7ca0 Added storage area standalone rtl by Manar · 4 years, 4 months ago
  68. ec9b536 Removed storage area from mgmt_core by Manar · 4 years, 4 months ago
  69. d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 4 months ago
  70. 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 4 months ago
  71. 3a1e353 Fix another 36->37 typo in mem_tb.v by Ahmed Ghazy · 4 years, 4 months ago
  72. cfe7653 Corrected the timer testbenches for minor count differences due to by Tim Edwards · 4 years, 4 months ago
  73. 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 4 months ago
  74. ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 4 months ago
  75. e6eda80 Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 4 months ago
  76. 0b6219d Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 4 months ago
  77. 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 4 months ago
  78. 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 4 months ago
  79. 14d35ac Added synthesized memory (4kb) by Manar · 4 years, 4 months ago
  80. 05ad4fc Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 4 months ago
  81. 2a62066 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 4 months ago
  82. 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 4 months ago
  83. 98a7adc Removed cross bar switch port from mgmt core by Manar · 4 years, 4 months ago
  84. b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 4 months ago
  85. 268a90b Merge pull request #18 from ax3ghazy/params by R. Timothy Edwards · 4 years, 4 months ago
  86. 1c1b462 Merge pull request #17 from Manarabdelaty/release by R. Timothy Edwards · 4 years, 4 months ago
  87. 4533150 Merge pull request #16 from ax3ghazy/mkq by R. Timothy Edwards · 4 years, 4 months ago
  88. f757546 Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 4 years, 4 months ago
  89. 2adba10 Fix typos in parameter names by Ahmed Ghazy · 4 years, 4 months ago
  90. 6d9739d Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 4 months ago
  91. 7ea4895 Fixed sysctrl unit test by Manar · 4 years, 4 months ago
  92. ba04b40 Allow PDK_PATH to be user-specified by Ahmed Ghazy · 4 years, 4 months ago
  93. 81d5a89 Move wire declarations before they're first used by Ahmed Ghazy · 4 years, 4 months ago
  94. 63c933f Removed VCD and hex files, which should not be in the repository. by Tim Edwards · 4 years, 4 months ago
  95. b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 4 months ago
  96. 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 4 months ago
  97. e2ef673 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 4 months ago
  98. 4c73335 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 4 months ago
  99. 7a8cbb1 Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 4 months ago
  100. 53d9218 Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 4 months ago