Updated TB
- Gl sim passes
diff --git a/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v b/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v
index 8a85b7e..3ef1c4e 100644
--- a/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v
+++ b/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v
@@ -1,5 +1,9 @@
module DFFRAM_beh #( parameter COLS=1)
(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+ `endif
CLK,
WE,
EN,
@@ -9,6 +13,11 @@
);
localparam A_WIDTH = 8+$clog2(COLS);
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+ `endif
+
input wire CLK;
input wire [3:0] WE;
input wire EN;
@@ -29,4 +38,4 @@
else
Do <= 32'b0;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index b8e9719..c324056 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -40,8 +40,8 @@
-I $(PDK_PATH) -I .. -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ iverilog -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DGL_UA -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I .. -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index ea44637..35f2cd1 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -27,18 +27,30 @@
`include "sst26wf080b.v"
`include "23LC512.v"
+`include "caravel.v"
`ifdef SIM
`ifdef FAST
- `define NO_DFFRAM
+ `define USE_DFFRAM_BEH
`define NO_HC_CACHE
`include "DFFRAM_beh.v"
`else
- `include "user_project/IPs/DFFRAM.v"
- `include "user_project/IPs/DFFRAMBB.v"
+ `ifndef GL_UA
+ `include "user_project/IPs/DFFRAM_4K.v"
+ `include "user_project/IPs/DFFRAMBB.v"
+ `include "user_project/IPs/DMC_32x16HC.v"
+ `endif
`endif
+`ifdef GL_UA
+ `include "gl/user_project/gl/apb_sys_0.v"
+ `include "gl/user_project/gl/DFFRAM_4K.v"
+ `include "gl/user_project/gl/DMC_32x16HC.v"
+ `include "gl/user_project/gl/NfiVe32_SYS.v"
+ `include "gl/user_project/gl/user_project_wrapper.v"
+`else
+
`include "user_project/AHB_sys_0/AHBlite_sys_0.v"
`include "user_project/AHB_sys_0/AHBlite_bus0.v"
@@ -75,8 +87,7 @@
`include "user_project/NfiVe32.v"
`include "user_project/soc_core.v"
-`include "caravel.v"
-
+`endif
`endif
module io_ports_tb;
