Updated timer testbench checks to account for csb io
diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile index 641a453..a62f01c 100644 --- a/verilog/dv/caravel/mgmt_soc/timer/Makefile +++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -1,5 +1,6 @@ FIRMWARE_PATH = ../.. -RTL_PATH = ../../../../rtl +VERILOG_PATH = ../../../.. +RTL_PATH = $(VERILOG_PATH)/rtl IP_PATH = ../../../../ip BEHAVIOURAL_MODELS = ../../ @@ -7,6 +8,8 @@ GCC_PREFIX?=riscv32-unknown-elf PDK_PATH?=/ef/tech/SW/sky130A +SIM?=RTL + .SUFFIXES: PATTERN = timer
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer.c b/verilog/dv/caravel/mgmt_soc/timer/timer.c index c3a8dc4..0ebd8cb 100644 --- a/verilog/dv/caravel/mgmt_soc/timer/timer.c +++ b/verilog/dv/caravel/mgmt_soc/timer/timer.c
@@ -55,7 +55,7 @@ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; + // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v index acb6798..64cf850 100644 --- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v +++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -62,6 +62,8 @@ assign checkbits = mprj_io[37:32]; assign countbits = mprj_io[31:0]; + assign mprj_io[3] = 1'b1; // Force CSB high. + wire flash_csb; wire flash_clk; wire flash_io0; @@ -78,32 +80,32 @@ `endif /* Add checks here */ wait(checkbits == 6'h01); - $display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits); - if(countbits !== 32'hdcba7cf3) begin + $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits); + if(countbits !== 32'hdcba7cfb) begin $display("Monitor: Test Timer Failed"); $finish; end wait(checkbits == 6'h02); - $display(" countbits = 0x%x (should be 0x11)", countbits); - if(countbits !== 32'h11) begin + $display(" countbits = 0x%x (should be 0x19)", countbits); + if(countbits !== 32'h19) begin $display("Monitor: Test Timer Failed"); $finish; end wait(checkbits == 6'h03); $display(" countbits = %x (should be 0x0f)", countbits); - if(countbits !== 32'h0f) begin + if(countbits !== ((32'h0f) | (3'b100))) begin $display("Monitor: Test Timer Failed"); $finish; end wait(checkbits == 6'h04); $display(" countbits = %x (should be 0x0f)", countbits); - if(countbits !== 32'h0f) begin + if(countbits !== ((32'h0f) | (3'b100))) begin $display("Monitor: Test Timer Failed"); $finish; end wait(checkbits == 6'h05); - $display(" countbits = %x (should be 0x12b4)", countbits); - if(countbits !== 32'h12b4) begin + $display(" countbits = %x (should be 0x12bc)", countbits); + if(countbits !== 32'h12bc) begin $display("Monitor: Test Timer Failed"); $finish; end
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2.c b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c index a8c65e0..aa98cce 100644 --- a/verilog/dv/caravel/mgmt_soc/timer2/timer2.c +++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
@@ -56,7 +56,7 @@ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; + // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v index 750635d..96aab4e 100644 --- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v +++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -78,14 +78,14 @@ `endif /* Add checks here */ wait(checkbits == 6'h01); - $display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits); - if(countbits !== 32'hdcba7cf3) begin + $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits); + if(countbits !== 32'hdcba7cfb) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 6'h02); - $display(" countbits = 0x%x (should be 0x11)", countbits); - if(countbits !== 32'h11) begin + $display(" countbits = 0x%x (should be 0x19)", countbits); + if(countbits !== 32'h19) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end @@ -102,22 +102,22 @@ $finish; end wait(checkbits == 6'h05); - $display(" countbits = %x (should be 0x12b4)", countbits); - if(countbits !== 32'h12b4) begin + $display(" countbits = %x (should be 0x12bc)", countbits); + if(countbits !== 32'h12bc) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 6'h06); - $display(" countbits = %x (should be 0x0055)", countbits); - if(countbits !== 32'h0055) begin + $display(" countbits = %x (should be 0x005d)", countbits); + if(countbits !== 32'h005d) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 6'h07); - $display(" countbits = %x (should be 0x0000)", countbits); - if(countbits !== 32'h0000) begin + $display(" countbits = %x (should be 0x0008)", countbits); + if(countbits !== 32'h0008) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end @@ -130,8 +130,8 @@ end wait(checkbits == 6'h10); - $display(" countbits = %x (should be 0x0002)", countbits); - if(countbits !== 32'h0002) begin + $display(" countbits = %x (should be 0x000a)", countbits); + if(countbits !== 32'h000a) begin $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end @@ -170,6 +170,8 @@ assign VDD3V3 = power1; assign VDD1V8 = power2; assign VSS = 1'b0; + + assign mprj_io[3] = 1'b1; // Force CSB high. // These are the mappings of mprj_io GPIO pads that are set to // specific functions on startup: