(1) Added a wrapper interface between the top level verilog and the user project
example.
(2) Corrected broken directory references in README.md
(3) Added the caravel.pdf document (first draft, mostly just figures and no text).
diff --git a/README.md b/README.md
index 24c331e..7337455 100644
--- a/README.md
+++ b/README.md
@@ -13,17 +13,18 @@
- Control the Mega Project power supply
The memory map of the management SoC is given below <br>
+(NOTE: This needs updating; see the [README file](verilog/rtl/README) for an updated list.)
<img src="/doc/mgmt_soc_memory_map.png" width="40%" height="40%">
## Mega Project Area
-This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???).
-The repoo contains a [sample mega project](/verilog/rtl/mprj_counter.v) that contains a binary 32-bit up counter. </br>
+This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel datasheet](doc/caravel.pdf) for details.
+The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
<p align=”center”>
<img src="/doc/counter_32.png" width="50%" height="50%">
</p>
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/harness/mprj_counter/io_ports).
-2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/harness/mprj_counter/la_test1).
-3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/harness/mprj_counter/la_test2).
+1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/mprj_counter/io_ports).
+2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/mprj_counter/la_test1).
+3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/mprj_counter/la_test2).
