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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-032 / a9446f961c96ed57b02986c3a664e0b36c5b51bb / . / verilog / dv / caravel / user_proj_example
tree: 3e623e61ea647fc041747188dfc54d853f1d719c [path history] [tgz]
  1. io_ports/
  2. sw_n5/
  3. 23LC512.v
  4. DFFRAM_beh.v
  5. files.list
  6. files_fast_sim.list
  7. Makefile
  8. README.md
  9. sst26wf080b.v
verilog/dv/caravel/user_proj_example/README.md

Mega-Project Counter Tests

The directory includes three tests for the counter mega-project example:

  1. IO Ports Test:

    • Configures the user space lower 8 IO pins as outputs
    • Observes the counter value through the configured pins in the testbench

  2. Logic Analyzer Test 1:

    • Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value
    • Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value
    • Flags when counter value exceeds 500 through the management SoC gpio
    • Outputs message to the UART when the test concludes successfuly

  3. Logic Analyzer Test 2:

    • Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values
    • Provides counter clock and monitors the counter value after five clock cycles