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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-032/55ec369c02acdf302e786516e00ec777461283ca
commit
55ec369c02acdf302e786516e00ec777461283ca
[log] [tgz]
author
Manar <manarabdelatty@aucegypt.edu>
Fri Oct 30 16:32:18 2020 +0200
committer
Manar <manarabdelatty@aucegypt.edu>
Fri Oct 30 16:32:18 2020 +0200
tree
c1d6b9b87a402480e4e6cfc99f2c53e15fe2b80f
parent
0cefb93da1dd65b27279488f6ffdef5aca0bc00d [diff]
Connected storage area to mgmt_core

- Added wishbone bridge in mgmt_soc to contain all logic needed for the core to interface
with the storage area
- Updated defs.h with the base addresses for the storage blocks
- Added R/W test for the mgmt blocks
8 files changed
tree: c1d6b9b87a402480e4e6cfc99f2c53e15fe2b80f
  1. def/
  2. doc/
  3. gds/
  4. lef/
  5. mag/
  6. openlane/
  7. scripts/
  8. verilog/
  9. LICENSE
  10. README.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.