Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-032 / 5bffd11044e6f494cfab4d73d2cdfd77d843990d / . / verilog / dv / caravel / user_proj_example
tree: 1391bc5a6ed3268024bd249dd4d5d234e40de6c5 [path history] [tgz]
  1. io_ports/
  2. la_test1/
  3. la_test2/
  4. sw_n5/
  5. 23LC512.v
  6. DFFRAM_beh.v
  7. files.list
  8. files_fast_sim.list
  9. Makefile
  10. README.md
  11. sst26wf080b.v
verilog/dv/caravel/user_proj_example/README.md

Mega-Project Counter Tests

The directory includes three tests for the counter mega-project example:

  1. IO Ports Test:

    • Configures the user space lower 8 IO pins as outputs
    • Observes the counter value through the configured pins in the testbench

  2. Logic Analyzer Test 1:

    • Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value
    • Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value
    • Flags when counter value exceeds 500 through the management SoC gpio
    • Outputs message to the UART when the test concludes successfuly

  3. Logic Analyzer Test 2:

    • Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values
    • Provides counter clock and monitors the counter value after five clock cycles