add missing signals

verilog/dv/wb_utests/uart_wb/uart_wb_tb.v

diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
index acfd8ad..56b93f6 100644
--- a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -19,6 +19,9 @@
 
 	wire wb_ack_o;
 	wire [31:0] wb_dat_o;
+
+    wire tbuart_rx;
+	wire ser_rx;
   
     initial begin
         wb_clk_i = 0; 
@@ -147,4 +150,4 @@
 		.ser_rx(ser_rx)
 	);
 
-endmodule
\ No newline at end of file
+endmodule

verilog/rtl/simpleuart.v

diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 62a3ea6..66e1915 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -45,6 +45,7 @@
     wire [31:0] simpleuart_reg_div_do;
     wire [31:0] simpleuart_reg_dat_do;
     wire [31:0] simpleuart_reg_cfg_do;
+    wire reg_dat_wait;
 
     wire resetn = ~wb_rst_i;
     wire valid = wb_stb_i && wb_cyc_i; 
@@ -126,6 +127,8 @@
     reg [31:0] send_divcnt;
     reg send_dummy;
 
+    wire reg_ena_do;
+
     assign reg_div_do = cfg_divider;
     assign reg_ena_do = {31'd0, enabled};