Fix typos in parameter names

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8b143db..841ef64 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -58,8 +58,8 @@
     /*--------------------------------------*/
 
     user_proj_example #(
-	.IO_PADS(`MPRJ_IO_PADS),
-	.PWR_PADS(`MPRJ_PWR_PADS)
+	.IO_PADS(IO_PADS),
+	.PWR_PADS(PWR_PADS)
     ) mprj ( 
 	.vdda1(vdda1),	// User area 1 3.3V power
 	.vdda2(vdda2),	// User area 2 3.3V power