Added final summary report
diff --git a/doc/final_summary_report.csv b/doc/final_summary_report.csv
new file mode 100644
index 0000000..0f7706e
--- /dev/null
+++ b/doc/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/home/cse-p07-2179-gaa/work/N5_SoC/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,0h5m23s,10.2784,316.4889476961395,632.977895392279,0,1311.13,3253,0,0,0,0,0,0,0,49,0,-1,864931,34703,0.0,0.0,0.0,-7.1,-0.42,0.0,0.0,0.0,-942.83,-27.17,826654252,0.0,9.36,7.57,8.07,2.64,-1,3325,3943,997,1615,0,0,0,3253,83,2,19,26,159,53,68,814,709,666,13,7318,34548,0,41866,95.96928982725528,10.42,10,3,5,50,1,153.6,153.18,0.35,0.4,sky130_fd_sc_hd,8,4
