commit 14d35ac952caec3f6ff1a06b25a22cbef70d526d
author Manar <manarabdelatty@aucegypt.edu> Wed Oct 21 22:47:15 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Wed Oct 21 22:47:15 2020 +0200
tree 08e7b35f37f5b7a919a3e3cc9e5192f449a2ec4c
parent 5f968550ba00cc2839093085ca89efa092cefb81

Added synthesized memory (4kb)

verilog/rtl/mem_wb.v

diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index bacf52c..882f1c7 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -93,12 +93,12 @@
     
     /* Using Port 0 Only - Size: 1KB, 256x32 bits */
     //sram_1rw1r_32_256_8_scn4m_subm 
-    sram_1rw1r_32_8192_8_sky130 SRAM(
+    sram_1rw1r_32_256_8_sky130 SRAM(
             .clk0(clk), 
             .csb0(~ena), 
             .web0(~|wen),
             .wmask0(wen),
-            .addr0(addr[12:0]),
+            .addr0(addr[7:0]),
             .din0(wdata),
             .dout0(rdata)
       );