harness phase1 initial commit
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..5a3fba1
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,13 @@
+# DV Tests
+
+Organized into two subdirectories:
+ * harness: contains tests for both the mangement SoC and the mega-project.
+ * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
+
+<pre>
+├── harness
+│ ├── mgmt_soc
+│ ├── mprj_counter
+└── wb_utests
+</pre>
+
diff --git a/verilog/dv/harness/mgmt_soc/defs.h b/verilog/dv/harness/defs.h
similarity index 66%
rename from verilog/dv/harness/mgmt_soc/defs.h
rename to verilog/dv/harness/defs.h
index e2d777f..d9eec3a 100644
--- a/verilog/dv/harness/mgmt_soc/defs.h
+++ b/verilog/dv/harness/defs.h
@@ -12,15 +12,17 @@
extern uint32_t flashio_worker_begin;
extern uint32_t flashio_worker_end;
-// IOs: UART (0x2000_0000), GPIO (0x2100_0000), LA (0x2200_0000)
+// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+// GPIO (0x2100_0000)
#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
+// Logic Analyzer (0x2200_0000)
#define reg_la0_data (*(volatile uint32_t*)0x22000000)
#define reg_la1_data (*(volatile uint32_t*)0x22000004)
#define reg_la2_data (*(volatile uint32_t*)0x22000008)
@@ -31,6 +33,49 @@
#define reg_la2_ena (*(volatile uint32_t*)0x22000018)
#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
+// Mega Project Control (0x2300_0000)
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000000)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000004)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000008)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x2300000c)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000010)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000014)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000018)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x2300001c)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000020)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000024)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000028)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x2300002c)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000030)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000034)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000038)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x2300003c)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000040)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000044)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000048)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x2300004c)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000050)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000054)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000058)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x2300005c)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000060)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000064)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000068)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x2300006c)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000070)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000074)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000078)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x2300007c)
+
+// Mega Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
// Flash Control SPI Configuration (2D00_0000)
#define reg_spictrl (*(volatile uint32_t*)0x2D000000)
diff --git a/verilog/dv/harness/mgmt_soc/Makefile b/verilog/dv/harness/mgmt_soc/Makefile
index c934af3..9f185c0 100644
--- a/verilog/dv/harness/mgmt_soc/Makefile
+++ b/verilog/dv/harness/mgmt_soc/Makefile
@@ -3,7 +3,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = gpio mem uart perf hkspi sysctrl xbar
+PATTERNS = gpio mem uart perf hkspi sysctrl mprj_ctrl
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/harness/mgmt_soc/gpio/Makefile b/verilog/dv/harness/mgmt_soc/gpio/Makefile
index e9253c0..719e42b 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/harness/mgmt_soc/gpio/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
.SUFFIXES:
PATTERN = gpio
@@ -7,14 +12,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio.c b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
index 17a4885..0d9caf5 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
index c20ba26..35c8cf3 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
@@ -20,7 +20,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
module gpio_tb;
@@ -151,7 +151,7 @@
assign VSS = 1'b0;
assign VDD1V8 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/Makefile b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
index 2850baa..07ea208 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
.SUFFIXES:
PATTERN = hkspi
@@ -7,14 +12,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
-
+
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< /dev/stdout | sed -e '1 s/@10000000/@00000000/; 2,65537 d;' > $@
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
index d572727..a415214 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
index 0edc43d..09d1dab 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
@@ -4,7 +4,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
`include "tbuart.v"
@@ -167,31 +167,31 @@
write_byte(8'h00); // Address (register 3 = product ID)
read_byte(tbdata);
$display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata != 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
- if(tbdata != 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
+ if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
read_byte(tbdata);
$display("Read register 3 = 0x%02x (should be 0x05)", tbdata);
- if(tbdata != 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 4 = 0x%02x (should be 0x07)", tbdata);
- if(tbdata != 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 5 = 0x%02x (should be 0x01)", tbdata);
- if(tbdata != 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 8 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
end_csb();
@@ -209,7 +209,7 @@
assign VSS = 1'b0;
assign VDD1V8 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mem/Makefile b/verilog/dv/harness/mgmt_soc/mem/Makefile
index d63df1b..fc85291 100644
--- a/verilog/dv/harness/mgmt_soc/mem/Makefile
+++ b/verilog/dv/harness/mgmt_soc/mem/Makefile
@@ -1,4 +1,9 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
.SUFFIXES:
PATTERN = mem
@@ -8,14 +13,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem.c b/verilog/dv/harness/mgmt_soc/mem/mem.c
index 0bff65d..31d0f75 100644
--- a/verilog/dv/harness/mgmt_soc/mem/mem.c
+++ b/verilog/dv/harness/mgmt_soc/mem/mem.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
index 09bb0a7..0d0c93d 100644
--- a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
@@ -20,7 +20,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
module mem_tb;
@@ -146,7 +146,7 @@
assign VDD3V3 = 1'b1;
assign VDD1V8 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..3b396d7
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T, $(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..97b8148
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,38 @@
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Mega-Project IO Control Test
+*/
+
+void main()
+{
+ /* All GPIO pins are configured to be output */
+ reg_gpio_data = 0;
+ reg_gpio_ena = 0x0000;
+
+ // start test
+ reg_gpio_data = 0xA040;
+
+ // Write to IO Control
+ reg_mprj_io_0 = 0x004F;
+ if(0x004F != reg_mprj_io_0) reg_gpio_data = 0xAB40;
+ reg_gpio_data = 0xAB41;
+
+ // Write to IO Control
+ reg_mprj_io_1 = 0x005F;
+ if(0x005F != reg_mprj_io_1) reg_gpio_data = 0xAB50;
+ reg_gpio_data = 0xAB51;
+
+ // Write to IO Control
+ reg_mprj_io_2 = 0x006F;
+ if(0x006F != reg_mprj_io_2) reg_gpio_data = 0xAB60;
+ reg_gpio_data = 0xAB61;
+
+ // Write to IO Control
+ reg_mprj_io_3 = 0xF0F5;
+ if(0xF0F5 != reg_mprj_io_3) reg_gpio_data = 0xAB70;
+ reg_gpio_data = 0xAB71;
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
similarity index 60%
rename from verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
rename to verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index b9357f0..bcbbe12 100644
--- a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,10 +1,10 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
-module xbar_tb;
+module mprj_ctrl_tb;
reg XCLK;
reg XI;
@@ -22,6 +22,10 @@
wire flash_io3;
wire SDO;
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
always #10 XCLK <= (XCLK === 1'b0);
always #220 XI <= (XI === 1'b0);
@@ -31,57 +35,41 @@
end
initial begin
- $dumpfile("xbar_tb.vcd");
- $dumpvars(0, xbar_tb);
+ $dumpfile("mprj_ctrl_tb.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
repeat (25) begin
repeat (1000) @(posedge XCLK);
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Crossbar Switch (RTL) Failed");
- $display("%c[0m", 27);
+ $display ("Monitor: Timeout, Test Mega-Project (RTL) Failed");
+ $display("%c[0m",27);
$finish;
end
always @(gpio) begin
if(gpio == 16'hA040) begin
- $display("Crossbar Switch Test started");
+ $display("Mega-Project control Test started");
end
else if(gpio == 16'hAB40) begin
$display("%c[1;31m",27);
- $display("Monitor: Crossbar test R/W from QSPI CTRL slave failed.");
+ $display("Monitor: IO control R/W failed");
$display("%c[0m",27);
$finish;
end
else if(gpio == 16'hAB41) begin
- $display("Monitor: Crossbar test R/W from QSPI CTRL slave passed");
+ $display("Monitor: IO control R/W passed");
end
else if(gpio == 16'hAB50) begin
$display("%c[1;31m",27);
- $display("Monitor: Crossbar test R/W from storage area failed.");
+ $display("Monitor: power control R/W failed");
$display("%c[0m",27);
$finish;
end else if(gpio == 16'hAB51) begin
- $display("Monitor: Crossbar test R/W from storage area passed.");
- end
- else if(gpio == 16'hAB60) begin
- $display("%c[1;31m",27);
- $display("Monitor: Crossbar test R/W from mega project 1st slave failed.");
- $display("%c[0m",27);
- $finish;
- end else if(gpio == 16'hAB61) begin
- $display("Monitor: Crossbar test R/W from mega project 1st slave passed.");
- end
- else if(gpio == 16'hAB70) begin
- $display("%c[1;31m",27);
- $display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
- $display("%c[0m",27);
- $finish;
- end else if(gpio == 16'hAB71) begin
- $display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
- $display("Monitor: Timeout, Test Crossbar Switch (RTL) Passed.");
+ $display("Monitor: power control R/W passed");
+ $display("Monitor: Mega-Project control (RTL) test passed.");
$finish;
- end
+ end
end
initial begin
@@ -107,11 +95,11 @@
assign VDD1V8 = 1'b1;
assign VDD3V3 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
- .xi (XI),
+ .xi (XI),
.xclk (XCLK),
.SDI (SDI),
.SDO (SDO),
@@ -137,7 +125,7 @@
);
spiflash #(
- .FILENAME("xbar.hex")
+ .FILENAME("mprj_ctrl.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
diff --git a/verilog/dv/harness/mgmt_soc/perf/Makefile b/verilog/dv/harness/mgmt_soc/perf/Makefile
index dad371f..b24bd84 100644
--- a/verilog/dv/harness/mgmt_soc/perf/Makefile
+++ b/verilog/dv/harness/mgmt_soc/perf/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
.SUFFIXES:
PATTERN = perf
@@ -7,14 +12,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf.c b/verilog/dv/harness/mgmt_soc/perf/perf.c
index 4dc34b1..bd94f5d 100644
--- a/verilog/dv/harness/mgmt_soc/perf/perf.c
+++ b/verilog/dv/harness/mgmt_soc/perf/perf.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
index edd10ba..3e5edbc 100644
--- a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
@@ -20,7 +20,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
module striVe_perf_tb;
@@ -122,7 +122,7 @@
assign VDD1V8 = 1'b1;
assign VDD3V3 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3 ),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
index 0b43365..a4a14a6 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
.SUFFIXES:
PATTERN = sysctrl
@@ -7,14 +12,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
index a4a6762..023a08c 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
index d1e4439..4932e0d 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
module sysctrl_tb;
@@ -127,7 +127,7 @@
assign VDD1V8 = 1'b1;
assign VDD3V3 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/uart/Makefile b/verilog/dv/harness/mgmt_soc/uart/Makefile
index 057be64..3ce3936 100644
--- a/verilog/dv/harness/mgmt_soc/uart/Makefile
+++ b/verilog/dv/harness/mgmt_soc/uart/Makefile
@@ -1,4 +1,8 @@
# ---- Test patterns for project striVe ----
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
.SUFFIXES:
@@ -9,14 +13,14 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
%.vcd: %.vvp
vvp $<
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart.c b/verilog/dv/harness/mgmt_soc/uart/uart.c
index fe362f8..bf21144 100644
--- a/verilog/dv/harness/mgmt_soc/uart/uart.c
+++ b/verilog/dv/harness/mgmt_soc/uart/uart.c
@@ -1,19 +1,5 @@
-#include "../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
- if (c == '\n')
- putchar('\r');
- reg_uart_data = c;
-}
-
-void print(const char *p)
-{
- while (*p)
- putchar(*(p++));
-}
+#include "../../defs.h"
+#include "../stub.c"
// --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
index 56c76f2..c031659 100644
--- a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
@@ -20,7 +20,7 @@
`timescale 1 ns / 1 ps
-`include "harness.v"
+`include "harness_chip.v"
`include "spiflash.v"
`include "tbuart.v"
@@ -105,7 +105,7 @@
assign VDD1V8 = 1'b1;
assign VDD3V3 = 1'b1;
- harness uut (
+ harness_chip uut (
.vdd (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/xbar/Makefile b/verilog/dv/harness/mgmt_soc/xbar/Makefile
deleted file mode 100644
index 5302d06..0000000
--- a/verilog/dv/harness/mgmt_soc/xbar/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-.SUFFIXES:
-
-PATTERN = xbar
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c ../sections.lds ../start.s
- /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
-
-%.hex: %.elf
- /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar.c b/verilog/dv/harness/mgmt_soc/xbar/xbar.c
deleted file mode 100644
index 5565f1f..0000000
--- a/verilog/dv/harness/mgmt_soc/xbar/xbar.c
+++ /dev/null
@@ -1,41 +0,0 @@
-#include "../defs.h"
-
-// --------------------------------------------------------
-
-/*
- Crosbbar Switch Test
- - Reads default value of SPI-Controlled registers
- - Flags failure/success using gpio
-*/
-void main()
-{
- int i;
-
- reg_gpio_data = 0;
- reg_gpio_ena = 0x0000;
-
- // start test
- reg_gpio_data = 0xA040;
-
- // Write & Read from QSPI CTRL Slave
- qspi_ctrl_slave = 0xA0A1;
- if(0xA0A1 != qspi_ctrl_slave) reg_gpio_data = 0xAB40;
- reg_gpio_data = 0xAB41;
-
- // Write & Read from storage area Slave
- storage_area_slave = 0xB0B1;
- if(0xB0B1 != storage_area_slave) reg_gpio_data = 0xAB50;
- reg_gpio_data = 0xAB51;
-
- // Write & Read from Mega Project 1st slave
- mega_any_slave1 = 0xC0C1;
- if(0xC0C1 != mega_any_slave1) reg_gpio_data = 0xAB60;
- reg_gpio_data = 0xAB61;
-
- // Write & Read from Mega Project 1st slave
- mega_any_slave2 = 0xD0D1;
- if(0xD0D1 != mega_any_slave2) reg_gpio_data = 0xAB70;
- reg_gpio_data = 0xAB71;
-
-}
-
diff --git a/verilog/dv/wb/Makefile b/verilog/dv/harness/mprj_counter/Makefile
similarity index 80%
rename from verilog/dv/wb/Makefile
rename to verilog/dv/harness/mprj_counter/Makefile
index 7b0e09b..6b5248c 100644
--- a/verilog/dv/wb/Makefile
+++ b/verilog/dv/harness/mprj_counter/Makefile
@@ -3,7 +3,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = gpio_wb intercon_wb spimemio_wb uart_wb crossbar_wb arbiter_wb
+PATTERNS = io_ports la_test1 la_test2
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/harness/mprj_counter/README.md b/verilog/dv/harness/mprj_counter/README.md
new file mode 100644
index 0000000..16afd68
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/README.md
@@ -0,0 +1,20 @@
+# Mega-Project Counter Tests
+
+The directory includes three tests for the counter mega-project example:
+
+1) IO Ports Test:
+
+ * Configures the Mega-project lower 8 IO pins as outputs
+ * Observes the counter value through the configured pins in the testbench
+
+ 2) Logic Analyzer Test 1:
+
+ * Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value
+ * Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value
+ * Flags when counter value exceeds 500 through the management SoC gpio
+ * Outputs message to the UART when the test concludes successfuly
+
+ 3) Logic Analyzer Test 2:
+
+ * Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values
+ * Provides counter clock and monitors the counter value after five clock cycles
diff --git a/verilog/dv/harness/mprj_counter/io_ports/Makefile b/verilog/dv/harness/mprj_counter/io_ports/Makefile
new file mode 100644
index 0000000..8f0cd33
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+.SUFFIXES:
+
+PATTERN = io_ports
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports.c b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c
new file mode 100644
index 0000000..e4b9cf4
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c
@@ -0,0 +1,40 @@
+#include "../../defs.h"
+
+/*
+ IO Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+ /*
+ IO Control Registers
+
+ | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x060E)
+ | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
+ | 110 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x010F)
+ | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
+ | 001 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
+
+ */
+
+ // Configure lower 8-IOs as output
+ // Observe counter value in the testbench
+ reg_mprj_io_0 = 0x060E;
+ reg_mprj_io_1 = 0x060E;
+ reg_mprj_io_2 = 0x060E;
+ reg_mprj_io_3 = 0x060E;
+ reg_mprj_io_4 = 0x060E;
+ reg_mprj_io_5 = 0x060E;
+ reg_mprj_io_6 = 0x060E;
+ reg_mprj_io_7 = 0x060E;
+
+}
+
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
new file mode 100644
index 0000000..e30f139
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
@@ -0,0 +1,139 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+
+module io_ports_tb;
+ reg XCLK;
+ reg XI;
+
+ reg real adc_h, adc_l;
+ reg real adc_0, adc_1;
+ reg real comp_n, comp_p;
+ reg SDI, CSB, SCK, RSTB;
+ wire SDO;
+
+ wire [15:0] gpio;
+ wire [31:0] mprj_io;
+ wire [7:0] mprj_io_0;
+
+ assign mprj_io_0 = mprj_io[7:0];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 XCLK <= (XCLK === 1'b0);
+ always #220 XI <= (XI === 1'b0);
+
+ initial begin
+ XI = 0;
+ XCLK = 0;
+ end
+
+ initial begin
+ $dumpfile("io_ports.vcd");
+ $dumpvars(0, io_ports_tb);
+
+ // Repeat cycles of 1000 XCLK edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge XCLK);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ // Observe Output pins [7:0]
+ wait(mprj_io_0==8'h01);
+ wait(mprj_io_0==8'h02);
+ wait(mprj_io_0==8'h03);
+ wait(mprj_io_0==8'h04);
+ wait(mprj_io_0==8'h05);
+ wait(mprj_io_0==8'h06);
+ wait(mprj_io_0==8'h07);
+ wait(mprj_io_0==8'h08);
+ wait(mprj_io_0==8'h09);
+ wait(mprj_io_0==8'h0A);
+ wait(mprj_io_0==8'hFF);
+ wait(mprj_io_0==8'h00);
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ CSB <= 1'b0; // Apply CSB to start transmission
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ end
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ assign VSS = 1'b0;
+ assign VDD1V8 = 1'b1;
+ assign VDD3V3 = 1'b1;
+
+ harness_chip uut (
+ .vdd (VDD3V3),
+ .vdd1v8 (VDD1V8),
+ .vss (VSS),
+ .xi (XI),
+ .xclk (XCLK),
+ .SDI (SDI),
+ .SDO (SDO),
+ .CSB (CSB),
+ .SCK (SCK),
+ .ser_rx (1'b0),
+ .ser_tx (tbuart_rx),
+ .irq (1'b0),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .flash_io2(flash_io2),
+ .flash_io3(flash_io3),
+ .adc_high (adc_h),
+ .adc_low (adc_l),
+ .adc0_in (adc_0),
+ .adc1_in (adc_1),
+ .RSTB (RSTB),
+ .comp_inp (comp_p),
+ .comp_inn (comp_n)
+ );
+
+ spiflash #(
+ .FILENAME("io_ports.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(flash_io2),
+ .io3(flash_io3)
+ );
+
+endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test1/Makefile b/verilog/dv/harness/mprj_counter/la_test1/Makefile
new file mode 100644
index 0000000..da557a6
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+.SUFFIXES:
+
+PATTERN = la_test1
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1.c b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c
new file mode 100644
index 0000000..1404a1e
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c
@@ -0,0 +1,51 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+/*
+ MPRJ Logic Analyzer Test:
+ - Observes counter value through LA probes [31:0]
+ - Sets counter initial value through LA probes [63:32]
+ - Flags when counter value exceeds 500 through the management SoC gpio
+ - Outputs message to the UART when the test concludes successfuly
+*/
+
+void main()
+{
+
+ // All GPIO pins are configured to be output
+ // Used to flad the start/end of a test
+ reg_gpio_data = 0;
+ reg_gpio_ena = 0x0000;
+
+ // Set UART clock to 64 kbaud
+ reg_uart_clkdiv = 625;
+
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [63:32] as outputs from the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0x00000000; // [63:32]
+ reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Flag start of the test
+ reg_gpio_data = 0xAB40;
+
+ // Set Counter value to zero through LA probes [63:32]
+ reg_la1_data = 0x00000000;
+
+ // Configure LA probes from [63:32] as inputs to disable counter write
+ reg_la1_ena = 0xFFFFFFFF;
+
+ while (1) {
+ if (reg_la0_data > 0x1F4) {
+ reg_gpio_data = 0xAB41;
+ break;
+ }
+ }
+ print("\n");
+ print("Monitor: Test 2 Passed\n\n");
+ reg_gpio_data = 0xAB51;
+}
+
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
new file mode 100644
index 0000000..1eb6885
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
@@ -0,0 +1,132 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module la_test1_tb;
+ reg XCLK;
+ reg XI;
+
+ reg real adc_h, adc_l;
+ reg real adc_0, adc_1;
+ reg real comp_n, comp_p;
+ reg SDI, CSB, SCK, RSTB;
+ wire SDO;
+
+ wire [15:0] gpio;
+ wire [31:0] mprj_io;
+ wire [7:0] mprj_io_0;
+
+ assign mprj_io_0 = mprj_io[7:0];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 XCLK <= (XCLK === 1'b0);
+ always #220 XI <= (XI === 1'b0);
+
+ initial begin
+ XI = 0;
+ XCLK = 0;
+ end
+
+ initial begin
+ $dumpfile("la_test1.vcd");
+ $dumpvars(0, la_test1_tb);
+
+ // Repeat cycles of 1000 XCLK edges as needed to complete testbench
+ repeat (200) begin
+ repeat (1000) @(posedge XCLK);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(gpio == 16'hAB40);
+ $display("LA Test 1 started");
+ wait(gpio == 16'hAB41);
+ wait(gpio == 16'hAB51);
+ #10000;
+ $finish;
+ end
+
+ initial begin
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ CSB <= 1'b0; // Apply CSB to start transmission
+ end
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ assign VSS = 1'b0;
+ assign VDD1V8 = 1'b1;
+ assign VDD3V3 = 1'b1;
+
+ harness_chip uut (
+ .vdd (VDD3V3),
+ .vdd1v8 (VDD1V8),
+ .vss (VSS),
+ .xi (XI),
+ .xclk (XCLK),
+ .SDI (SDI),
+ .SDO (SDO),
+ .CSB (CSB),
+ .SCK (SCK),
+ .ser_rx (1'b0),
+ .ser_tx (tbuart_rx),
+ .irq (1'b0),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .flash_io2(flash_io2),
+ .flash_io3(flash_io3),
+ .adc_high (adc_h),
+ .adc_low (adc_l),
+ .adc0_in (adc_0),
+ .adc1_in (adc_1),
+ .RSTB (RSTB),
+ .comp_inp (comp_p),
+ .comp_inn (comp_n)
+ );
+
+ spiflash #(
+ .FILENAME("la_test1.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(flash_io2),
+ .io3(flash_io3)
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(tbuart_rx)
+ );
+
+endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test2/Makefile b/verilog/dv/harness/mprj_counter/la_test2/Makefile
new file mode 100644
index 0000000..c8b727b
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+.SUFFIXES:
+
+PATTERN = la_test2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2.c b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c
new file mode 100644
index 0000000..e9f5ece
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c
@@ -0,0 +1,47 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+/*
+ MPRJ LA Test:
+ - Sets counter clk through LA[64]
+ - Sets counter rst through LA[65]
+ - Observes count value for five clk cycle through LA[31:0]
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+ // All GPIO pins are configured to be output
+ // Used to flad the start/end of a test
+ reg_gpio_data = 0;
+ reg_gpio_ena = 0x0000;
+
+ // Configure All LA probes as inputs to the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0xFFFFFFFF; // [63:32]
+ reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Flag start of the test
+ reg_gpio_data = 0xAB60;
+
+ // Configure LA[64] LA[65] as outputs from the cpu
+ reg_la2_ena = 0xFFFFFFFC;
+
+ // Set clk & reset to one
+ reg_la2_data = 0x00000003;
+
+ // Toggle clk & de-assert reset
+ for (i=0; i<11; i=i+1) {
+ clk = !clk;
+ reg_la2_data = 0x00000000 | clk;
+ }
+
+ if (reg_la0_data == 0x05) {
+ reg_gpio_data = 0xAB61;
+ }
+
+}
+
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
new file mode 100644
index 0000000..a3e6223
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
@@ -0,0 +1,125 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+
+module la_test2_tb;
+ reg XCLK;
+ reg XI;
+
+ reg real adc_h, adc_l;
+ reg real adc_0, adc_1;
+ reg real comp_n, comp_p;
+ reg SDI, CSB, SCK, RSTB;
+ wire SDO;
+
+ wire [15:0] gpio;
+ wire [31:0] mprj_io;
+ wire [7:0] mprj_io_0;
+
+ assign mprj_io_0 = mprj_io[7:0];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 XCLK <= (XCLK === 1'b0);
+ always #220 XI <= (XI === 1'b0);
+
+ initial begin
+ XI = 0;
+ XCLK = 0;
+ end
+
+ initial begin
+ $dumpfile("la_test2.vcd");
+ $dumpvars(0, la_test2_tb);
+
+ // Repeat cycles of 1000 XCLK edges as needed to complete testbench
+ repeat (30) begin
+ repeat (1000) @(posedge XCLK);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(gpio == 16'h AB60);
+ $display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
+ wait(gpio == 16'h AB61);
+ $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
+ $finish;
+ end
+
+ initial begin
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ CSB <= 1'b0; // Apply CSB to start transmission
+ end
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ assign VSS = 1'b0;
+ assign VDD1V8 = 1'b1;
+ assign VDD3V3 = 1'b1;
+
+ harness_chip uut (
+ .vdd (VDD3V3),
+ .vdd1v8 (VDD1V8),
+ .vss (VSS),
+ .xi (XI),
+ .xclk (XCLK),
+ .SDI (SDI),
+ .SDO (SDO),
+ .CSB (CSB),
+ .SCK (SCK),
+ .ser_rx (1'b0),
+ .ser_tx (),
+ .irq (1'b0),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .flash_io2(flash_io2),
+ .flash_io3(flash_io3),
+ .adc_high (adc_h),
+ .adc_low (adc_l),
+ .adc0_in (adc_0),
+ .adc1_in (adc_1),
+ .RSTB (RSTB),
+ .comp_inp (comp_p),
+ .comp_inn (comp_n)
+ );
+
+ spiflash #(
+ .FILENAME("la_test2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(flash_io2),
+ .io3(flash_io3)
+ );
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/sections.lds b/verilog/dv/harness/sections.lds
similarity index 93%
rename from verilog/dv/harness/mgmt_soc/sections.lds
rename to verilog/dv/harness/sections.lds
index 4392c6d..8482887 100644
--- a/verilog/dv/harness/mgmt_soc/sections.lds
+++ b/verilog/dv/harness/sections.lds
@@ -1,6 +1,6 @@
MEMORY {
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
- RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x400 /* 256 words ( 1024 ? ) */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 8192 words ( 32 KB) */
}
SECTIONS {
diff --git a/verilog/dv/harness/mgmt_soc/spiflash.v b/verilog/dv/harness/spiflash.v
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/spiflash.v
rename to verilog/dv/harness/spiflash.v
diff --git a/verilog/dv/harness/mgmt_soc/start.s b/verilog/dv/harness/start.s
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/start.s
rename to verilog/dv/harness/start.s
diff --git a/verilog/dv/harness/stub.c b/verilog/dv/harness/stub.c
new file mode 100644
index 0000000..4d9c970
--- /dev/null
+++ b/verilog/dv/harness/stub.c
@@ -0,0 +1,12 @@
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
\ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/tbuart.v b/verilog/dv/harness/tbuart.v
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/tbuart.v
rename to verilog/dv/harness/tbuart.v
diff --git a/verilog/dv/harness/mgmt_soc/verify.log b/verilog/dv/harness/verify.log
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/verify.log
rename to verilog/dv/harness/verify.log
diff --git a/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v b/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v
deleted file mode 100644
index 164d526..0000000
--- a/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v
+++ /dev/null
@@ -1,232 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
-`include "arbiter.v"
-`include "dummy_slave.v"
-
-`ifndef AW
-`define AW 32
-`endif
-`ifndef DW
-`define DW 32
-`endif
-`ifndef NM
-`define NM 2
-`endif
-
-module arbiter_wb_tb;
-
- localparam SEL = `DW / 8;
-
- reg wb_clk_i;
- reg wb_rst_i;
-
- // Masters Interface
- reg [`NM-1:0] wbm_stb_i;
- reg [`NM-1:0] wbm_cyc_i;
- reg [`NM-1:0] wbm_we_i;
- reg [`NM*SEL-1:0] wbm_sel_i;
- reg [`NM*`DW-1:0] wbm_dat_i;
- reg [`NM*`AW-1:0] wbm_adr_i;
-
- wire [`NM-1:0] wbm_ack_o;
- wire [`NM-1:0] wbm_err_o;
- wire [`NM*`DW-1:0] wbm_dat_o;
-
- // Slave Interface
- reg wbs_ack_i;
- reg wbs_err_i;
- wire [`DW-1:0] wbs_dat_i;
- wire wbs_stb_i;
- wire wbs_cyc_i;
- wire wbs_we_i;
- wire [SEL-1:0] wbs_sel_i;
- wire [`AW-1:0] wbs_adr_i;
- wire [`DW-1:0] wbs_dat_o;
-
- wb_arbiter #(
- .AW(`AW),
- .DW(`DW),
- .NM(`NM)
- ) uut (
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // Masters Interface
- .wbm_stb_i(wbm_stb_i),
- .wbm_cyc_i(wbm_cyc_i),
- .wbm_we_i(wbm_we_i),
- .wbm_sel_i(wbm_sel_i),
- .wbm_dat_i(wbm_dat_i),
- .wbm_adr_i(wbm_adr_i),
-
- .wbm_ack_o(wbm_ack_o),
- .wbm_err_o(wbm_err_o),
- .wbm_dat_o(wbm_dat_o),
-
- // Slave Interface
- .wbs_ack_i(wbs_ack_o),
- .wbs_err_i(wbs_err_o),
- .wbs_dat_i(wbs_dat_o),
- .wbs_stb_o(wbs_stb_i),
- .wbs_cyc_o(wbs_cyc_i),
- .wbs_we_o(wbs_we_i),
- .wbs_sel_o(wbs_sel_i),
- .wbs_adr_o(wbs_adr_i),
- .wbs_dat_o(wbs_dat_i)
- );
-
- // Instantiate one dummy slave for testing
- dummy_slave dummy_slave (
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .wb_stb_i(wbs_stb_i),
- .wb_cyc_i(wbs_cyc_i),
- .wb_we_i(wbs_we_i),
- .wb_sel_i(wbs_sel_i),
- .wb_adr_i(wbs_adr_i),
- .wb_dat_i(wbs_dat_i),
- .wb_dat_o(wbs_dat_o),
- .wb_ack_o(wbs_ack_o)
- );
-
- always #1 wb_clk_i = ~wb_clk_i;
-
- initial begin
- wb_clk_i = 0;
- wb_rst_i = 0;
- wbm_stb_i = 0;
- wbm_cyc_i = 0;
- wbm_we_i = 0;
- wbm_sel_i = 0;
- wbm_dat_i = 0;
- wbm_adr_i = 0;
- wbs_ack_i = 0;
- wbs_err_i = 0;
- end
-
- initial begin
- $dumpfile("arbiter_wb_tb.vcd");
- $dumpvars(0, arbiter_wb_tb);
- repeat (50) begin
- repeat (1000) @(posedge wb_clk_i);
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Arbiter Failed");
- $display("%c[0m",27);
- $finish;
- end
-
-
- reg [`DW-1:0] data;
- reg [`AW-1:0] address;
-
- integer i;
-
- initial begin
- wb_rst_i = 1;
- #2;
- wb_rst_i = 0;
- #2;
-
- // Case 1: Initiate W/R requests from M0 -- MN
- for (i=0; i<`NM; i=i+1) begin
- data = $urandom_range(0, 255);
- address = $urandom_range(0, 255);
- write(address,data,i);
- #2;
- read(i);
- if (wbm_dat_i[i*`DW +: `DW] !== data) begin
- $display("Request Error from master %0b", i);
- $finish;
- end
- end
-
- #10;
-
- // Case 2: Initiate W/R requests from MN -- M0
- for (i=`NM-1; i>=0; i=i-1) begin
- data = $urandom_range(0, 255);
- address = $urandom_range(0, 255);
- write(address,data,i);
- #2;
- read(i);
- if (wbm_dat_i[i*`DW +: `DW] !== data) begin
- $display("Request Error from master %0b", i);
- $finish;
- end
- end
-
- // Case 3: Initiate concurrent W/R requests from all masters
- address = $urandom_range(0, 255);
- wbm_stb_i = {`NM{1'b1}};
- wbm_cyc_i = {`NM{1'b1}};
- wbm_we_i = {`NM{1'b1}};
- wbm_sel_i = {`NM{4'hF}};
- wbm_adr_i = {`NM{address}};
- for (i=`NM-1; i>=0; i=i-1) begin
- wbm_dat_i[i*`DW+: `DW] = $urandom_range(0, 2**32);
- end
-
- // Make sure that served request is master 0 (highest priority)
- wait(wbm_ack_o[0]);
- if (wbm_ack_o[`NM-1:1] !== 0) begin
- $display("Arbitration failed");
- $finish;
- end
-
- // Read
- wbm_we_i = {`NM{1'b0}};
- wait(wbm_ack_o[0]);
-
- // Make sure that the second master doesn't receive an ack
- if (wbm_ack_o[`NM-1:1] !== 0) begin
- $display("Arbitration failed");
- $finish;
- end
- #10;
- $finish;
- end
-
- task read;
- input mindex;
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i[mindex] = 1;
- wbm_cyc_i[mindex] = 1;
- wbm_we_i[mindex] = 0;
- $display("Read Cycle from master %0b started", mindex);
- end
- wait(wbm_ack_o[mindex]);
- wait(!wbm_ack_o[mindex]);
- wbm_stb_i[mindex] = 0;
- wbm_cyc_i[mindex] = 0;
- $display("Read Cycle from master %0b ended.", mindex);
- end
- endtask
-
- task write;
- input [`AW-1:0] adr;
- input [`DW-1:0] data;
- input integer mindex;
-
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i[mindex] = 1;
- wbm_cyc_i[mindex] = 1;
- wbm_we_i[mindex] = 1;
- wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[mindex*`AW+: `AW] = adr;
- wbm_dat_i[mindex*`DW+: `DW] = data;
- $display("Write Cycle from master %0b started", mindex);
- end
-
- wait(wbm_ack_o[mindex]);
- wait(!wbm_ack_o[mindex]);
- wbm_stb_i[mindex] = 0;
- wbm_cyc_i[mindex] = 0;
- $display("Write Cycle from master %0b ended.", mindex);
- end
- endtask
-
-endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/crossbar_wb/Makefile b/verilog/dv/wb/crossbar_wb/Makefile
deleted file mode 100644
index fcd10cc..0000000
--- a/verilog/dv/wb/crossbar_wb/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-.SUFFIXES:
-
-PATTERN = crossbar_wb
-
-all: ${PATTERN:=.vcd}
-
-%.vvp: %_tb.v
- iverilog -I .. -I ../../ -I ../../../ip -I ../../../rtl \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-clean:
- rm -f *.vvp *.vcd *.log
-
-.PHONY: clean all
diff --git a/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v b/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v
deleted file mode 100644
index a9a35b4..0000000
--- a/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v
+++ /dev/null
@@ -1,292 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
-`include "crossbar.v"
-`include "dummy_slave.v"
-
-`ifndef AW
- `define AW 32
-`endif
-`ifndef DW
- `define DW 32
-`endif
-`ifndef NM
- `define NM 2
-`endif
-
-`ifndef NS
- `define NS 4
-`endif
-
-`ifndef SLAVE_ADR
- `define SLAVE_ADR { \
- {8'hB0, {24{1'b0}}},\
- {8'hA0, {24{1'b0}}},\
- {8'h90, {24{1'b0}}},\
- {8'h80, {24{1'b0}}}\
- }\
-`endif
-
-`ifndef ADR_MASK
- `define ADR_MASK { \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}} \
- }\
-`endif
-
-module crossbar_wb_tb;
-
- localparam SEL = `DW / 8;
-
- reg wb_clk_i;
- reg wb_rst_i;
-
- // Masters interface
- reg [`NM-1:0] wbm_cyc_i;
- reg [`NM-1:0] wbm_stb_i;
- reg [`NM-1:0] wbm_we_i;
- reg [(`NM*(`DW/8))-1:0] wbm_sel_i;
- reg [(`NM*`AW)-1:0] wbm_adr_i;
- reg [(`NM*`DW)-1:0] wbm_dat_i;
- wire [`NM-1:0] wbm_ack_o;
- wire [`NM-1:0] wbm_err_o;
- wire [(`NM*`DW)-1:0] wbm_dat_o;
-
- // Slaves interfaces
- wire [`NS-1:0] wbs_ack_o;
- wire [(`NS*`DW)-1:0] wbs_dat_i;
- wire [`NS-1:0] wbs_cyc_o;
- wire [`NS-1:0] wbs_stb_o;
- wire [`NS-1:0] wbs_we_o;
- wire [(`NS*(`DW/8))-1:0] wbs_sel_o;
- wire [(`NS*`AW)-1:0] wbs_adr_o;
- wire [(`NS*`DW)-1:0] wbs_dat_o;
-
- wb_xbar #(
- .NM(`NM),
- .NS(`NS),
- .AW(`AW),
- .DW(`DW),
- .SLAVE_ADR(`SLAVE_ADR),
- .ADR_MASK(`ADR_MASK)
- )
- wb_xbar(
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- // Masters interface
- .wbm_cyc_i(wbm_cyc_i),
- .wbm_stb_i(wbm_stb_i),
- .wbm_we_i (wbm_we_i),
- .wbm_sel_i(wbm_sel_i),
- .wbm_adr_i(wbm_adr_i),
- .wbm_dat_i(wbm_dat_i),
- .wbm_ack_o(wbm_ack_o),
- .wbm_dat_o(wbm_dat_o),
- // Slaves interfaces
- .wbs_ack_i(wbs_ack_o),
- .wbs_dat_i(wbs_dat_o),
- .wbs_cyc_o(wbs_cyc_o),
- .wbs_stb_o(wbs_stb_o),
- .wbs_we_o(wbs_we_o),
- .wbs_sel_o(wbs_sel_o),
- .wbs_adr_o(wbs_adr_o),
- .wbs_dat_o(wbs_dat_i)
- );
-
- // Instantiate four dummy slaves for testing
- dummy_slave dummy_slaves [`NS-1:0](
- .wb_clk_i({`NS{wb_clk_i}}),
- .wb_rst_i({`NS{wb_rst_i}}),
- .wb_stb_i(wbs_stb_o),
- .wb_cyc_i(wbs_cyc_o),
- .wb_we_i(wbs_we_o),
- .wb_sel_i(wbs_sel_o),
- .wb_adr_i(wbs_adr_o),
- .wb_dat_i(wbs_dat_i),
- .wb_dat_o(wbs_dat_o),
- .wb_ack_o(wbs_ack_o)
- );
-
- initial begin
- wb_clk_i = 0;
- wb_rst_i = 0;
- wbm_cyc_i = 0;
- wbm_stb_i = 0;
- wbm_we_i = 0;
- wbm_sel_i = 0;
- wbm_adr_i = 0;
- wbm_dat_i = 0;
- end
-
- always #1 wb_clk_i = ~wb_clk_i;
-
- initial begin
- $dumpfile("crossbar_wb_tb.vcd");
- $dumpvars(0, crossbar_wb_tb);
- repeat (50) begin
- repeat (1000) @(posedge wb_clk_i);
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Crossbar Switch Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- integer i;
-
- reg [`AW*`NS-1:0] addresses = {
- {8'hB0, {24{1'b0}}},
- {8'hA0, {24{1'b0}}},
- {8'h90, {24{1'b0}}},
- {8'h80, {24{1'b0}}}
- };
-
- reg [`DW-1:0] m0_slave_data;
- reg [`DW-1:0] m1_slave_data;
- reg [`AW-1:0] slave_adr;
-
- initial begin
- wb_rst_i = 1;
- #2;
- wb_rst_i = 0;
- #2;
-
- // Case 1: Master0 addresses slave 0 and Master 2 Addresses slave 1
- slave_adr = addresses[`AW-1:0];
- m0_slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, m0_slave_data, 0);
-
- #2;
- read(slave_adr, 0);
- if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
- $display("Error reading from slave");
- $finish;
- end
-
- #10;
- slave_adr = addresses[`AW*2-1:`AW*1];
- m1_slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, m1_slave_data, 1);
- #2;
- read(slave_adr, 1);
- #10;
- if (wbm_dat_o[1*`DW+: `DW] !== m1_slave_data) begin
- $display("Error reading from slave");
- $finish;
- end
- #10;
- // Case 2: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously
- slave_adr = addresses[`AW-1:0];
- m0_slave_data = $urandom_range(0, 2**(`DW-2));
-
- wbm_stb_i[0] = 1;
- wbm_cyc_i[0] = 1;
- wbm_we_i [0] = 1;
- wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[0*`AW+: `AW] = slave_adr;
- wbm_dat_i[0*`DW+: `DW] = m0_slave_data;
-
- slave_adr = addresses[`AW*2-1:`AW*1];
- m1_slave_data = $urandom_range(0, 2**(`DW-2));
-
- wbm_stb_i[1] = 1;
- wbm_cyc_i[1] = 1;
- wbm_we_i[1] = 1;
- wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[1*`AW+: `AW] = slave_adr;
- wbm_dat_i[1*`DW+: `DW] = m1_slave_data;
-
- wait(wbm_ack_o[0] && wbm_ack_o[1]);
- wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
-
- // Read
- wbm_we_i = 2'b00;
- wait(wbm_ack_o[0] && wbm_ack_o[1]);
- wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
-
- if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
- $display("Error reading from slave");
- $finish;
- end
-
- // Case 3: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously
- slave_adr = addresses[`AW-1:0];
- m0_slave_data = $urandom_range(0, 2**(`DW-2));
-
- wbm_stb_i[0] = 1;
- wbm_cyc_i[0] = 1;
- wbm_we_i [0] = 1;
- wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[0*`AW+: `AW] = slave_adr;
- wbm_dat_i[0*`DW+: `DW] = m0_slave_data;
-
- slave_adr = addresses[`AW-1:0];
- m1_slave_data = $urandom_range(0, 2**(`DW-2));
-
- wbm_stb_i[1] = 1;
- wbm_cyc_i[1] = 1;
- wbm_we_i [1] = 1;
- wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[1*`AW+: `AW] = slave_adr;
- wbm_dat_i[1*`DW+: `DW] = m1_slave_data;
-
- wait(wbm_ack_o[0] && !wbm_ack_o[1]);
- wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
-
- // Read
- wbm_we_i = 2'b00;
- wait(wbm_ack_o[0]);
- wait(!wbm_ack_o[0]);
- if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
- $display("Error reading from slave");
- $finish;
- end
-
- $finish;
- end
-
- task read;
- input addr;
- input mindex;
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i[mindex] = 1;
- wbm_cyc_i[mindex] = 1;
- wbm_we_i[mindex] = 0;
- $display("Read cycle from master %0b started", mindex);
- end
- wait(wbm_ack_o[mindex]);
- wait(!wbm_ack_o[mindex]);
- wbm_stb_i[mindex] = 0;
- wbm_cyc_i[mindex] = 0;
- $display("Read cycle from master %0b ended.", mindex);
- end
- endtask
-
- task write;
- input [`AW-1:0] adr;
- input [`DW-1:0] data;
- input integer mindex;
-
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i[mindex] = 1;
- wbm_cyc_i[mindex] = 1;
- wbm_we_i[mindex] = 1;
- wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}};
- wbm_adr_i[mindex*`AW+: `AW] = adr;
- wbm_dat_i[mindex*`DW+: `DW] = data;
- $display("Write cycle from master %0b started", mindex);
- end
-
- wait(wbm_ack_o[mindex]);
- wait(!wbm_ack_o[mindex]);
- wbm_stb_i[mindex] = 0;
- wbm_cyc_i[mindex] = 0;
- $display("Write cycle from master %0b ended.", mindex);
- end
- endtask
-
-endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/distributor/Makefile b/verilog/dv/wb/distributor/Makefile
deleted file mode 100644
index f3a1273..0000000
--- a/verilog/dv/wb/distributor/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-.SUFFIXES:
-
-PATTERN = distributor
-
-all: ${PATTERN:=.vcd}
-
-%.vvp: %_tb.v
- iverilog -I .. -I ../../ -I ../../../ip -I ../../../rtl \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-clean:
- rm -f *.vvp *.vcd *.log
-
-.PHONY: clean all
diff --git a/verilog/dv/wb/distributor/distributor_tb.v b/verilog/dv/wb/distributor/distributor_tb.v
deleted file mode 100644
index ab8f929..0000000
--- a/verilog/dv/wb/distributor/distributor_tb.v
+++ /dev/null
@@ -1,226 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
-`include "distributor.v"
-`include "dummy_slave.v"
-
-`ifndef AW
- `define AW 32
-`endif
-`ifndef DW
- `define DW 32
-`endif
-
-`ifndef NS
- `define NS 4
-`endif
-
-`ifndef SLAVE_ADR
- `define SLAVE_ADR { \
- {8'hB0, {24{1'b0}}},\
- {8'hA0, {24{1'b0}}},\
- {8'h90, {24{1'b0}}},\
- {8'h80, {24{1'b0}}}\
- }\
-`endif
-
-`ifndef ADR_MASK
- `define ADR_MASK { \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}}, \
- {8'hFF, {24{1'b0}}} \
- }\
-`endif
-
-module distributor_tb;
-
- localparam SEL = `DW / 8;
-
- reg wb_clk_i;
- reg wb_rst_i;
-
- // Masters interface
- reg wbm_cyc_i;
- reg wbm_stb_i;
- reg wbm_we_i;
- reg [(`DW/8)-1:0] wbm_sel_i;
- reg [`AW-1:0] wbm_adr_i;
- reg [`DW-1:0] wbm_dat_i;
- wire wbm_ack_o;
- wire [`DW-1:0] wbm_dat_o;
-
- // Slaves interfaces
- wire [`NS-1:0] wbs_ack_o;
- wire [(`NS*`DW)-1:0] wbs_dat_i;
- wire [`NS-1:0] wbs_cyc_o;
- wire [`NS-1:0] wbs_stb_o;
- wire [`NS-1:0] wbs_we_o;
- wire [(`NS*(`DW/8))-1:0] wbs_sel_o;
- wire [(`NS*`AW)-1:0] wbs_adr_o;
- wire [(`NS*`DW)-1:0] wbs_dat_o;
-
- distributor #(
- .NS(`NS),
- .AW(`AW),
- .DW(`DW),
- .ADR_MASK(`ADR_MASK),
- .SLAVE_ADR(`SLAVE_ADR)
- )
- uut (
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- // Masters interface
- .wbm_cyc_i(wbm_cyc_i),
- .wbm_stb_i(wbm_stb_i),
- .wbm_we_i (wbm_we_i),
- .wbm_sel_i(wbm_sel_i),
- .wbm_adr_i(wbm_adr_i),
- .wbm_dat_i(wbm_dat_i),
- .wbm_ack_o(wbm_ack_o),
- .wbm_dat_o(wbm_dat_o),
-
- // Slaves interfaces
- .wbs_ack_i(wbs_ack_o),
- .wbs_dat_i(wbs_dat_o),
- .wbs_cyc_o(wbs_cyc_o),
- .wbs_stb_o(wbs_stb_o),
- .wbs_we_o(wbs_we_o),
- .wbs_sel_o(wbs_sel_o),
- .wbs_adr_o(wbs_adr_o),
- .wbs_dat_o(wbs_dat_i)
- );
-
- // Instantiate four dummy slaves for testing
- dummy_slave dummy_slaves [`NS-1:0](
- .wb_clk_i({`NS{wb_clk_i}}),
- .wb_rst_i({`NS{wb_rst_i}}),
- .wb_stb_i(wbs_stb_o),
- .wb_cyc_i(wbs_cyc_o),
- .wb_we_i(wbs_we_o),
- .wb_sel_i(wbs_sel_o),
- .wb_adr_i(wbs_adr_o),
- .wb_dat_i(wbs_dat_i),
- .wb_dat_o(wbs_dat_o),
- .wb_ack_o(wbs_ack_o)
- );
-
- initial begin
- wb_clk_i = 0;
- wb_rst_i = 0;
- wbm_cyc_i = 0;
- wbm_stb_i = 0;
- wbm_we_i = 0;
- wbm_sel_i = 0;
- wbm_adr_i = 0;
- wbm_dat_i = 0;
- end
-
- always #1 wb_clk_i = ~wb_clk_i;
-
- initial begin
- $dumpfile("distributor_tb.vcd");
- $dumpvars(0, distributor_tb);
- repeat (50) begin
- repeat (1000) @(posedge wb_clk_i);
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Distributor Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- integer i;
-
- reg [`DW-1:0] slave_data;
- reg [`AW-1:0] slave_adr;
-
- initial begin
- wb_rst_i = 1;
- #2;
- wb_rst_i = 0;
- #2;
-
- slave_adr = 32'h 8000_0000;
- slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, slave_data);
- #2;
- read(slave_adr);
- if (wbm_dat_i !== slave_data) begin
- $display("Failed R/W from slave");
- end
-
- #2;
- slave_adr = 32'h 9000_0000;
- slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, slave_data);
- #2;
- read(slave_adr);
- if (wbm_dat_i !== slave_data) begin
- $display("Failed R/W from slave");
- end
- #2;
-
- slave_adr = 32'h A000_0000;
- slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, slave_data);
- #2;
- read(slave_adr);
- if (wbm_dat_i !== slave_data) begin
- $display("Failed R/W from slave");
- end
-
- #2;
- slave_adr = 32'h B000_0000;
- slave_data = $urandom_range(0, 2**(`DW-2));
- write(slave_adr, slave_data);
- #2;
- read(slave_adr);
- if (wbm_dat_i !== slave_data) begin
- $display("Failed R/W from slave");
- end
-
-
- $finish;
- end
-
- task read;
- input [`AW-1:0] addr;
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i = 1;
- wbm_cyc_i = 1;
- wbm_we_i = 0;
- wbm_adr_i = addr;
- $display("Read Cycle Started");
- end
- wait(wbm_ack_o);
- wait(!wbm_ack_o);
- wbm_stb_i = 0;
- wbm_cyc_i = 0;
- $display("Read cycle Ended");
- end
- endtask
-
- task write;
- input [`AW-1:0] adr;
- input [`DW-1:0] data;
- begin
- @(posedge wb_clk_i) begin
- wbm_stb_i = 1;
- wbm_cyc_i = 1;
- wbm_we_i = 1;
- wbm_sel_i = {SEL{1'b1}};
- wbm_adr_i = adr;
- wbm_dat_i = data;
- $display("Write cycle started");
- end
- wait(wbm_ack_o);
- wait(!wbm_ack_o);
- wbm_stb_i = 0;
- wbm_cyc_i = 0;
- $display("Write cycle ended.");
- end
- endtask
-
-endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/distributor/distributor_tb.vcd b/verilog/dv/wb/distributor/distributor_tb.vcd
deleted file mode 100644
index 12f7ae8..0000000
--- a/verilog/dv/wb/distributor/distributor_tb.vcd
+++ /dev/null
@@ -1,963 +0,0 @@
-$date
- Fri Aug 21 14:18:15 2020
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module distributor_tb $end
-$var wire 4 ! wbs_we_o [3:0] $end
-$var wire 4 " wbs_stb_o [3:0] $end
-$var wire 16 # wbs_sel_o [15:0] $end
-$var wire 128 $ wbs_dat_o [127:0] $end
-$var wire 128 % wbs_dat_i [127:0] $end
-$var wire 4 & wbs_cyc_o [3:0] $end
-$var wire 128 ' wbs_adr_o [127:0] $end
-$var wire 4 ( wbs_ack_o [3:0] $end
-$var wire 32 ) wbm_dat_o [31:0] $end
-$var wire 1 * wbm_ack_o $end
-$var reg 32 + slave_adr [31:0] $end
-$var reg 32 , slave_data [31:0] $end
-$var reg 1 - wb_clk_i $end
-$var reg 1 . wb_rst_i $end
-$var reg 32 / wbm_adr_i [31:0] $end
-$var reg 1 0 wbm_cyc_i $end
-$var reg 32 1 wbm_dat_i [31:0] $end
-$var reg 4 2 wbm_sel_i [3:0] $end
-$var reg 1 3 wbm_stb_i $end
-$var reg 1 4 wbm_we_i $end
-$scope module dummy_slaves[0] $end
-$var wire 1 5 valid $end
-$var wire 32 6 wb_adr_i [31:0] $end
-$var wire 1 7 wb_clk_i $end
-$var wire 1 8 wb_cyc_i $end
-$var wire 32 9 wb_dat_i [31:0] $end
-$var wire 1 : wb_rst_i $end
-$var wire 4 ; wb_sel_i [3:0] $end
-$var wire 1 < wb_stb_i $end
-$var wire 1 = wb_we_i $end
-$var reg 32 > store [31:0] $end
-$var reg 1 ? wb_ack_o $end
-$var reg 32 @ wb_dat_o [31:0] $end
-$upscope $end
-$scope module dummy_slaves[1] $end
-$var wire 1 A valid $end
-$var wire 32 B wb_adr_i [31:0] $end
-$var wire 1 C wb_clk_i $end
-$var wire 1 D wb_cyc_i $end
-$var wire 32 E wb_dat_i [31:0] $end
-$var wire 1 F wb_rst_i $end
-$var wire 4 G wb_sel_i [3:0] $end
-$var wire 1 H wb_stb_i $end
-$var wire 1 I wb_we_i $end
-$var reg 32 J store [31:0] $end
-$var reg 1 K wb_ack_o $end
-$var reg 32 L wb_dat_o [31:0] $end
-$upscope $end
-$scope module dummy_slaves[2] $end
-$var wire 1 M valid $end
-$var wire 32 N wb_adr_i [31:0] $end
-$var wire 1 O wb_clk_i $end
-$var wire 1 P wb_cyc_i $end
-$var wire 32 Q wb_dat_i [31:0] $end
-$var wire 1 R wb_rst_i $end
-$var wire 4 S wb_sel_i [3:0] $end
-$var wire 1 T wb_stb_i $end
-$var wire 1 U wb_we_i $end
-$var reg 32 V store [31:0] $end
-$var reg 1 W wb_ack_o $end
-$var reg 32 X wb_dat_o [31:0] $end
-$upscope $end
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-$var wire 1 \ wb_cyc_i $end
-$var wire 32 ] wb_dat_i [31:0] $end
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-$var wire 4 _ wb_sel_i [3:0] $end
-$var wire 1 ` wb_stb_i $end
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-$var reg 32 b store [31:0] $end
-$var reg 1 c wb_ack_o $end
-$var reg 32 d wb_dat_o [31:0] $end
-$upscope $end
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-$var wire 1 . wb_rst_i $end
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-$var wire 32 f wbm_dat_i [31:0] $end
-$var wire 4 g wbm_sel_i [3:0] $end
-$var wire 1 3 wbm_stb_i $end
-$var wire 1 4 wbm_we_i $end
-$var wire 4 h wbs_ack_i [3:0] $end
-$var wire 4 i wbs_cyc_o [3:0] $end
-$var wire 128 j wbs_dat_i [127:0] $end
-$var wire 4 k wbs_stb_o [3:0] $end
-$var wire 4 l wbs_we_o [3:0] $end
-$var wire 16 m wbs_sel_o [15:0] $end
-$var wire 128 n wbs_dat_o [127:0] $end
-$var wire 128 o wbs_adr_o [127:0] $end
-$var wire 1 * wbm_ack_o $end
-$var wire 4 p slave_sel [3:0] $end
-$var reg 32 q wbm_dat_o [31:0] $end
-$var integer 32 r i [31:0] $end
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-$scope begin genblk1[1] $end
-$upscope $end
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-$scope begin genblk1[3] $end
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diff --git a/verilog/dv/wb/la_wb/la_wb_tb.vcd b/verilog/dv/wb/la_wb/la_wb_tb.vcd
deleted file mode 100644
index 9a9969d..0000000
--- a/verilog/dv/wb/la_wb/la_wb_tb.vcd
+++ /dev/null
@@ -1,635 +0,0 @@
-$date
- Fri Aug 21 14:19:50 2020
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module la_wb_tb $end
-$var wire 32 ! la_data_adr_0 [31:0] $end
-$var wire 32 " la_data_adr_1 [31:0] $end
-$var wire 32 # la_data_adr_2 [31:0] $end
-$var wire 32 $ la_data_adr_3 [31:0] $end
-$var wire 32 % la_ena_adr_0 [31:0] $end
-$var wire 32 & la_ena_adr_1 [31:0] $end
-$var wire 32 ' la_ena_adr_2 [31:0] $end
-$var wire 32 ( la_ena_adr_3 [31:0] $end
-$var wire 32 ) wb_dat_o [31:0] $end
-$var wire 1 * wb_ack_o $end
-$var reg 32 + la_data_0 [31:0] $end
-$var reg 32 , la_data_1 [31:0] $end
-$var reg 32 - la_data_2 [31:0] $end
-$var reg 32 . la_data_3 [31:0] $end
-$var reg 32 / la_ena_0 [31:0] $end
-$var reg 32 0 la_ena_1 [31:0] $end
-$var reg 32 1 la_ena_2 [31:0] $end
-$var reg 32 2 la_ena_3 [31:0] $end
-$var reg 32 3 wb_adr_i [31:0] $end
-$var reg 1 4 wb_clk_i $end
-$var reg 1 5 wb_cyc_i $end
-$var reg 32 6 wb_dat_i [31:0] $end
-$var reg 1 7 wb_rst_i $end
-$var reg 4 8 wb_sel_i [3:0] $end
-$var reg 1 9 wb_stb_i $end
-$var reg 1 : wb_we_i $end
-$scope module uut $end
-$var wire 4 ; iomem_we [3:0] $end
-$var wire 1 < resetn $end
-$var wire 1 = valid $end
-$var wire 1 * wb_ack_o $end
-$var wire 32 > wb_adr_i [31:0] $end
-$var wire 1 4 wb_clk_i $end
-$var wire 1 5 wb_cyc_i $end
-$var wire 32 ? wb_dat_i [31:0] $end
-$var wire 1 7 wb_rst_i $end
-$var wire 4 @ wb_sel_i [3:0] $end
-$var wire 1 9 wb_stb_i $end
-$var wire 1 : wb_we_i $end
-$var wire 32 A wb_dat_o [31:0] $end
-$var wire 1 B ready $end
-$var wire 128 C la_ena [127:0] $end
-$var wire 128 D la_data [127:0] $end
-$scope module la_ctrl $end
-$var wire 1 4 clk $end
-$var wire 32 E iomem_addr [31:0] $end
-$var wire 1 = iomem_valid $end
-$var wire 32 F iomem_wdata [31:0] $end
-$var wire 4 G iomem_wstrb [3:0] $end
-$var wire 1 < resetn $end
-$var wire 4 H la_ena_sel [3:0] $end
-$var wire 128 I la_ena [127:0] $end
-$var wire 4 J la_data_sel [3:0] $end
-$var wire 128 K la_data [127:0] $end
-$var reg 32 L iomem_rdata [31:0] $end
-$var reg 1 B iomem_ready $end
-$var reg 32 M la_data_0 [31:0] $end
-$var reg 32 N la_data_1 [31:0] $end
-$var reg 32 O la_data_2 [31:0] $end
-$var reg 32 P la_data_3 [31:0] $end
-$var reg 32 Q la_ena_0 [31:0] $end
-$var reg 32 R la_ena_1 [31:0] $end
-$var reg 32 S la_ena_2 [31:0] $end
-$var reg 32 T la_ena_3 [31:0] $end
-$upscope $end
-$upscope $end
-$scope task read $end
-$var reg 33 U addr [32:0] $end
-$upscope $end
-$scope task write $end
-$var reg 33 V addr [32:0] $end
-$var reg 33 W data [32:0] $end
-$upscope $end
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diff --git a/verilog/dv/wb/la_wb/ldo_wb_tb.vcd b/verilog/dv/wb/la_wb/ldo_wb_tb.vcd
deleted file mode 100644
index a0e252e..0000000
--- a/verilog/dv/wb/la_wb/ldo_wb_tb.vcd
+++ /dev/null
@@ -1,635 +0,0 @@
-$date
- Thu Aug 20 00:22:06 2020
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module ldo_wb_tb $end
-$var wire 32 ! ldo_data_adr_0 [31:0] $end
-$var wire 32 " ldo_data_adr_1 [31:0] $end
-$var wire 32 # ldo_data_adr_2 [31:0] $end
-$var wire 32 $ ldo_data_adr_3 [31:0] $end
-$var wire 32 % ldo_ena_adr_0 [31:0] $end
-$var wire 32 & ldo_ena_adr_1 [31:0] $end
-$var wire 32 ' ldo_ena_adr_2 [31:0] $end
-$var wire 32 ( ldo_ena_adr_3 [31:0] $end
-$var wire 32 ) wb_dat_o [31:0] $end
-$var wire 1 * wb_ack_o $end
-$var reg 32 + ldo_data_0 [31:0] $end
-$var reg 32 , ldo_data_1 [31:0] $end
-$var reg 32 - ldo_data_2 [31:0] $end
-$var reg 32 . ldo_data_3 [31:0] $end
-$var reg 32 / ldo_ena_0 [31:0] $end
-$var reg 32 0 ldo_ena_1 [31:0] $end
-$var reg 32 1 ldo_ena_2 [31:0] $end
-$var reg 32 2 ldo_ena_3 [31:0] $end
-$var reg 32 3 wb_adr_i [31:0] $end
-$var reg 1 4 wb_clk_i $end
-$var reg 1 5 wb_cyc_i $end
-$var reg 32 6 wb_dat_i [31:0] $end
-$var reg 1 7 wb_rst_i $end
-$var reg 4 8 wb_sel_i [3:0] $end
-$var reg 1 9 wb_stb_i $end
-$var reg 1 : wb_we_i $end
-$scope module uut $end
-$var wire 4 ; iomem_we [3:0] $end
-$var wire 1 < resetn $end
-$var wire 1 = valid $end
-$var wire 1 * wb_ack_o $end
-$var wire 32 > wb_adr_i [31:0] $end
-$var wire 1 4 wb_clk_i $end
-$var wire 1 5 wb_cyc_i $end
-$var wire 32 ? wb_dat_i [31:0] $end
-$var wire 1 7 wb_rst_i $end
-$var wire 4 @ wb_sel_i [3:0] $end
-$var wire 1 9 wb_stb_i $end
-$var wire 1 : wb_we_i $end
-$var wire 32 A wb_dat_o [31:0] $end
-$var wire 1 B ready $end
-$var wire 128 C ldo_ena [127:0] $end
-$var wire 128 D ldo_data [127:0] $end
-$scope module ldo_ctrl $end
-$var wire 1 4 clk $end
-$var wire 32 E iomem_addr [31:0] $end
-$var wire 1 = iomem_valid $end
-$var wire 32 F iomem_wdata [31:0] $end
-$var wire 4 G iomem_wstrb [3:0] $end
-$var wire 1 < resetn $end
-$var wire 4 H ldo_ena_sel [3:0] $end
-$var wire 128 I ldo_ena [127:0] $end
-$var wire 4 J ldo_data_sel [3:0] $end
-$var wire 128 K ldo_data [127:0] $end
-$var reg 32 L iomem_rdata [31:0] $end
-$var reg 1 B iomem_ready $end
-$var reg 32 M ldo_data_0 [31:0] $end
-$var reg 32 N ldo_data_1 [31:0] $end
-$var reg 32 O ldo_data_2 [31:0] $end
-$var reg 32 P ldo_data_3 [31:0] $end
-$var reg 32 Q ldo_ena_0 [31:0] $end
-$var reg 32 R ldo_ena_1 [31:0] $end
-$var reg 32 S ldo_ena_2 [31:0] $end
-$var reg 32 T ldo_ena_3 [31:0] $end
-$upscope $end
-$upscope $end
-$scope task read $end
-$var reg 33 U addr [32:0] $end
-$upscope $end
-$scope task write $end
-$var reg 33 V addr [32:0] $end
-$var reg 33 W data [32:0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
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-$end
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diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd
deleted file mode 100644
index 3abe514..0000000
--- a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd
+++ /dev/null
@@ -1,460 +0,0 @@
-$date
- Fri Aug 21 14:21:00 2020
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module spi_sysctrl_wb_tb $end
-$var wire 32 ! spi_cfg [31:0] $end
-$var wire 32 " spi_ena [31:0] $end
-$var wire 32 # spi_mask_rev [31:0] $end
-$var wire 32 $ spi_mfgr_id [31:0] $end
-$var wire 32 % spi_pll_bypass [31:0] $end
-$var wire 32 & spi_pll_cfg [31:0] $end
-$var wire 32 ' spi_prod_id [31:0] $end
-$var wire 8 ( spi_ro_config [7:0] $end
-$var wire 12 ) spi_ro_mfgr_id [11:0] $end
-$var wire 8 * spi_ro_prod_id [7:0] $end
-$var wire 32 + wb_dat_o [31:0] $end
-$var wire 1 , wb_ack_o $end
-$var wire 1 - spi_ro_xtal_ena $end
-$var wire 1 . spi_ro_reg_ena $end
-$var wire 26 / spi_ro_pll_trim [25:0] $end
-$var wire 3 0 spi_ro_pll_sel [2:0] $end
-$var wire 5 1 spi_ro_pll_div [4:0] $end
-$var wire 1 2 spi_ro_pll_dco_ena $end
-$var wire 1 3 spi_ro_pll_bypass $end
-$var wire 4 4 spi_ro_mask_rev [3:0] $end
-$var wire 1 5 por $end
-$var wire 1 6 irq_spi $end
-$var wire 1 7 ext_reset $end
-$var wire 1 8 SDO_enb $end
-$var wire 1 9 SDO $end
-$var reg 1 : CSB $end
-$var reg 1 ; RSTB $end
-$var reg 1 < SCK $end
-$var reg 1 = SDI $end
-$var reg 4 > mask_rev_in [3:0] $end
-$var reg 1 ? trap $end
-$var reg 32 @ wb_adr_i [31:0] $end
-$var reg 1 A wb_clk_i $end
-$var reg 1 B wb_cyc_i $end
-$var reg 32 C wb_dat_i [31:0] $end
-$var reg 1 D wb_rst_i $end
-$var reg 4 E wb_sel_i [3:0] $end
-$var reg 1 F wb_stb_i $end
-$var reg 1 G wb_we_i $end
-$scope module hkspi $end
-$var wire 1 : CSB $end
-$var wire 1 5 RST $end
-$var wire 1 ; RSTB $end
-$var wire 1 < SCK $end
-$var wire 1 = SDI $end
-$var wire 4 H mask_rev [3:0] $end
-$var wire 4 I mask_rev_in [3:0] $end
-$var wire 12 J mfgr_id [11:0] $end
-$var wire 8 K prod_id [7:0] $end
-$var wire 1 ? trap $end
-$var wire 1 L wrstb $end
-$var wire 1 8 sdo_enb $end
-$var wire 1 M rdstb $end
-$var wire 8 N odata [7:0] $end
-$var wire 8 O idata [7:0] $end
-$var wire 8 P iaddr [7:0] $end
-$var wire 1 9 SDO $end
-$var reg 1 6 irq $end
-$var reg 1 3 pll_bypass $end
-$var reg 1 2 pll_dco_ena $end
-$var reg 5 Q pll_div [4:0] $end
-$var reg 3 R pll_sel [2:0] $end
-$var reg 26 S pll_trim [25:0] $end
-$var reg 1 . reg_ena $end
-$var reg 1 7 reset $end
-$var reg 1 - xtal_ena $end
-$scope module U1 $end
-$var wire 1 : CSB $end
-$var wire 1 < SCK $end
-$var wire 1 = SDI $end
-$var wire 8 T idata [7:0] $end
-$var wire 8 U odata [7:0] $end
-$var wire 8 V oaddr [7:0] $end
-$var wire 1 9 SDO $end
-$var reg 8 W addr [7:0] $end
-$var reg 3 X count [2:0] $end
-$var reg 3 Y fixed [2:0] $end
-$var reg 8 Z ldata [7:0] $end
-$var reg 7 [ predata [6:0] $end
-$var reg 1 M rdstb $end
-$var reg 1 \ readmode $end
-$var reg 1 8 sdoenb $end
-$var reg 2 ] state [1:0] $end
-$var reg 1 ^ writemode $end
-$var reg 1 L wrstb $end
-$upscope $end
-$upscope $end
-$scope module uut $end
-$var wire 4 _ iomem_we [3:0] $end
-$var wire 1 3 pll_bypass $end
-$var wire 1 ` resetn $end
-$var wire 8 a spi_ro_config [7:0] $end
-$var wire 4 b spi_ro_mask_rev [3:0] $end
-$var wire 12 c spi_ro_mfgr_id [11:0] $end
-$var wire 1 2 spi_ro_pll_dco_ena $end
-$var wire 5 d spi_ro_pll_div [4:0] $end
-$var wire 3 e spi_ro_pll_sel [2:0] $end
-$var wire 26 f spi_ro_pll_trim [25:0] $end
-$var wire 8 g spi_ro_prod_id [7:0] $end
-$var wire 1 . spi_ro_reg_ena $end
-$var wire 1 - spi_ro_xtal_ena $end
-$var wire 1 h valid $end
-$var wire 1 , wb_ack_o $end
-$var wire 32 i wb_adr_i [31:0] $end
-$var wire 1 A wb_clk_i $end
-$var wire 1 B wb_cyc_i $end
-$var wire 32 j wb_dat_i [31:0] $end
-$var wire 1 D wb_rst_i $end
-$var wire 4 k wb_sel_i [3:0] $end
-$var wire 1 F wb_stb_i $end
-$var wire 1 G wb_we_i $end
-$var wire 32 l wb_dat_o [31:0] $end
-$var wire 1 m ready $end
-$scope module spi_sysctrl $end
-$var wire 1 A clk $end
-$var wire 32 n iomem_addr [31:0] $end
-$var wire 1 h iomem_valid $end
-$var wire 32 o iomem_wdata [31:0] $end
-$var wire 4 p iomem_wstrb [3:0] $end
-$var wire 1 3 pll_bypass $end
-$var wire 1 ` resetn $end
-$var wire 8 q spi_ro_config [7:0] $end
-$var wire 4 r spi_ro_mask_rev [3:0] $end
-$var wire 12 s spi_ro_mfgr_id [11:0] $end
-$var wire 1 2 spi_ro_pll_dco_ena $end
-$var wire 5 t spi_ro_pll_div [4:0] $end
-$var wire 3 u spi_ro_pll_sel [2:0] $end
-$var wire 26 v spi_ro_pll_trim [25:0] $end
-$var wire 8 w spi_ro_prod_id [7:0] $end
-$var wire 1 . spi_ro_reg_ena $end
-$var wire 1 - spi_ro_xtal_ena $end
-$var wire 1 x spi_prod_sel $end
-$var wire 1 y spi_mfgr_sel $end
-$var wire 1 z spi_maskrev_sel $end
-$var wire 1 { spi_ena_sel $end
-$var wire 1 | spi_cfg_sel $end
-$var wire 1 } pll_cfg_sel $end
-$var wire 1 ~ pll_bypass_sel $end
-$var reg 32 !" iomem_rdata [31:0] $end
-$var reg 1 m iomem_ready $end
-$upscope $end
-$upscope $end
-$scope task read $end
-$var reg 33 "" addr [32:0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-bx ""
-bx !"
-0~
-0}
-1|
-0{
-0z
-0y
-0x
-b101 w
-b11111111111110111111111111 v
-b0 u
-b100 t
-b10001010110 s
-bx r
-bz q
-b0 p
-b0 o
-b0 n
-xm
-bx l
-b0 k
-b0 j
-b0 i
-0h
-b101 g
-b11111111111110111111111111 f
-b0 e
-b100 d
-b10001010110 c
-bx b
-bz a
-0`
-b0 _
-0^
-b0 ]
-0\
-b0 [
-b0 Z
-b0 Y
-b0 X
-b0 W
-b0 V
-b0 U
-b0 T
-b11111111111110111111111111 S
-b0 R
-b100 Q
-b0 P
-b0 O
-b0 N
-0M
-0L
-b101 K
-b10001010110 J
-bx I
-bx H
-0G
-0F
-b0 E
-1D
-b0 C
-0B
-0A
-b0 @
-x?
-bx >
-0=
-0<
-0;
-1:
-09
-18
-07
-06
-15
-bx 4
-13
-12
-b100 1
-b0 0
-b11111111111110111111111111 /
-1.
-1-
-x,
-bx +
-b101 *
-b10001010110 )
-bz (
-b101110000000000000000000010000 '
-b101110000000000000000000001000 &
-b101110000000000000000000011000 %
-b101110000000000000000000001100 $
-b101110000000000000000000010100 #
-b101110000000000000000000000100 "
-b101110000000000000000000000000 !
-$end
-#1000
-0,
-0m
-1A
-#2000
-05
-1`
-0A
-1;
-0D
-#3000
-1A
-#4000
-0A
-b101110000000000000000000010100 ""
-b1111 4
-b1111 H
-b1111 b
-b1111 r
-b1111 >
-b1111 I
-#5000
-0|
-1z
-1h
-b101110000000000000000000010100 @
-b101110000000000000000000010100 i
-b101110000000000000000000010100 n
-1B
-1F
-1A
-#6000
-0A
-#7000
-b1111 +
-b1111 l
-b1111 !"
-1,
-1m
-1A
-#8000
-0A
-#9000
-0h
-b101110000000000000000000001100 ""
-0F
-0B
-0,
-0m
-1A
-#10000
-0A
-#11000
-1y
-0z
-1h
-b101110000000000000000000001100 @
-b101110000000000000000000001100 i
-b101110000000000000000000001100 n
-1B
-1F
-1A
-#12000
-0A
-#13000
-b10001010110 +
-b10001010110 l
-b10001010110 !"
-1,
-1m
-1A
-#14000
-0A
-#15000
-0h
-b101110000000000000000000010000 ""
-0F
-0B
-0,
-0m
-1A
-#16000
-0A
-#17000
-0y
-1x
-1h
-b101110000000000000000000010000 @
-b101110000000000000000000010000 i
-b101110000000000000000000010000 n
-1B
-1F
-1A
-#18000
-0A
-#19000
-b101 +
-b101 l
-b101 !"
-1,
-1m
-1A
-#20000
-0A
-#21000
-0h
-b101110000000000000000000011000 ""
-0F
-0B
-0,
-0m
-1A
-#22000
-0A
-#23000
-0x
-1~
-1h
-b101110000000000000000000011000 @
-b101110000000000000000000011000 i
-b101110000000000000000000011000 n
-1B
-1F
-1A
-#24000
-0A
-#25000
-b1 +
-b1 l
-b1 !"
-1,
-1m
-1A
-#26000
-0A
-#27000
-0h
-b101110000000000000000000001000 ""
-0F
-0B
-0,
-0m
-1A
-#28000
-0A
-#29000
-1}
-0~
-1h
-b101110000000000000000000001000 @
-b101110000000000000000000001000 i
-b101110000000000000000000001000 n
-1B
-1F
-1A
-#30000
-0A
-#31000
-b111111111111101111111111111 +
-b111111111111101111111111111 l
-b111111111111101111111111111 !"
-1,
-1m
-1A
-#32000
-0A
-#33000
-0h
-b101110000000000000000000000100 ""
-0F
-0B
-0,
-0m
-1A
-#34000
-0A
-#35000
-1{
-0}
-1h
-b101110000000000000000000000100 @
-b101110000000000000000000000100 i
-b101110000000000000000000000100 n
-1B
-1F
-1A
-#36000
-0A
-#37000
-b10000011 +
-b10000011 l
-b10000011 !"
-1,
-1m
-1A
-#38000
-0A
-#39000
-0h
-0F
-0B
-0,
-0m
-1A
diff --git a/verilog/dv/wb/Makefile b/verilog/dv/wb_utests/Makefile
similarity index 77%
copy from verilog/dv/wb/Makefile
copy to verilog/dv/wb_utests/Makefile
index 7b0e09b..930e5b5 100644
--- a/verilog/dv/wb/Makefile
+++ b/verilog/dv/wb_utests/Makefile
@@ -3,7 +3,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = gpio_wb intercon_wb spimemio_wb uart_wb crossbar_wb arbiter_wb
+PATTERNS = gpio_wb intercon_wb la_wb mem_wb mprj_ctrl spi_sysctrl_wb spimemio_wb uart_wb
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/wb/gpio_wb/Makefile b/verilog/dv/wb_utests/gpio_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/gpio_wb/Makefile
rename to verilog/dv/wb_utests/gpio_wb/Makefile
diff --git a/verilog/dv/wb/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/gpio_wb/gpio_wb_tb.v
rename to verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
diff --git a/verilog/dv/wb/intercon_wb/Makefile b/verilog/dv/wb_utests/intercon_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/intercon_wb/Makefile
rename to verilog/dv/wb_utests/intercon_wb/Makefile
diff --git a/verilog/dv/wb/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/intercon_wb/intercon_wb_tb.v
rename to verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
diff --git a/verilog/dv/wb/la_wb/Makefile b/verilog/dv/wb_utests/la_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/la_wb/Makefile
rename to verilog/dv/wb_utests/la_wb/Makefile
diff --git a/verilog/dv/wb/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/la_wb/la_wb_tb.v
rename to verilog/dv/wb_utests/la_wb/la_wb_tb.v
diff --git a/verilog/dv/wb/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/mem_wb/Makefile
rename to verilog/dv/wb_utests/mem_wb/Makefile
diff --git a/verilog/dv/wb/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
similarity index 96%
rename from verilog/dv/wb/mem_wb/mem_wb_tb.v
rename to verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index eb45e22..2c2afd7 100644
--- a/verilog/dv/wb/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -4,7 +4,7 @@
`define USE_OPENRAM
-`include "sram_1rw1r_32_256_8_sky130.v"
+`include "sram_1rw1r_32_8192_8_sky130.v"
`include "mem_wb.v"
module mem_wb_tb;
@@ -62,7 +62,7 @@
// Randomly Write to memory array
for ( i = 0; i < 1; i = i + 1) begin
- ref_data[i] = $urandom_range(0, 2**32);
+ ref_data[i] = $urandom_range(0, 2**30);
write(i, ref_data[i]);
#2;
end
diff --git a/verilog/dv/wb/arbiter_wb/Makefile b/verilog/dv/wb_utests/mprj_ctrl/Makefile
similarity index 62%
rename from verilog/dv/wb/arbiter_wb/Makefile
rename to verilog/dv/wb_utests/mprj_ctrl/Makefile
index e792a4d..841be9e 100644
--- a/verilog/dv/wb/arbiter_wb/Makefile
+++ b/verilog/dv/wb_utests/mprj_ctrl/Makefile
@@ -1,11 +1,11 @@
.SUFFIXES:
-PATTERN = arbiter_wb
+PATTERN = mprj_ctrl
all: ${PATTERN:=.vcd}
%.vvp: %_tb.v
- iverilog -I ../../../ip -I .. -I ../../ -I ../../../rtl \
+ iverilog -I ../../../rtl \
$< -o $@
%.vcd: %.vvp
@@ -14,4 +14,4 @@
clean:
rm -f *.vvp *.vcd *.log
-.PHONY: clean all
+.PHONY: clean all
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..a4c01d0
--- /dev/null
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,142 @@
+
+
+`timescale 1 ns / 1 ps
+
+`include "mprj_ctrl.v"
+
+module mprj_ctrl_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // Mega Project Control Registers
+ wire [31:0] mprj_ctrl = uut.BASE_ADR;
+ wire [31:0] pwr_ctrl = uut.BASE_ADR + uut.IO_PADS*4;
+
+ initial begin
+ $dumpfile("mprj_ctrl_tb.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] data;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ for (i=0; i<uut.IO_PADS; i=i+1) begin
+ data = $urandom_range(0, 2**(7));
+ write(mprj_ctrl+i*4, data);
+ #2;
+ read(mprj_ctrl+i*4);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from IO-CTRL Failed.");
+ $finish;
+ end
+ end
+
+ for (i=0; i<uut.PWR_CTRL; i=i+1) begin
+ data = $urandom_range(0, 2**(7));
+ write(pwr_ctrl+i*4, data);
+ #2;
+ read(pwr_ctrl+i*4);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from POWER-CTRL Failed.");
+ $finish;
+ end
+ end
+
+ $display("Success!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ mprj_ctrl_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/spi_sysctrl_wb/Makefile b/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/spi_sysctrl_wb/Makefile
rename to verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
rename to verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
diff --git a/verilog/dv/wb/spimemio_wb/Makefile b/verilog/dv/wb_utests/spimemio_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/spimemio_wb/Makefile
rename to verilog/dv/wb_utests/spimemio_wb/Makefile
diff --git a/verilog/dv/wb/spimemio_wb/flash.hex b/verilog/dv/wb_utests/spimemio_wb/flash.hex
similarity index 100%
rename from verilog/dv/wb/spimemio_wb/flash.hex
rename to verilog/dv/wb_utests/spimemio_wb/flash.hex
diff --git a/verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v
rename to verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
diff --git a/verilog/dv/wb/sysctrl_wb/Makefile b/verilog/dv/wb_utests/sysctrl_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/sysctrl_wb/Makefile
rename to verilog/dv/wb_utests/sysctrl_wb/Makefile
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v
rename to verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd
similarity index 100%
rename from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd
rename to verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd
diff --git a/verilog/dv/wb/uart_wb/Makefile b/verilog/dv/wb_utests/uart_wb/Makefile
similarity index 100%
rename from verilog/dv/wb/uart_wb/Makefile
rename to verilog/dv/wb_utests/uart_wb/Makefile
diff --git a/verilog/dv/wb/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
similarity index 100%
rename from verilog/dv/wb/uart_wb/uart_wb_tb.v
rename to verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
