final gds & drc results
diff --git a/Makefile.master b/Makefile.master
new file mode 100644
index 0000000..ce7eb6b
--- /dev/null
+++ b/Makefile.master
@@ -0,0 +1,341 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# cannot commit files larger than 100 MB to GitHub
+FILE_SIZE_LIMIT_MB = 100
+
+# Commands to be used to compress/uncompress files
+# they must operate **in place** (otherwise, modify the target to delete the
+# intermediate file/archive)
+COMPRESS ?= gzip -n --best
+UNCOMPRESS ?= gzip -d
+ARCHIVE_EXT ?= gz
+
+# The following variables are to build static pattern rules
+
+# Needed to rebuild archives that were previously split
+SPLIT_FILES := $(shell find . -type f -name "*.$(ARCHIVE_EXT).00.split")
+SPLIT_FILES_SOURCES := $(basename $(basename $(basename $(SPLIT_FILES))))
+
+# Needed to uncompress the existing archives
+ARCHIVES := $(shell find . -type f -name "*.$(ARCHIVE_EXT)")
+ARCHIVE_SOURCES := $(basename $(ARCHIVES))
+
+# Needed to compress and split files/archives that are too large
+LARGE_FILES := $(shell find ./gds -type f -name "*.gds")
+LARGE_FILES += $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*" -not -path "./gds/*" -not -path "./openlane/*")
+LARGE_FILES_GZ := $(addsuffix .$(ARCHIVE_EXT), $(LARGE_FILES))
+LARGE_FILES_GZ_SPLIT := $(addsuffix .$(ARCHIVE_EXT).00.split, $(LARGE_FILES))
+# consider splitting existing archives
+LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES))
+
+# PDK setup configs
+THREADS ?= $(shell nproc)
+STD_CELL_LIBRARY ?= sky130_fd_sc_hd
+SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
+IO_LIBRARY ?= sky130_fd_io
+SKYWATER_COMMIT ?= f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+OPEN_PDKS_COMMIT ?= 95c92cc563e00b3ee3ed9863b352304943e8ff8f
+
+.DEFAULT_GOAL := ship
+# We need portable GDS_FILE pointers...
+.PHONY: ship
+ship: check-env uncompress
+ @echo "###############################################"
+ @echo "Generating Caravel GDS (sources are in the 'gds' directory)"
+ @sleep 1
+ @echo "\
+ random seed `scripts/set_user_id.py -report`; \
+ gds readonly true; \
+ gds rescale false; \
+ gds read ../gds/user_project_wrapper.gds; \
+ load caravel -dereference;\
+ select top cell;\
+ gds write caravel.gds; \
+ exit;" > ./mag/mag2gds_caravel.tcl
+ @cd mag && PDKPATH=${PDK_ROOT}/sky130A magic -noc -dnull mag2gds_caravel.tcl < /dev/null
+ @rm ./mag/mag2gds_caravel.tcl
+ @mv -f ./gds/caravel.gds ./gds/caravel.old.gds
+ mv ./mag/caravel.gds ./gds
+
+.PHONY: clean
+clean:
+ cd ./verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) clean
+ cd ./verilog/dv/caravel/user_proj_example/ && \
+ $(MAKE) -j$(THREADS) clean
+ cd ./verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) clean
+
+
+.PHONY: verify
+verify:
+ cd ./verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) all
+ cd ./verilog/dv/caravel/user_proj_example/ && \
+ $(MAKE) -j$(THREADS) all
+ cd ./verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) all
+
+
+
+#####
+$(LARGE_FILES_GZ): %.$(ARCHIVE_EXT): %
+ @if ! [ $(suffix $<) = ".$(ARCHIVE_EXT)" ]; then\
+ $(COMPRESS) $< > /dev/null &&\
+ echo "$< -> $@";\
+ fi
+
+$(LARGE_FILES_GZ_SPLIT): %.$(ARCHIVE_EXT).00.split: %.$(ARCHIVE_EXT)
+ @if [ -n "$$(find "$<" -prune -size +$(FILE_SIZE_LIMIT_MB)M)" ]; then\
+ split $< -b $(FILE_SIZE_LIMIT_MB)M $<. -d --additional-suffix=.split &&\
+ rm $< &&\
+ echo -n "$< -> $$(ls $<.*.split)" | tr '\n' ' ' && echo "";\
+ fi
+
+# This target compresses all files larger than $(FILE_SIZE_LIMIT_MB) MB
+.PHONY: compress
+compress: $(LARGE_FILES_GZ) $(LARGE_FILES_GZ_SPLIT)
+ @echo "Files larger than $(FILE_SIZE_LIMIT_MB) MBytes are compressed!"
+
+
+
+#####
+$(ARCHIVE_SOURCES): %: %.$(ARCHIVE_EXT)
+ @$(UNCOMPRESS) $<
+ @echo "$< -> $@"
+
+.SECONDEXPANSION:
+$(SPLIT_FILES_SOURCES): %: $$(sort $$(wildcard %.$(ARCHIVE_EXT).*.split))
+ @cat $? > $@.$(ARCHIVE_EXT)
+ @rm $?
+ @echo "$? -> $@.$(ARCHIVE_EXT)"
+ @$(UNCOMPRESS) $@.$(ARCHIVE_EXT)
+ @echo "$@.$(ARCHIVE_EXT) -> $@"
+
+
+.PHONY: uncompress
+uncompress: $(SPLIT_FILES_SOURCES) $(ARCHIVE_SOURCES)
+ @echo "All files are uncompressed!"
+
+
+# verify that the wrapper was respected
+xor-wrapper:
+ # first erase the user's user_project_wrapper.gds
+ sh utils/erase_box.sh gds/user_project_wrapper.gds 0 0 2920 3520
+ # do the same for the empty wrapper
+ sh utils/erase_box.sh gds/user_project_wrapper_empty.gds 0 0 2920 3520
+ mkdir -p signoff/user_project_wrapper_xor
+ # XOR the two resulting layouts
+ sh utils/xor.sh \
+ gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper user_project_wrapper.xor.xml
+ sh utils/xor.sh \
+ gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper gds/user_project_wrapper.xor.gds > signoff/user_project_wrapper_xor/xor.log
+ rm gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds
+ mv gds/user_project_wrapper.xor.gds gds/user_project_wrapper.xor.xml signoff/user_project_wrapper_xor
+ python utils/parse_klayout_xor_log.py \
+ -l signoff/user_project_wrapper_xor/xor.log \
+ -o signoff/user_project_wrapper_xor/total.txt
+ # screenshot the result for convenience
+ sh utils/scrotLayout.sh \
+ $(PDK_ROOT)/sky130A/libs.tech/klayout/sky130A.lyt \
+ signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds
+ @cat signoff/user_project_wrapper_xor/total.txt
+
+# LVS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./mag/tmp
+ echo "addpath hexdigits;\
+ addpath \$$PDKPATH/libs.ref/sky130_ml_xx_hd/mag;\
+ load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract unique;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && \
+ export MAGTYPE=maglef; \
+ magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./mag/*.ext
+ mv -f ./mag/extract_$*.{tcl,log} ./mag/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh ./spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 ./scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
+ mv -f ./verilog/gl/*{.out,.json,.log} ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+# connect-by-label is enabled here!
+LVS_MAGLEF_BLOCKS = $(foreach block, $(BLOCKS), lvs-maglef-$(block))
+$(LVS_MAGLEF_BLOCKS): lvs-maglef-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./maglef/tmp
+ echo "load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && export MAGTYPE=maglef; magic -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./maglef/*.ext
+ mv -f ./mag/extract_$*.{tcl,log} ./maglef/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh ./spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 ./scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.maglef.lvs.summary.log
+ mv -f ./verilog/gl/*{.out,.json,.log} ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+# DRC
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+DRC_BLOCKS = $(foreach block, $(BLOCKS), drc-$(block))
+$(DRC_BLOCKS): drc-% : ./gds/%.gds
+ echo "Running DRC on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_DRC=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc -noc -dnull drc_on_gds.tcl < /dev/null
+ @echo "DRC result: ./gds/tmp/$*.drc"
+
+# Antenna
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+ANTENNA_BLOCKS = $(foreach block, $(BLOCKS), antenna-$(block))
+$(ANTENNA_BLOCKS): antenna-% : ./gds/%.gds
+ echo "Running Antenna Checks on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_ANTENNA=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc -noc -dnull antenna_on_gds.tcl < /dev/null 2>&1 | tee ./tmp/$*.antenna
+ mv -f ./gds/*.ext ./gds/tmp/
+ @echo "Antenna result: ./gds/tmp/$*.antenna"
+
+.PHONY: help
+help:
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+###########################################################################
+.PHONY: pdk
+pdk: skywater-pdk skywater-library skywater-timing open_pdks build-pdk
+
+$(PDK_ROOT)/skywater-pdk:
+ git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk
+
+.PHONY: skywater-pdk
+skywater-pdk: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git checkout master && git pull && \
+ git checkout -qf $(SKYWATER_COMMIT)
+
+.PHONY: skywater-library
+skywater-library: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git submodule update --init libraries/$(STD_CELL_LIBRARY)/latest && \
+ git submodule update --init libraries/$(IO_LIBRARY)/latest && \
+ git submodule update --init libraries/$(SPECIAL_VOLTAGE_LIBRARY)/latest
+
+skywater-timing: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ $(MAKE) timing
+### OPEN_PDKS
+$(PDK_ROOT)/open_pdks:
+ git clone git://opencircuitdesign.com/open_pdks $(PDK_ROOT)/open_pdks
+
+.PHONY: open_pdks
+open_pdks: check-env $(PDK_ROOT)/open_pdks
+ cd $(PDK_ROOT)/open_pdks && \
+ git checkout master && git pull && \
+ git checkout -qf $(OPEN_PDKS_COMMIT)
+
+.PHONY: build-pdk
+build-pdk: check-env $(PDK_ROOT)/open_pdks $(PDK_ROOT)/skywater-pdk
+ [ -d $(PDK_ROOT)/sky130A ] && \
+ (echo "Warning: A sky130A build already exists under $(PDK_ROOT). It will be deleted first!" && \
+ sleep 5 && \
+ rm -rf $(PDK_ROOT)/sky130A) || \
+ true
+ cd $(PDK_ROOT)/open_pdks && \
+ ./configure --enable-alpha-lib --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries --with-sky130-local-path=$(PDK_ROOT) && \
+ cd sky130 && \
+ sed -i 's/REPO_PATH = ~\/gits/REPO_PATH = \$$\(PDK_ROOT\)\/open_pdks\/libs/g' Makefile && \
+ $(MAKE) veryclean && \
+ $(MAKE) && \
+ $(MAKE) install-local && \
+ $(MAKE) clean
+
+.RECIPE: manifest
+manifest: mag/ maglef/ verilog/rtl/ scripts/ Makefile
+ touch manifest && \
+ find verilog/rtl/* -type f ! -name "caravel_netlists.v" ! -name "user_*.v" ! -name "README" ! -name "defines.v" -exec shasum {} \; > manifest && \
+ find maglef/*.mag -type f ! -name "user_project_wrapper.mag" -exec shasum {} \; >> manifest && \
+ shasum mag/caravel.mag mag/.magicrc >> manifest
+ shasum scripts/set_user_id.py scripts/generate_fill.py scripts/compositor.py >> manifest
+ shasum lef/user_project_wrapper_empty.lef >> manifest
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+# Make README.rst
+README.rst: README.src.rst docs/source/getting-started.rst docs/source/tool-versioning.rst openlane/README.src.rst docs/source/caravel-with-openlane.rst Makefile
+ pip -q install rst_include && \
+ rm -f README.rst && \
+ rst_include include README.src.rst - | \
+ sed \
+ -e's@\.\/\_static@\/docs\/source\/\_static@g' \
+ -e's@:doc:`tool-versioning`@`tool-versioning.rst <./docs/source/tool-versioning.rst>`__@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > README.rst && \
+ rst_include include openlane/README.src.rst - | \
+ sed \
+ -e's@https://github.com/efabless/caravel/blob/master/verilog@../verilog@g' \
+ -e's@:ref:`getting-started`@`README.rst <../README.rst>`__@g' \
+ -e's@https://github.com/efabless/caravel/blob/master/openlane/@./@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > openlane/README.rst
diff --git a/doc b/doc
new file mode 120000
index 0000000..5c457d7
--- /dev/null
+++ b/doc
@@ -0,0 +1 @@
+docs
\ No newline at end of file
diff --git a/docs/README.md b/docs/README.md
new file mode 100644
index 0000000..1fa58df
--- /dev/null
+++ b/docs/README.md
@@ -0,0 +1,18 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
diff --git a/docs/caravel_datasheet.pdf b/docs/caravel_datasheet.pdf
new file mode 100644
index 0000000..2da582f
--- /dev/null
+++ b/docs/caravel_datasheet.pdf
Binary files differ
diff --git a/docs/caravel_datasheet.ps b/docs/caravel_datasheet.ps
new file mode 100644
index 0000000..e6e09dd
--- /dev/null
+++ b/docs/caravel_datasheet.ps
@@ -0,0 +1,12616 @@
+%!PS-Adobe-3.0
+%%Title: caravel_datasheet.ps
+%%Creator: XCircuit v0.0 rev-769945435
+%%CreationDate: Tue Oct 27 20:52:47 2020
+%%Pages: 30
+%%BoundingBox: 0 0 612 792
+%%DocumentNeededResources: font Times-Roman Times-BoldItalic Helvetica
+%%+ font Helvetica-Bold Helvetica-Oblique HelveticaISO Helvetica-ObliqueISO
+%%+ font Courier Courier-Bold
+%%EndComments
+%%BeginProlog
+%
+% PostScript prolog for output from xcircuit
+% Version: 3.9
+%
+% Electrical circuit (and otherwise general) drawing program
+%
+% Written by Tim Edwards 8/5/93--4/12/16 (tim@opencircuitdesign.com)
+% The Johns Hopkins University (1993-2004)
+% MultiGiG, Inc. (2004-2012)
+% Open Circuit Design (2012-2016)
+%
+%%BeginResource: procset XCIRCproc 3.9 1
+%
+% supporting definitions --- these are the primary xcircuit types.
+
+/XCIRCsave save def
+/topmat matrix currentmatrix def
+
+/fontslant { /slant exch def [1 0 slant 1 0 0]
+ exch findfont exch makefont dup length dict /ndict exch def
+ { 1 index /FID ne { ndict 3 1 roll put } { pop pop } ifelse } forall
+ ndict definefont pop} def
+/ul { count 0 gt { dup type /stringtype eq showflag 1 eq and { gsave
+ currentpoint topmat setmatrix 0 0 moveto 2 index stringwidth pop (_)
+ false charpath flattenpath pathbbox grestore exch pop 1 index
+ sub setlinewidth exch pop currentpoint 3 -1 roll add moveto 0
+ rlineto stroke moveto } if } if } def
+/ol { count 0 gt { dup type /stringtype eq showflag 1 eq and { gsave gsave
+ currentpoint topmat setmatrix 2 index stringwidth pop 3 index
+ true charpath flattenpath pathbbox grestore exch pop
+ exch pop topmat setmatrix (_) true charpath pathbbox grestore
+ exch pop 1 index sub setlinewidth exch pop currentpoint
+ exch 4 1 roll exch sub add moveto pop 0 rlineto stroke
+ moveto } if } if } def
+/stW { gsave currentpoint newpath moveto true charpath flattenpath
+ pathbbox pop exch pop sub grestore } def
+/Ts {mark Tabs aload pop counttomark 1 add array astore /Tabs exch def Tabs
+ 0 currentpoint pop put} def
+/Tbn {mark Tabs aload pop counttomark dup 2 add 1 roll cleartomark 1 sub} def
+/Tb { 0 1 Tbn {Tabs exch get dup currentpoint pop lt
+ {currentpoint exch pop moveto exit} {pop} ifelse } for } def
+/Tf { Tbn -1 0 {Tabs exch get dup currentpoint pop gt
+ {currentpoint exch pop moveto exit} {pop} ifelse } for } def
+/qS { (aa) stW (a a) stW sub 4 div 0 Kn } def
+/hS { qS qS } def
+/pspc 0 def
+/cf0 { scalefont setfont } bind def
+/Kn { dup kY add /kY exch def rmoveto } bind def
+/ss { /fscale fscale 0.67 mul def currentfont 0.67 cf0 0 fscale0 fscale mul
+ 0.33 mul neg Kn} def
+/Ss { /fscale fscale 0.67 mul def currentfont 0.67 cf0 0 fscale0 fscale mul
+ 0.67 mul Kn } def
+/ns { 0 kY neg Kn /kY 0 def /fscale 1.0 def xfont0 1.0 cf0 } def
+/MR { /twidth exch def } def
+/CRx { } def
+/CR { ns 0 /Bline Bline fscale0 neg add def Bline moveto CRx } def
+/cf { dup type /realtype ne {1.0} if exch findfont exch kY 0 eq
+ { 40 mul dup /fscale0 exch def cf0 /xfont0 currentfont def}
+ {fscale0 mul fscale mul cf0} ifelse } def
+/ctmk { counttomark dup 2 add -1 roll pop } bind def
+/label { gsave translate 0 0 moveto dup scale neg
+ /rotval exch def /twidth 100000 def /just exch def just 128 and
+ 0 gt {/mshow {pop} def} {/mshow {show} def} ifelse just 16 and 0
+ gt {gsave rotval rotate 0 1 dtransform gsave pagemat setmatrix
+ idtransform exch grestore 1 0 dtransform gsave pagemat setmatrix
+ idtransform exch grestore dup abs 1e-9 lt {pop mul 0 gt} {3 1 roll
+ pop pop 0 lt} ifelse grestore {-1 /rotval rotval neg def /just just
+ dup 3 and 1 ne {3 xor} if def} {1} ifelse exch -1e-9 lt {-1 /rotval
+ rotval neg def /just just dup 12 and 4 ne {12 xor} if def} {1}
+ ifelse scale } if /showflag 0 def /fspc pspc def /Bline 0 def
+ /numlines 0 def /padding 0 array def /Tabs 0 array def
+ /fscale 1.0 def /kY 0 def gsave /CRx { linewid padding
+ aload pop numlines 1 add dup /numlines exch def array astore
+ /padding exch def /linewid 0 def } def dup 1 add copy dup 1 0
+ dtransform exch atan rotate {exch dup type /stringtype eq {gsave dup
+ gsave newpath 0 0 moveto true charpath flattenpath pathbbox pop exch
+ pop exch pop grestore currentpoint pop add dup /linewid exch def twidth
+ ge {grestore CR exch 1 add dup 2 add {CR} exch 1 roll exch} {grestore}
+ ifelse true charpath flattenpath} {dup type /arraytype eq {exec} {12
+ string cvs true charpath flattenpath} ifelse} ifelse} repeat
+ CRx /CRx {padding aload pop just 1280 and 0 gt {blockwid exch sub just
+ 1024 and 0 gt {0.5 mul} if} {pop 0} ifelse 0 rmoveto numlines 1 sub
+ dup /numlines exch def array astore /padding exch def} def exch pop
+ pathbbox grestore 4 copy pop exch pop exch sub /blockwid exch def
+ 3 -1 roll pop 3 1 roll just 1 and 0 gt {just 2 and
+ 0 gt {exch pop neg fspc sub} {exch sub 0.5 mul neg} ifelse} {pop neg
+ fspc add} ifelse exch Bline exch just 4 and 0 gt {just 8 and 0 gt
+ {exch pop neg fspc sub} {add 0.5 mul neg} ifelse} {pop neg fspc add}
+ ifelse rotval rotate Kn currentpoint translate /showflag 1 def /Bline
+ 0 def /Tabs 0 array def /fscale 1.0 def /kY 0 def CRx {dup type
+ /stringtype eq {mshow} {dup type /arraytype eq {exec} {12 string cvs
+ mshow} ifelse} ifelse} repeat grestore endclip} def
+/pinlabel { 4 index 32 and 0 ne hlevel 0 eq or { /pspc 10 def label
+ /pspc 0 def } { pop pop pop pop pop {pop} repeat } ifelse } def
+/pinglobal { pinlabel } def
+/infolabel { pinlabel } def
+/graphic { gsave 4 index cvx exec /DataSource get resetfile translate 0 0
+ moveto neg rotate dup scale cvx exec image grestore endclip} def
+
+/scb { setrgbcolor } bind def /sce { defColor aload pop scb } bind def
+/cRedef {/defColor currentcolor 3 array astore def} def
+/begingate {dup type /dicttype ne {1 dict} if begin % default params
+ dup type /dicttype ne {1 dict} if begin % instanced params
+ /hlevel hlevel 1 add def /defColor currentcolor sce 3 array astore
+ def gsave sce dup type /nametype eq { pop } if translate 0 0 moveto
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+ {/clipped clipped 1 add def} if} bind def
+/endgate { /hlevel hlevel 1 sub def grestore defColor aload pop cRedef
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+
+/hlevel 0 def
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+ { 3 index exch 5 exch put dup -8 3 index { 3 index
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+/addtoy3 {3 exch addtoy pop} def
+/addtoy4 {4 exch addtoy pop} def
+/addtox {exch dup dup 2 mul 3 add 1 roll -1 1 { 4 1 roll dup 4 1 roll 3 -1 roll
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+/addtox1 {1 exch addtox pop} def
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+/addtox4 {4 exch addtox pop} def
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+/elb { matrix currentmatrix 7 -1 roll 7 -1 roll translate 5 1 roll 4 -1 roll
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+/nellip { elb ele arcn setmatrix } def
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+/inchscale {setpagemat 0.375 mul dup scale} def
+/cmscale {setpagemat 0.35433071 mul dup scale} def
+
+%%EndResource
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+/Encoding ISOLatin1Encoding def currentdict end
+/HelveticaISO exch definefont pop
+
+/Helvetica-Oblique findfont dup length dict begin
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+/Encoding ISOLatin1Encoding def currentdict end
+/Helvetica-ObliqueISO exch definefont pop
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+} def
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+(flash2 io0) {/Helvetica cf} 2 20 0.000 1.000 848 592 label
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+(for the user project.) {CR} (any use by the user) {CR} (be programmed to) {CR}
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+("pass-thru" mode) {CR} (accessed with the) {CR} (They can be) {CR}
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+label
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+{/HelveticaISO cf} (mm ) {hS}
+(\(see http://riscv.org/\), a 32-bit wishbone bus, and an approximately 2.8)
+{CR}
+(based on the simple 2-cycle PicoRV32 RISC-V core implementing the RV32IMC instruction set)
+{CR}
+(SkyWater 130nm open PDK. The Caravel harness comprises a small RISC-V microprocessor)
+{CR}
+(The efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/)
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+{CR} (the \252large\272 variant, incorporating options IRQ,) {CR}
+(github site. The hardware implementation is) {CR}
+(The full core description is available from the) {CR}
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+(process specifications and data at https://github.com/google/skywater-pdk/.)
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+(https://github.com/efabless/caravel/.) {CR}
+(The complete Caravel chip design may be obtained from the git repository located at)
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+(\(October 2020\).) {CR}
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+(user area power supply padframe pads into the user area for easier connecting.)
+{CR}
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+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 832 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 800 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 768 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 864 label
+(Digital I/O) {/Helvetica cf} 2 16 0.000 0.700 -392 1008 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 1040 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 1072 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 960 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 704 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 672 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 736 label
+(Housekeeping serial interface data input) {/Helvetica cf} 2 16 0.000 0.700
+-224 832 label
+(Housekeeping serial interface chip select) {/Helvetica cf} 2 16 0.000 0.700
+-224 800 label
+(Housekeeping serial interface clock) {/Helvetica cf} 2 16 0.000 0.700 -224 768
+label
+(Housekeeping serial interface data output) {/Helvetica cf} 2 16 0.000 0.700
+-224 864 label
+(Flash SPI data input/output) {/Helvetica cf} 2 16 0.000 0.700 -224 1008 label
+(Flash SPI chip select) {/Helvetica cf} 2 16 0.000 0.700 -224 1040 label
+(Flash SPI clock) {/Helvetica cf} 2 16 0.000 0.700 -224 1072 label
+(External CMOS 3.3V clock source) {/Helvetica cf} 2 16 0.000 0.700 -224 960
+label
+(UART receive channel) {/Helvetica cf} 2 16 0.000 0.700 -224 704 label
+(UART transmit channel) {/Helvetica cf} 2 16 0.000 0.700 -224 736 label
+(External interrupt) {/Helvetica cf} 2 16 0.000 0.700 -224 672 label
+(Efabless Caravel PicoRV32 SoC and User Project Harness) {/Helvetica cf} 2 28
+0.000 1.000 -864 1536 label
+(page 4) {/Helvetica cf} 2 31 0.000 0.700 368 1520 label
+(Standard package:) {/Helvetica cf} 2 16 0.000 0.700 -856 -112 label
+(WLCSP \(bump bond\)) {/Helvetica cf} 2 16 0.000 0.700 -568 -112 label
+(Bump pitch:) {/Helvetica cf} 2 16 0.000 0.700 -856 -176 label
+(mm) {hS} (0.5) {/Helvetica cf} 4 16 0.000 0.700 -568 -176 label
+(Package size:) {/Helvetica cf} 2 16 0.000 0.700 -856 -144 label
+(mm) {qS} (\327 5.3) {/HelveticaISO cf} (mm ) {qS} (3.2) {/Helvetica cf} 8 16
+0.000 0.700 -568 -144 label
+(F9) {/Helvetica cf} 2 16 0.000 0.700 -864 464 label
+(F8) {/Helvetica cf} 2 16 0.000 0.700 -864 432 label
+(E8) {/Helvetica cf} 2 16 0.000 0.700 -864 400 label
+(E9) {/Helvetica cf} 2 16 0.000 0.700 -864 368 label
+(spi_sdi) {/Helvetica cf} 2 16 0.000 0.700 -624 368 label
+(spi_csb) {/Helvetica cf} 2 16 0.000 0.700 -624 400 label
+(spi_sck) {/Helvetica cf} 2 16 0.000 0.700 -624 432 label
+(spi_sdo) {/Helvetica cf} 2 16 0.000 0.700 -624 464 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 368 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 400 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 432 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 464 label
+(Serial interface masterdata input) {/Helvetica cf} 2 16 0.000 0.700 -224 368
+label
+(Serial interface master chip select) {/Helvetica cf} 2 16 0.000 0.700 -224 400
+label
+(Serial interface master clock) {/Helvetica cf} 2 16 0.000 0.700 -224 432 label
+(Serial interface master data output) {/Helvetica cf} 2 16 0.000 0.700 -224 464
+label
+(C7) {/Helvetica cf} 2 16 0.000 0.700 -864 32 label
+(B7) {/Helvetica cf} 2 16 0.000 0.700 -864 -64 label
+(A10) {/Helvetica cf} 2 16 0.000 0.700 -864 256 label
+(B3) {/Helvetica cf} 2 16 0.000 0.700 -864 -32 label
+(A2) {/Helvetica cf} 2 16 0.000 0.700 -864 0 label
+(C5, C6, D5, D6) {/Helvetica cf} 2 16 0.000 0.700 -864 224 label
+(D4) {/Helvetica cf} 2 16 0.000 0.700 -864 176 label
+(E6) {/Helvetica cf} 2 16 0.000 0.700 -864 112 label
+(C4) {/Helvetica cf} 2 16 0.000 0.700 -864 320 label
+(F6) {/Helvetica cf} 2 16 0.000 0.700 -864 80 label
+(E10) {/Helvetica cf} 2 16 0.000 0.700 -864 640 label
+(vccd2) {/Helvetica cf} 2 16 0.000 0.700 -624 0 label
+(vssd2) {/Helvetica cf} 2 16 0.000 0.700 -624 -64 label
+(vccd) {/Helvetica cf} 2 16 0.000 0.700 -624 256 label
+(vssa2) {/Helvetica cf} 2 16 0.000 0.700 -624 -32 label
+(vdda2) {/Helvetica cf} 2 16 0.000 0.700 -624 32 label
+(vssio/vssa/vssd) {/Helvetica cf} 2 16 0.000 0.700 -624 224 label
+(vdda1) {/Helvetica cf} 2 16 0.000 0.700 -624 176 label
+(vssa1) {/Helvetica cf} 2 16 0.000 0.700 -624 112 label
+(vddio) {/Helvetica cf} 2 16 0.000 0.700 -624 320 label
+(vssd1) {/Helvetica cf} 2 16 0.000 0.700 -624 80 label
+(gpio) {/Helvetica cf} 2 16 0.000 0.700 -624 640 label
+(F2) {/Helvetica cf} 2 16 0.000 0.700 -864 144 label
+(F10) {/Helvetica cf} 2 16 0.000 0.700 -864 288 label
+(vccd1) {/Helvetica cf} 2 16 0.000 0.700 -624 144 label
+(vdda) {/Helvetica cf} 2 16 0.000 0.700 -624 288 label
+(E9, D7) {CR} (E7, F8, E8, F9,) {CR} (E4, F5, E5, F7,) {CR} (D3, F3, E3, F4,)
+{CR} (D2, E1, F1, E2,) {CR} (B1, C2, C1, D1,) {CR} (A3, C3, A1, B2,) {CR}
+(A5, B5, A4, B4,) {CR} (C8, A7, A6, B6,) {CR} (A9, B9, A8, B8,) {/Helvetica cf}
+20 28 0.000 0.700 -864 1384 label
+(Digital I/O) {/Helvetica cf} 2 16 0.000 0.700 -392 1360 label
+(General purpose configurable digital I/O with) {/Helvetica cf} 2 16 0.000
+0.700 -224 1360 label
+(and the management SoC.) {CR} (control. Shared between the user project area)
+{CR} (analog output, high voltage output, slew rate) {CR}
+(pullup/pulldown, input or output, enable/disable,) {CR}
+(General purpose configurable digital I/O with) {/Helvetica cf} 10 28 0.000
+0.700 -224 1328 label
+(mprj_io[37:0]) {/Helvetica cf} 2 16 0.000 0.700 -624 1360 label
+(D8) {/Helvetica cf} 2 16 0.000 0.700 -864 1072 label
+(B10) {/Helvetica cf} 2 16 0.000 0.700 -864 912 label
+(resetb) {/Helvetica cf} 2 16 0.000 0.700 -624 912 label
+(Digital in) {/Helvetica cf} 2 16 0.000 0.700 -392 912 label
+(SoC system reset \(sense inverted\)) {/Helvetica cf} 2 16 0.000 0.700 -224 912
+label
+(D7) {/Helvetica cf} 2 16 0.000 0.700 -864 608 label
+(JTAG) {/Helvetica cf} 2 16 0.000 0.700 -624 608 label
+(Digital I/O) {/Helvetica cf} 2 16 0.000 0.700 -392 608 label
+(JTAG system access) {/Helvetica cf} 2 16 0.000 0.700 -224 608 label
+(F5) {/Helvetica cf} 2 16 0.000 0.700 -864 576 label
+(flash2 csb) {/Helvetica cf} 2 16 0.000 0.700 -624 576 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 576 label
+(User area QSPI flash enable \(sense inverted\)) {/Helvetica cf} 2 16 0.000
+0.700 -224 576 label
+(E4) {/Helvetica cf} 2 16 0.000 0.700 -864 544 label
+(flash2 sck) {/Helvetica cf} 2 16 0.000 0.700 -624 544 label
+(Digital out) {/Helvetica cf} 2 16 0.000 0.700 -392 544 label
+(User area QSPI flash clock) {/Helvetica cf} 2 16 0.000 0.700 -224 544 label
+(E3, F4) {/Helvetica cf} 2 16 0.000 0.700 -864 512 label
+(flash2 io1:0) {/Helvetica cf} 2 16 0.000 0.700 -624 512 label
+(Digital I/O) {/Helvetica cf} 2 16 0.000 0.700 -392 512 label
+(User area QSPI flash data) {/Helvetica cf} 2 16 0.000 0.700 -224 512 label
+(Digital I/O) {/Helvetica cf} 2 16 0.000 0.700 -392 640 label
+(Management GPIO/user power enable) {/Helvetica cf} 2 16 0.000 0.700 -224 640
+label
+(ESD and padframe power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 320 label
+(3.3V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 288 label
+(Management area power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 288 label
+(1.8V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 256 label
+(Management area digital power supply) {/Helvetica cf} 2 16 0.000 0.700 -224
+256 label
+(ESD, padframe, and management area ground) {/Helvetica cf} 2 16 0.000 0.700
+-224 224 label
+(3.3V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 176 label
+(User area 1 power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 176 label
+(1.8V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 144 label
+(User area 1 digital power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 144
+label
+(Ground) {/Helvetica cf} 2 16 0.000 0.700 -400 112 label
+(User area 1 ground) {/Helvetica cf} 2 16 0.000 0.700 -224 112 label
+(Ground) {/Helvetica cf} 2 16 0.000 0.700 -400 80 label
+(User area 1 digital ground) {/Helvetica cf} 2 16 0.000 0.700 -224 80 label
+(3.3V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 32 label
+(User area 2 power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 32 label
+(1.8V Power) {/Helvetica cf} 2 16 0.000 0.700 -400 0 label
+(User area 2 digital power supply) {/Helvetica cf} 2 16 0.000 0.700 -224 0
+label
+(Ground) {/Helvetica cf} 2 16 0.000 0.700 -400 -32 label
+(User area 2 ground) {/Helvetica cf} 2 16 0.000 0.700 -224 -32 label
+(Ground) {/Helvetica cf} 2 16 0.000 0.700 -400 -64 label
+(User area 2 digital ground) {/Helvetica cf} 2 16 0.000 0.700 -224 -64 label
+pgsave restore showpage
+
+%%Page: gpio 5
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1184 960 translate
+
+0.600 0.600 0.600 scb
+0 1.000 -912 -32 -912 480 -368 480 -368 -32 4 polygon
+0.800 0.800 0.800 scb
+0 1.000 -320 -256 -320 16 208 16 208 -256 4 polygon
+0.679 1.000 0.184 scb
+512 1.000 -992 960 -992 -768 256 -768 256 960 4 polygon
+sce
+(Functional Description) {/Helvetica-Bold cf} 2 16 0.000 0.700 -992 928 label
+1 1.000 -992 912 256 912 2 polygon
+(GPIO \(pin E10\)) {/Helvetica cf} 2 16 0.000 0.700 -480 864 label
+(General Purpose I/O) {/Helvetica-Bold cf} 2 16 0.000 0.700 -992 864 label
+( are immediate. ) {/Helvetica cf} (reg_gpio_data) {/Helvetica-Bold cf}
+(All reads from ) {CR} (are registered.) {/Helvetica cf} (reg_gpio_data )
+{/Courier-Bold cf}
+(The basic function of the GPIO is illustrated below. All writes to )
+{/Helvetica cf} 12 16 0.000 0.700 -992 624 label
+(0x21000000) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -416 label
+(GPIO input/output \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700 -352 -416
+label
+(0x21000004) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -496 label
+(GPIO output enable \(0 = output, 1 = input\)) {/Helvetica cf} 2 16 0.000 0.700
+-352 -496 label
+(0x21000008) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -544 label
+(GPIO pullup enable \(1 = pullup, 0 = none\)) {/Helvetica cf} 2 16 0.000 0.700
+-352 -544 label
+(0x2100000c) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -592 label
+(GPIO pulldown enable \(1 = pulldown, 0 = none\)) {/Helvetica cf} 2 16 0.000
+0.700 -352 -592 label
+(reg_gpio_data) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -416 label
+(reg_gpio_ena) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -496 label
+(reg_gpio_pu) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -544 label
+(reg_gpio_pd) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -592 label
+(GPIO memory address map:) {/Helvetica cf} 2 16 0.000 0.700 -976 -320 label
+(Pin) {/Helvetica cf} 2 23 0.000 0.700 -928 224 label
+0.750 0.000 -736 368 analog::resistor
+0.750 0.000 -736 80 analog::resistor
+0.750 0.000 -736 288 analog::switch
+1 1.000 -736 240 -736 208 2 polygon
+1.000 0.000 -736 224 generic::dot
+0.750 0.000 -736 176 analog::switch
+0.750 0.000 -736 416 analog::vdd
+0.750 0.000 -736 32 analog::gnd
+0 1.000 -896 176 -896 272 -800 272 -800 176 4 polygon
+1 1.000 -896 176 -800 272 2 polygon
+1 1.000 -896 272 -800 176 2 polygon
+(reg_gpio_pu) {/Courier-Bold cf} 2 16 0.000 0.700 -704 256 label
+(reg_gpio_pd) {/Courier-Bold cf} 2 20 0.000 0.700 -704 160 label
+(reg_gpio_data) {/Courier-Bold cf} 2 16 0.000 0.700 -16 192 label
+-1.000 0.000 -416 288 digital::buffer
+1 1.000 -416 312 -416 448 2 polygon
+(reg_gpio_ena) {/Courier-Bold cf} 2 16 0.000 0.700 -312 440 label
+1 1.000 -480 288 -496 288 -496 224 3 polygon
+1.000 0.000 -496 224 generic::dot
+1 1.000 -336 320 -336 256 -272 224 -272 352 -336 320 5 polygon
+1 1.000 -80 -128 -80 -32 -144 0 -144 -160 -80 -128 5 polygon
+1 1.000 -336 288 -368 288 2 polygon
+1 1.000 -304 336 -304 384 -208 384 3 polygon
+1 1.000 -272 320 -112 320 2 polygon
+1 1.000 -272 256 -208 256 2 polygon
+(0x2f000000) {/Courier-Bold cf} 2 16 360.000 0.700 -576 -640 label
+(PLL clock output destination \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700
+-352 -640 label
+(0x2f000004) {/Courier-Bold cf} 2 16 360.000 0.700 -576 -688 label
+(Trap output destination \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700 -352
+-688 label
+(0x2f000008) {/Courier-Bold cf} 2 16 360.000 0.700 -576 -736 label
+(IRQ 7 input source \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700 -352 -736
+label
+(GPIO output readback \(16th bit\)) {/Helvetica cf} 2 16 0.000 0.700 -352 -448
+label
+1 1.000 -800 224 -496 224 2 polygon
+1 1.000 -496 224 -496 64 -32 64 3 polygon
+1.000 90.000 -48 64 generic::arrowhead
+-1.000 270.000 -192 192 generic::arrowhead
+1 1.000 -320 448 -416 448 2 polygon
+(I/O pad) {/Helvetica-Oblique cf} 2 28 0.000 0.700 -896 464 label
+1 1.000 -144 192 -208 192 -208 256 3 polygon
+(reg_pll_out_dest) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -640 label
+(reg_trap_out_dest) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -688 label
+(reg_irq7_source) {/Courier-Bold cf} 2 16 0.000 0.700 -976 -736 label
+(address) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -576 -368 label
+(description) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -352 -368 label
+(C header name) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -976 -368 label
+1 1.000 -976 -384 240 -384 2 polygon
+(function data bit) {/Helvetica-Oblique cf} 2 20 0.000 0.700 -96 320 label
+(function data enable) {/Helvetica-Oblique cf} 2 20 0.000 0.700 -192 384 label
+(0) {/Helvetica cf} 2 21 0.000 0.700 -288 256 label
+(1) {/Helvetica cf} 2 21 0.000 0.700 -288 320 label
+0 1.000 -144 160 -144 224 -80 224 -80 160 4 polygon
+(register) {/Helvetica-Oblique cf} 2 17 0.000 0.700 -112 240 label
+1 1.000 -80 192 -32 192 2 polygon
+1 1.000 -208 64 -208 -32 -144 -32 3 polygon
+1 1.000 -112 -144 -112 -208 2 polygon
+(IRQ select) {/Helvetica-Oblique cf} 2 29 0.000 0.700 -112 -224 label
+1 1.000 -144 -128 -224 -128 2 polygon
+1 1.000 -144 -96 -224 -96 2 polygon
+1 1.000 -144 -64 -224 -64 2 polygon
+(0) {/Helvetica cf} 2 23 0.000 0.700 -240 -128 label
+1.000 0.000 -208 64 generic::dot
+1 1.000 -352 288 -352 128 -32 128 3 polygon
+1.000 90.000 -48 128 generic::arrowhead
+1.000 0.000 -352 288 generic::dot
+1 1.000 -80 -80 0 -80 2 polygon
+(IRQ channel) {/Helvetica-Oblique cf} 2 20 0.000 0.700 16 -80 label
+-1.000 270.000 -80 192 generic::arrowhead
+(reg_gpio_data) {/Courier-Bold cf} 2 16 0.000 0.700 -16 128 label
+(\(read, 16th bit\)) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -16 96 label
+(\(read, low bit\)) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -16 32 label
+(reg_gpio_data) {/Courier-Bold cf} 2 16 0.000 0.700 -16 64 label
+(0) {/Helvetica cf} 2 21 0.000 0.700 -128 -128 label
+(other IRQ sources) {/Helvetica-Oblique cf} 2 23 0.000 0.700 -240 -80 label
+1 1.000 -96 -208 -96 -136 2 polygon
+(Figure 1. GPIO channel structure) {/Helvetica-Oblique cf} 2 16 0.000 0.700
+-976 -256 label
+0.800 0.800 0.800 scb
+224 1.000 -992 -272 -992 496 256 496 256 -272 4 polygon
+sce
+(page 5) {/Helvetica cf} 2 31 0.000 0.700 240 944 label
+(\(see Tables TBD\)) {/Helvetica cf} 2 20 0.000 0.700 -144 352 label
+(\(see Table TBD\)) {/Helvetica cf} 2 19 0.000 0.700 -176 -176 label
+(user area power supplies.) {CR}
+(with the completed user projects, this pin is used to enable the voltage regulators generating the)
+{CR}
+(the management SoC and cannot be assigned to the user project area. On the test board provided)
+{CR}
+(The GPI pin is a single assignable general-purpose digital input or output that is available only to)
+{/Helvetica cf} 8 28 0.000 0.700 -992 816 label
+pgsave restore showpage
+
+%%Page: gpio2 6
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 992 992 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -800 928 -800 -800 448 -800 448 928 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -800 896 label
+1 1.000 -800 880 448 880 2 polygon
+(GPIO description, continued.) {/Helvetica cf} 2 16 0.000 0.700 -800 832 label
+0 1.000 -752 496 -752 544 272 544 272 496 4 polygon
+1 1.000 -720 496 -720 448 2 polygon
+1 1.000 -688 496 -688 448 2 polygon
+1 1.000 -656 496 -656 448 2 polygon
+1 1.000 -624 496 -624 448 2 polygon
+1 1.000 -592 496 -592 448 2 polygon
+1 1.000 -560 496 -560 448 2 polygon
+1 1.000 -528 496 -528 448 2 polygon
+1 1.000 -496 496 -496 448 2 polygon
+1 1.000 -464 496 -464 448 2 polygon
+1 1.000 -432 496 -432 448 2 polygon
+1 1.000 -400 496 -400 448 2 polygon
+1 1.000 -368 496 -368 448 2 polygon
+1 1.000 -336 496 -336 448 2 polygon
+1 1.000 -304 496 -304 448 2 polygon
+1 1.000 -272 496 -272 448 2 polygon
+1 1.000 -240 592 -240 448 2 polygon
+1 1.000 -208 496 -208 448 2 polygon
+1 1.000 -176 496 -176 448 2 polygon
+1 1.000 -144 496 -144 448 2 polygon
+1 1.000 -112 496 -112 448 2 polygon
+1 1.000 -80 496 -80 448 2 polygon
+1 1.000 -48 496 -48 448 2 polygon
+1 1.000 -16 496 -16 448 2 polygon
+1 1.000 16 496 16 448 2 polygon
+1 1.000 48 496 48 448 2 polygon
+1 1.000 80 496 80 448 2 polygon
+1 1.000 112 496 112 448 2 polygon
+1 1.000 144 496 144 448 2 polygon
+1 1.000 176 496 176 448 2 polygon
+1 1.000 208 496 208 448 2 polygon
+1 1.000 240 496 240 448 2 polygon
+(reg_gpio_data) {/Courier-Bold cf} 2 16 0.000 0.700 -336 608 label
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 472 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 472 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 472 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 472 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 472 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 472 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 472 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 472 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 472 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 472 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 472 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 472 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 472 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 472 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 472 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 472 label
+sce
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 472 label
+0.600 0.600 0.600 scb
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 472 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 472 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 472 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 472 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 472 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 472 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 472 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 472 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 472 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 472 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 472 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 472 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 472 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 472 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 472 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 480 label
+(0x21000000) {/Courier-Bold cf} 2 16 0.000 0.700 64 560 label
+1 1.000 16 544 16 592 2 polygon
+1 1.000 -496 544 -496 592 2 polygon
+1 1.000 -752 592 -752 544 2 polygon
+1 1.000 272 592 272 544 2 polygon
+1 1.000 272 496 272 448 2 polygon
+1 1.000 -752 496 -752 448 2 polygon
+(0x21000001) {/Courier-Bold cf} 2 16 0.000 0.700 -192 560 label
+(0x21000002) {/Courier-Bold cf} 2 16 0.000 0.700 -448 560 label
+(0x21000003) {/Courier-Bold cf} 2 16 0.000 0.700 -704 560 label
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 560 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 528 label
+(GPIO output readback) {/Helvetica cf} 2 17 0.000 0.700 -496 512 label
+(GPIO input/output) {/Helvetica cf} 2 17 0.000 0.700 16 512 label
+1 1.000 -752 592 272 592 2 polygon
+1 1.000 -752 448 272 448 2 polygon
+0 1.000 -752 96 -752 144 272 144 272 96 4 polygon
+1 1.000 -720 96 -720 48 2 polygon
+1 1.000 -688 96 -688 48 2 polygon
+1 1.000 -656 96 -656 48 2 polygon
+1 1.000 -624 96 -624 48 2 polygon
+1 1.000 -592 96 -592 48 2 polygon
+1 1.000 -560 96 -560 48 2 polygon
+1 1.000 -528 96 -528 48 2 polygon
+1 1.000 -496 96 -496 48 2 polygon
+1 1.000 -464 96 -464 48 2 polygon
+1 1.000 -432 96 -432 48 2 polygon
+1 1.000 -400 96 -400 48 2 polygon
+1 1.000 -368 96 -368 48 2 polygon
+1 1.000 -336 96 -336 48 2 polygon
+1 1.000 -304 96 -304 48 2 polygon
+1 1.000 -272 96 -272 48 2 polygon
+1 1.000 -240 192 -240 48 2 polygon
+1 1.000 -208 96 -208 48 2 polygon
+1 1.000 -176 96 -176 48 2 polygon
+1 1.000 -144 96 -144 48 2 polygon
+1 1.000 -112 96 -112 48 2 polygon
+1 1.000 -80 96 -80 48 2 polygon
+1 1.000 -48 96 -48 48 2 polygon
+1 1.000 -16 96 -16 48 2 polygon
+1 1.000 16 96 16 48 2 polygon
+1 1.000 48 96 48 48 2 polygon
+1 1.000 80 96 80 48 2 polygon
+1 1.000 112 96 112 48 2 polygon
+1 1.000 144 96 144 48 2 polygon
+1 1.000 176 96 176 48 2 polygon
+1 1.000 208 96 208 48 2 polygon
+1 1.000 240 96 240 48 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 72 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 72 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 72 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 72 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 72 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 72 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 72 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 72 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 72 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 72 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 72 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 72 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 72 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 72 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 72 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 72 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 72 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 72 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 72 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 72 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 72 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 72 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 72 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 72 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 72 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 72 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 72 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 72 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 72 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 72 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 72 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 72 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 80 label
+(0x21000004) {/Courier-Bold cf} 2 16 0.000 0.700 64 160 label
+1 1.000 16 144 16 192 2 polygon
+1 1.000 -496 144 -496 192 2 polygon
+1 1.000 -752 192 -752 144 2 polygon
+1 1.000 272 192 272 144 2 polygon
+1 1.000 272 96 272 48 2 polygon
+1 1.000 -752 96 -752 48 2 polygon
+(0x21000005) {/Courier-Bold cf} 2 16 0.000 0.700 -192 160 label
+0.600 0.600 0.600 scb
+(0x21000006) {/Courier-Bold cf} 2 16 0.000 0.700 -448 160 label
+(0x21000007) {/Courier-Bold cf} 2 16 0.000 0.700 -704 160 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 160 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 128 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -496 112 label
+(GPIO output enable) {/Helvetica cf} 2 17 0.000 0.700 16 112 label
+1 1.000 -752 192 272 192 2 polygon
+1 1.000 -752 48 272 48 2 polygon
+(Writing to the address low bit always sets the registered value at the GPIO.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 368 label
+(Writing to address bit 16 has no effect.) {/Helvetica cf} 2 16 0.000 0.700
+-752 336 label
+(Reading from the address low bit reads the value at the chip pin.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 304 label
+
+(Reading from address bit 16 reads the value at the multiplexer output \(see diagram\).)
+{/Helvetica cf} 2 16 0.000 0.700 -752 272 label
+(Bit 0 corresponds to the GPIO channel enable.) {/Helvetica cf} 2 16 0.000
+0.700 -752 0 label
+(reg_gpio_ena) {/Courier-Bold cf} 2 16 0.000 0.700 -336 208 label
+(or one 8-bit byte.) {CR}
+(instruction and data type, the entire 32-bit register can be read in one instruction, or one 16-bit word,)
+{CR}
+(to the data bus width of the wishbone bus. Addresses, however, are in bytes. Depending on the)
+{CR}
+(In the memory-mapped register descriptions below, each register is shown as 32 bits corresponding)
+{/Helvetica cf} 8 16 0.000 0.700 -800 688 label
+(Bit value 1 indicates an output channel; 0 indicates an input.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 -32 label
+0 1.000 -752 -224 -752 -176 272 -176 272 -224 4 polygon
+1 1.000 -720 -224 -720 -272 2 polygon
+1 1.000 -688 -224 -688 -272 2 polygon
+1 1.000 -656 -224 -656 -272 2 polygon
+1 1.000 -624 -224 -624 -272 2 polygon
+1 1.000 -592 -224 -592 -272 2 polygon
+1 1.000 -560 -224 -560 -272 2 polygon
+1 1.000 -528 -224 -528 -272 2 polygon
+1 1.000 -496 -224 -496 -272 2 polygon
+1 1.000 -464 -224 -464 -272 2 polygon
+1 1.000 -432 -224 -432 -272 2 polygon
+1 1.000 -400 -224 -400 -272 2 polygon
+1 1.000 -368 -224 -368 -272 2 polygon
+1 1.000 -336 -224 -336 -272 2 polygon
+1 1.000 -304 -224 -304 -272 2 polygon
+1 1.000 -272 -224 -272 -272 2 polygon
+1 1.000 -240 -128 -240 -272 2 polygon
+1 1.000 -208 -224 -208 -272 2 polygon
+1 1.000 -176 -224 -176 -272 2 polygon
+1 1.000 -144 -224 -144 -272 2 polygon
+1 1.000 -112 -224 -112 -272 2 polygon
+1 1.000 -80 -224 -80 -272 2 polygon
+1 1.000 -48 -224 -48 -272 2 polygon
+1 1.000 -16 -224 -16 -272 2 polygon
+1 1.000 16 -224 16 -272 2 polygon
+1 1.000 48 -224 48 -272 2 polygon
+1 1.000 80 -224 80 -272 2 polygon
+1 1.000 112 -224 112 -272 2 polygon
+1 1.000 144 -224 144 -272 2 polygon
+1 1.000 176 -224 176 -272 2 polygon
+1 1.000 208 -224 208 -272 2 polygon
+1 1.000 240 -224 240 -272 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 -248 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 -248 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 -248 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 -248 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 -248 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 -248 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 -248 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 -248 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 -248 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 -248 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 -248 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 -248 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 -248 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 -248 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 -248 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 -248 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 -248 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 -248 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 -248 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 -248 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 -248 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 -248 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 -248 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 -248 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 -248 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 -248 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 -248 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 -248 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 -248 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 -248 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 -248 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 -248 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 -240 label
+(0x21000008) {/Courier-Bold cf} 2 16 0.000 0.700 64 -160 label
+1 1.000 16 -176 16 -128 2 polygon
+1 1.000 -496 -176 -496 -128 2 polygon
+1 1.000 -752 -128 -752 -176 2 polygon
+1 1.000 272 -128 272 -176 2 polygon
+1 1.000 272 -224 272 -272 2 polygon
+1 1.000 -752 -224 -752 -272 2 polygon
+(0x21000009) {/Courier-Bold cf} 2 16 360.000 0.700 -192 -160 label
+0.600 0.600 0.600 scb
+(0x2100000a) {/Courier-Bold cf} 2 16 0.000 0.700 -448 -160 label
+(0x2100000b) {/Courier-Bold cf} 2 16 0.000 0.700 -704 -160 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 -160 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 -192 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -496 -208 label
+(GPIO pin pull-up) {/Helvetica cf} 2 17 0.000 0.700 16 -208 label
+1 1.000 -752 -128 272 -128 2 polygon
+1 1.000 -752 -272 272 -272 2 polygon
+(Bit value 1 indicates pullup is active; 0 indicates pullup inactive.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 -352 label
+(reg_gpio_pu) {/Courier-Bold cf} 2 16 0.000 0.700 -336 -112 label
+0 1.000 -752 -544 -752 -496 272 -496 272 -544 4 polygon
+1 1.000 -720 -544 -720 -592 2 polygon
+1 1.000 -688 -544 -688 -592 2 polygon
+1 1.000 -656 -544 -656 -592 2 polygon
+1 1.000 -624 -544 -624 -592 2 polygon
+1 1.000 -592 -544 -592 -592 2 polygon
+1 1.000 -560 -544 -560 -592 2 polygon
+1 1.000 -528 -544 -528 -592 2 polygon
+1 1.000 -496 -544 -496 -592 2 polygon
+1 1.000 -464 -544 -464 -592 2 polygon
+1 1.000 -432 -544 -432 -592 2 polygon
+1 1.000 -400 -544 -400 -592 2 polygon
+1 1.000 -368 -544 -368 -592 2 polygon
+1 1.000 -336 -544 -336 -592 2 polygon
+1 1.000 -304 -544 -304 -592 2 polygon
+1 1.000 -272 -544 -272 -592 2 polygon
+1 1.000 -240 -448 -240 -592 2 polygon
+1 1.000 -208 -544 -208 -592 2 polygon
+1 1.000 -176 -544 -176 -592 2 polygon
+1 1.000 -144 -544 -144 -592 2 polygon
+1 1.000 -112 -544 -112 -592 2 polygon
+1 1.000 -80 -544 -80 -592 2 polygon
+1 1.000 -48 -544 -48 -592 2 polygon
+1 1.000 -16 -544 -16 -592 2 polygon
+1 1.000 16 -544 16 -592 2 polygon
+1 1.000 48 -544 48 -592 2 polygon
+1 1.000 80 -544 80 -592 2 polygon
+1 1.000 112 -544 112 -592 2 polygon
+1 1.000 144 -544 144 -592 2 polygon
+1 1.000 176 -544 176 -592 2 polygon
+1 1.000 208 -544 208 -592 2 polygon
+1 1.000 240 -544 240 -592 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 -568 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 -568 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 -568 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 -568 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 -568 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 -568 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 -568 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 -568 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 -568 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 -568 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 -568 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 -568 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 -568 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 -568 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 -568 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 -568 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 -568 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 -568 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 -568 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 -568 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 -568 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 -568 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 -568 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 -568 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 -568 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 -568 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 -568 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 -568 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 -568 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 -568 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 -568 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 -568 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 -560 label
+(0x2100000c) {/Courier-Bold cf} 2 16 0.000 0.700 64 -480 label
+1 1.000 16 -496 16 -448 2 polygon
+1 1.000 -496 -496 -496 -448 2 polygon
+1 1.000 -752 -448 -752 -496 2 polygon
+1 1.000 272 -448 272 -496 2 polygon
+1 1.000 272 -544 272 -592 2 polygon
+1 1.000 -752 -544 -752 -592 2 polygon
+(0x2100000d) {/Courier-Bold cf} 2 16 360.000 0.700 -192 -480 label
+0.600 0.600 0.600 scb
+(0x2100000e) {/Courier-Bold cf} 2 16 0.000 0.700 -448 -480 label
+(0x2100000f) {/Courier-Bold cf} 2 16 0.000 0.700 -704 -480 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 -480 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 -512 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -496 -528 label
+(GPIO pin pull-down \(inverted\)) {/Helvetica cf} 2 17 0.000 0.700 16 -528
+label
+1 1.000 -752 -448 272 -448 2 polygon
+1 1.000 -752 -592 272 -592 2 polygon
+(reg_gpio_pd) {/Courier-Bold cf} 2 16 0.000 0.700 -336 -432 label
+(Bit value 1 indicates pullup is active; 0 indicates pulldown is inactive.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 -672 label
+(Table 1) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 608 label
+(Table 2) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 208 label
+(Table 3) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 -112 label
+(Table 4) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 -432 label
+(page 6) {/Helvetica cf} 2 31 0.000 0.700 432 912 label
+(Bit 0 corresponds to the GPIO channel pull-up state.) {/Helvetica cf} 2 16
+0.000 0.700 -752 -320 label
+(Bit 0 corresponds to the GPIO channel pull-down state.) {/Helvetica cf} 2 16
+0.000 0.700 -752 -640 label
+pgsave restore showpage
+
+%%Page: gpio3 7
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1088 736 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -896 1184 -896 -544 352 -544 352 1184 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1152 label
+1 1.000 -896 1136 352 1136 2 polygon
+(GPIO description, continued.) {/Helvetica cf} 2 16 0.000 0.700 -896 1088 label
+0 1.000 -848 912 -848 960 176 960 176 912 4 polygon
+1 1.000 -816 912 -816 864 2 polygon
+1 1.000 -784 912 -784 864 2 polygon
+1 1.000 -752 912 -752 864 2 polygon
+1 1.000 -720 912 -720 864 2 polygon
+1 1.000 -688 912 -688 864 2 polygon
+1 1.000 -656 912 -656 864 2 polygon
+1 1.000 -624 912 -624 864 2 polygon
+1 1.000 -592 912 -592 864 2 polygon
+1 1.000 -560 912 -560 864 2 polygon
+1 1.000 -528 912 -528 864 2 polygon
+1 1.000 -496 912 -496 864 2 polygon
+1 1.000 -464 912 -464 864 2 polygon
+1 1.000 -432 912 -432 864 2 polygon
+1 1.000 -400 912 -400 864 2 polygon
+1 1.000 -368 912 -368 864 2 polygon
+1 1.000 -304 912 -304 864 2 polygon
+1 1.000 -272 912 -272 864 2 polygon
+1 1.000 -240 912 -240 864 2 polygon
+1 1.000 -208 912 -208 864 2 polygon
+1 1.000 -176 912 -176 864 2 polygon
+1 1.000 -144 912 -144 864 2 polygon
+1 1.000 -112 912 -112 864 2 polygon
+1 1.000 -80 912 -80 864 2 polygon
+1 1.000 -48 912 -48 864 2 polygon
+1 1.000 -16 912 -16 864 2 polygon
+1 1.000 16 912 16 864 2 polygon
+1 1.000 48 912 48 864 2 polygon
+1 1.000 80 912 80 864 2 polygon
+1 1.000 112 912 112 864 2 polygon
+1 1.000 144 912 144 864 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 160 888 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 128 888 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 96 888 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 64 888 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 32 888 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 0 888 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -32 888 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -64 888 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 -96 888 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -128 888 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -160 888 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -192 888 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -224 888 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -256 888 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -288 888 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -320 888 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -352 888 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -384 888 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -416 888 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -448 888 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -480 888 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -512 888 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -544 888 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -576 888 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -608 888 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -640 888 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -672 888 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -704 888 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -736 888 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -768 888 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -800 888 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -832 888 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 208 896 label
+(0x2f000000) {/Courier-Bold cf} 2 16 0.000 0.700 -32 976 label
+1 1.000 -80 960 -80 1008 2 polygon
+1 1.000 -592 960 -592 1008 2 polygon
+1 1.000 -848 1008 -848 960 2 polygon
+1 1.000 176 1008 176 960 2 polygon
+1 1.000 176 912 176 864 2 polygon
+1 1.000 -848 912 -848 864 2 polygon
+0.600 0.600 0.600 scb
+(0x2f000001) {/Courier-Bold cf} 2 16 360.000 0.700 -288 976 label
+(0x2f000002) {/Courier-Bold cf} 2 16 360.000 0.700 -544 976 label
+(0x2f000003) {/Courier-Bold cf} 2 16 0.000 0.700 -800 976 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 256 976 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 208 944 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -448 928 label
+1 1.000 -848 1008 176 1008 2 polygon
+1 1.000 -848 864 176 864 2 polygon
+(reg_pll_out_dest) {/Courier-Bold cf} 2 16 0.000 0.700 -432 1024 label
+1 1.000 -80 960 -80 912 2 polygon
+1 1.000 -336 1008 -336 960 2 polygon
+1 1.000 -336 912 -336 864 2 polygon
+(PLL clock dest.) {/Helvetica cf} 2 17 0.000 0.700 48 928 label
+(according to the following table:) {CR}
+(The low bit of this register directs the output of the core clock to the GPIO channel,)
+{/Helvetica cf} 4 28 0.000 0.700 -848 832 label
+( value) {/Helvetica cf} (0x2f000000) {/Courier-Bold cf} (Register byte )
+{/Helvetica cf} 6 16 0.000 0.700 -800 736 label
+(Clock output directed to this channel) {/Helvetica cf} 2 16 0.000 0.700 -352
+736 label
+(0) {/Courier-Bold cf} 2 16 0.000 0.700 -560 688 label
+(1) {/Courier-Bold cf} 2 16 0.000 0.700 -560 656 label
+(\(none\)) {/Helvetica cf} 2 16 0.000 0.700 -256 688 label
+1 1.000 -800 720 208 720 2 polygon
+1 1.000 -368 768 -368 640 2 polygon
+(0) {/Helvetica cf} 2 16 0.000 0.700 -704 688 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -704 656 label
+0 1.000 -848 336 -848 384 176 384 176 336 4 polygon
+1 1.000 -816 336 -816 288 2 polygon
+1 1.000 -784 336 -784 288 2 polygon
+1 1.000 -752 336 -752 288 2 polygon
+1 1.000 -720 336 -720 288 2 polygon
+1 1.000 -688 336 -688 288 2 polygon
+1 1.000 -656 336 -656 288 2 polygon
+1 1.000 -624 336 -624 288 2 polygon
+1 1.000 -592 336 -592 288 2 polygon
+1 1.000 -560 336 -560 288 2 polygon
+1 1.000 -528 336 -528 288 2 polygon
+1 1.000 -496 336 -496 288 2 polygon
+1 1.000 -464 336 -464 288 2 polygon
+1 1.000 -432 336 -432 288 2 polygon
+1 1.000 -400 336 -400 288 2 polygon
+1 1.000 -368 336 -368 288 2 polygon
+1 1.000 -304 336 -304 288 2 polygon
+1 1.000 -272 336 -272 288 2 polygon
+1 1.000 -240 336 -240 288 2 polygon
+1 1.000 -208 336 -208 288 2 polygon
+1 1.000 -176 336 -176 288 2 polygon
+1 1.000 -144 336 -144 288 2 polygon
+1 1.000 -112 336 -112 288 2 polygon
+1 1.000 -80 336 -80 288 2 polygon
+1 1.000 -48 336 -48 288 2 polygon
+1 1.000 -16 336 -16 288 2 polygon
+1 1.000 16 336 16 288 2 polygon
+1 1.000 48 336 48 288 2 polygon
+1 1.000 80 336 80 288 2 polygon
+1 1.000 112 336 112 288 2 polygon
+1 1.000 144 336 144 288 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 160 312 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 128 312 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 96 312 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 64 312 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 32 312 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 0 312 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -32 312 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -64 312 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 -96 312 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -128 312 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -160 312 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -192 312 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -224 312 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -256 312 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -288 312 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -320 312 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -352 312 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -384 312 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -416 312 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -448 312 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -480 312 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -512 312 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -544 312 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -576 312 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -608 312 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -640 312 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -672 312 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -704 312 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -736 312 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -768 312 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -800 312 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -832 312 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 208 320 label
+(0x2f000004) {/Courier-Bold cf} 2 16 0.000 0.700 -32 400 label
+1 1.000 -80 384 -80 432 2 polygon
+1 1.000 -592 384 -592 432 2 polygon
+1 1.000 -848 432 -848 384 2 polygon
+1 1.000 176 432 176 384 2 polygon
+1 1.000 176 336 176 288 2 polygon
+1 1.000 -848 336 -848 288 2 polygon
+0.600 0.600 0.600 scb
+(0x2f000005) {/Courier-Bold cf} 2 16 360.000 0.700 -288 400 label
+(0x2f000006) {/Courier-Bold cf} 2 16 360.000 0.700 -544 400 label
+(0x2f000007) {/Courier-Bold cf} 2 16 0.000 0.700 -800 400 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 256 400 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 208 368 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -448 352 label
+1 1.000 -848 432 176 432 2 polygon
+1 1.000 -848 288 176 288 2 polygon
+(reg_trap_out_dest) {/Courier-Bold cf} 2 16 0.000 0.700 -432 448 label
+1 1.000 -80 384 -80 336 2 polygon
+1 1.000 -336 432 -336 384 2 polygon
+1 1.000 -336 336 -336 288 2 polygon
+(trap signal dest.) {/Helvetica cf} 2 17 0.000 0.700 48 352 label
+(channel, according to the following table:) {CR}
+(The low bit of this register directs the output of the processor trap signal to the GPIO)
+{/Helvetica cf} 4 28 0.000 0.700 -848 256 label
+( value) {/Helvetica cf} (0x2f000004) {/Courier-Bold cf} (Register byte )
+{/Helvetica cf} 6 16 0.000 0.700 -800 160 label
+(Trap signal output directed to this channel) {/Helvetica cf} 2 16 0.000 0.700
+-320 160 label
+(0) {/Courier-Bold cf} 2 16 0.000 0.700 -560 112 label
+(1) {/Courier-Bold cf} 2 16 0.000 0.700 -560 80 label
+(GPIO) {/Helvetica cf} 2 16 0.000 0.700 -320 80 label
+(\(none\)) {/Helvetica cf} 2 16 0.000 0.700 -320 112 label
+1 1.000 -800 144 208 144 2 polygon
+1 1.000 -368 192 -368 64 2 polygon
+(0) {/Helvetica cf} 2 16 0.000 0.700 -704 112 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -704 80 label
+(Table 5) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -848 1024 label
+(Table 6) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -848 448 label
+(page 7) {/Helvetica cf} 2 31 0.000 0.700 336 1168 label
+(GPIO output.) {CR} (MHz\) may be unable to generate a full swing on the) {qS}
+(80) {/Helvetica cf} (e.g., ) {/Helvetica-Oblique cf}
+(Note that a high rate core clock \() {/Helvetica cf} 10 28 0.000 0.700 -848
+560 label
+(Core PLL clock to GPIO out) {/Helvetica cf} 2 16 0.000 0.700 -352 656 label
+0 1.000 -864 -192 -864 -144 160 -144 160 -192 4 polygon
+1 1.000 -832 -192 -832 -240 2 polygon
+1 1.000 -800 -192 -800 -240 2 polygon
+1 1.000 -768 -192 -768 -240 2 polygon
+1 1.000 -736 -192 -736 -240 2 polygon
+1 1.000 -704 -192 -704 -240 2 polygon
+1 1.000 -672 -192 -672 -240 2 polygon
+1 1.000 -640 -192 -640 -240 2 polygon
+1 1.000 -608 -192 -608 -240 2 polygon
+1 1.000 -576 -192 -576 -240 2 polygon
+1 1.000 -544 -192 -544 -240 2 polygon
+1 1.000 -512 -192 -512 -240 2 polygon
+1 1.000 -480 -192 -480 -240 2 polygon
+1 1.000 -448 -192 -448 -240 2 polygon
+1 1.000 -416 -192 -416 -240 2 polygon
+1 1.000 -384 -192 -384 -240 2 polygon
+1 1.000 -320 -192 -320 -240 2 polygon
+1 1.000 -288 -192 -288 -240 2 polygon
+1 1.000 -256 -192 -256 -240 2 polygon
+1 1.000 -224 -192 -224 -240 2 polygon
+1 1.000 -192 -192 -192 -240 2 polygon
+1 1.000 -160 -192 -160 -240 2 polygon
+1 1.000 -128 -192 -128 -240 2 polygon
+1 1.000 -96 -192 -96 -240 2 polygon
+1 1.000 -64 -192 -64 -240 2 polygon
+1 1.000 -32 -192 -32 -240 2 polygon
+1 1.000 0 -192 0 -240 2 polygon
+1 1.000 32 -192 32 -240 2 polygon
+1 1.000 64 -192 64 -240 2 polygon
+1 1.000 96 -192 96 -240 2 polygon
+1 1.000 128 -192 128 -240 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 144 -216 label
+0.600 0.600 0.600 scb
+(1) {/Helvetica cf} 2 21 0.000 0.500 112 -216 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 80 -216 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 48 -216 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 16 -216 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -16 -216 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -48 -216 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -80 -216 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 -112 -216 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -144 -216 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -176 -216 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -208 -216 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -240 -216 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -272 -216 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -304 -216 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -336 -216 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -368 -216 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -400 -216 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -432 -216 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -464 -216 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -496 -216 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -528 -216 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -560 -216 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -592 -216 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -624 -216 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -656 -216 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -688 -216 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -720 -216 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -752 -216 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -784 -216 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -816 -216 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -848 -216 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 192 -208 label
+(0x2f000008) {/Courier-Bold cf} 2 16 0.000 0.700 -48 -128 label
+1 1.000 -96 -144 -96 -96 2 polygon
+1 1.000 -608 -144 -608 -96 2 polygon
+1 1.000 -864 -96 -864 -144 2 polygon
+1 1.000 160 -96 160 -144 2 polygon
+1 1.000 160 -192 160 -240 2 polygon
+1 1.000 -864 -192 -864 -240 2 polygon
+0.600 0.600 0.600 scb
+(0x2f000009) {/Courier-Bold cf} 2 16 360.000 0.700 -304 -128 label
+(0x2f00000a) {/Courier-Bold cf} 2 16 360.000 0.700 -560 -128 label
+(0x2f00000b) {/Courier-Bold cf} 2 16 0.000 0.700 -816 -128 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 240 -128 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 192 -160 label
+(\(undefined, reads zero\)) {/Helvetica cf} 2 17 0.000 0.700 -464 -176 label
+1 1.000 -864 -96 160 -96 2 polygon
+1 1.000 -864 -240 160 -240 2 polygon
+(reg_irq7_source) {/Courier-Bold cf} 2 16 0.000 0.700 -448 -80 label
+1 1.000 -96 -144 -96 -192 2 polygon
+1 1.000 -352 -96 -352 -144 2 polygon
+1 1.000 -352 -192 -352 -240 2 polygon
+(IRQ 7 source) {/Helvetica cf} 2 17 0.000 0.700 32 -176 label
+(according to the following table:) {CR}
+(The low bit of this register directs the input of the GPIO to the processor\251s IRQ7 channel,)
+{/Helvetica cf} 4 28 0.000 0.700 -864 -272 label
+( value) {/Helvetica cf} (0x2f000008) {/Courier-Bold cf} (Register byte )
+{/Helvetica cf} 6 16 0.000 0.700 -816 -368 label
+(This channel directed to IRQ channel 7) {/Helvetica cf} 2 16 0.000 0.700 -336
+-368 label
+(00) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -416 label
+(01) {/Courier-Bold cf} 2 16 0.000 0.700 -576 -448 label
+(GPIO) {/Helvetica cf} 2 16 0.000 0.700 -304 -448 label
+(\(none\)) {/Helvetica cf} 2 16 0.000 0.700 -304 -416 label
+1 1.000 -816 -384 192 -384 2 polygon
+1 1.000 -384 -336 -384 -448 2 polygon
+(0) {/Helvetica cf} 2 16 0.000 0.700 -720 -416 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -720 -448 label
+(Table 7) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -864 -80 label
+pgsave restore showpage
+
+%%Page: hkspi 8
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1056 736 translate
+
+0.361 0.675 0.934 scb
+1 1.000 -144 680 -144 488 2 polygon
+1 1.000 -136 680 -136 488 2 polygon
+1 1.000 -656 664 -656 496 2 polygon
+0.679 1.000 0.184 scb
+512 1.000 -864 1184 -864 -544 384 -544 384 1184 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -864 1152 label
+1 1.000 -864 1136 384 1136 2 polygon
+(Housekeeping SPI) {/Helvetica-Bold cf} 2 16 0.000 0.700 -864 1088 label
+(SDI \(pin F9\), CSB \(pin E8\), SCK \(pin F8\), and SDO \(pin E9\))
+{/Helvetica cf} 2 16 0.000 0.700 -368 1088 label
+(SPI protocol definition) {/Helvetica-Bold cf} 2 16 0.000 0.700 -864 896 label
+1 1.000 -864 -192 384 -192 2 polygon
+(00000000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -224 label
+(No operation) {/Helvetica cf} 2 16 0.000 0.700 -448 -224 label
+(10000000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -256 label
+(01000000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -288 label
+(Write in streaming mode) {/Helvetica cf} 2 16 0.000 0.700 -448 -256 label
+(Read in streaming mode) {/Helvetica cf} 2 16 0.000 0.700 -448 -288 label
+(Simultaneous Read/Write in streaming mode) {/Helvetica cf} 2 16 0.000 0.700
+-448 -320 label
+(11000000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -320 label
+(10nnn000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -416 label
+1 1.000 -864 -496 384 -496 2 polygon
+(All input is in groups of 8 bits. Each byte is input msb first.)
+{/Helvetica cf} 2 16 0.000 0.700 -864 848 label
+
+(The first transferred byte is the command word, interpreted according to Table 8 below.)
+{/Helvetica cf} 2 16 0.000 0.700 -864 -112 label
+(SCK rising edge.) {CR}
+(outputs become active on the falling edge of SCK, such that data are written and read on the same)
+{CR}
+(when CSB is high and at all times other than the transfer of data bits on a read command. SDO)
+{CR}
+(on the rising edge of SCK. Output data are received on the SDO line. SDO is held high-impedance)
+{CR}
+(CSB pin must be low to enable an SPI transmission. Data are clocked by pin SCK, with data valid)
+{/Helvetica cf} 10 28 0.000 0.700 -864 144 label
+
+(After CSB is set low, the SPI is always in the "command" state, awaiting a new command.)
+{/Helvetica cf} 2 28 0.000 0.700 -864 -32 label
+(Addresses are read in sequence from lower values to higher values.)
+{/Helvetica cf} 2 28 0.000 0.700 -864 352 label
+
+(highest address. Any bits additional to an 8-bit boundary should be at the lowest address.)
+{CR}
+(Therefore groups of bits larger than 8 should be grouped such that the lowest bits are at the)
+{/Helvetica cf} 4 28 0.000 0.700 -864 304 label
+
+(byte transfer. Multi-byte transfers should ensure that data do not change between byte reads. )
+{CR}
+(Data are captured from the register map in bytes on the falling edge of the last SCK before a data)
+{/Helvetica cf} 4 28 0.000 0.700 -864 224 label
+(01nnn000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -448 label
+(11nnn000) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -480 label
+(Write in n-byte mode \(up to 7 bytes\).) {/Helvetica cf} 2 16 0.000 0.700 -448
+-416 label
+(Read in n-byte mode \(up to 7 bytes\).) {/Helvetica cf} 2 16 0.000 0.700 -448
+-448 label
+(Simultaneous Read/Write in n-byte mode \(up to 7 bytes\).) {/Helvetica cf} 2
+16 0.000 0.700 -448 -480 label
+(defined below.) {CR}
+(\(8 bits\) followed by one or more data words \(8 bits each\), according to the data transfer modes)
+{CR}
+(Every command sequence requires one command word \(8 bits\) followed by one address word)
+{/Helvetica cf} 6 28 0.000 0.700 -864 816 label
+
+(the next SCK rising edge\). The SPI pins are shared with user area general-purpose I/O.)
+{CR}
+(on the SCK rising edge, and output data presented on the falling edge of SCK \(to be sampled on)
+{CR}
+(standard 4-pin serial interface. The SPI implementation is mode 0, with new data on SDI captured)
+{CR}
+(The \252housekeeping\272 SPI is an SPI slave that can be accessed from a remote host through a)
+{/Helvetica cf} 8 28 0.000 0.700 -864 1056 label
+(CSB) {/Helvetica cf} 2 21 0.000 0.700 -816 656 label
+(SCK) {/Helvetica cf} 2 21 0.000 0.700 -816 608 label
+(SDI) {/Helvetica cf} 2 21 0.000 0.700 -816 560 label
+(SDO) {/Helvetica cf} 2 21 0.000 0.700 -816 512 label
+1 1.000 -736 672 -688 672 -688 640 160 640 4 polygon
+1 1.000 -656 592 -656 624 -640 624 -640 592 -624 592 -624 624 -608 624 -608 592
+-592 592 -592 624 -576 624 -576 592 -560 592 -560 624 -544 624 -544 592 -528
+592 -528 624 -512 624 -512 592 -496 592 -496 624 -480 624 -480 592 -464 592
+-464 624 -448 624 -448 592 -432 592 -432 624 -416 624 -416 592 -384 592 33
+polygon
+1 1.000 -384 592 -384 624 -368 624 -368 592 -352 592 -352 624 -336 624 -336 592
+-320 592 -320 624 -304 624 -304 592 -288 592 -288 624 -272 624 -272 592 -256
+592 -256 624 -240 624 -240 592 -224 592 -224 624 -208 624 -208 592 -192 592
+-192 624 -176 624 -176 592 -160 592 -160 624 -144 624 -144 592 -112 592 33
+polygon
+1 1.000 -112 592 -112 624 -96 624 -96 592 -80 592 -80 624 -64 624 -64 592 -48
+592 -48 624 -32 624 -32 592 -16 592 -16 624 0 624 0 592 16 592 16 624 32 624 32
+592 48 592 48 624 64 624 64 592 80 592 80 624 96 624 96 592 112 592 112 624 128
+624 128 592 160 592 33 polygon
+1 1.000 -656 592 -736 592 2 polygon
+1 1.000 -736 544 -672 544 -664 576 -416 576 -408 544 -128 544 -120 576 128 576
+136 544 160 544 10 polygon
+1 1.000 -672 544 -640 544 -632 576 3 polygon
+1 1.000 -640 544 -608 544 -600 576 3 polygon
+1 1.000 -608 544 -576 544 -568 576 3 polygon
+1 1.000 -576 544 -544 544 -536 576 3 polygon
+1 1.000 -544 544 -512 544 -504 576 3 polygon
+1 1.000 -512 544 -480 544 -472 576 3 polygon
+1 1.000 -480 544 -448 544 -440 576 3 polygon
+1 1.000 -448 544 -408 544 2 polygon
+1 1.000 -640 576 -632 544 2 polygon
+1 1.000 -608 576 -600 544 2 polygon
+1 1.000 -576 576 -568 544 2 polygon
+1 1.000 -544 576 -536 544 2 polygon
+1 1.000 -512 576 -504 544 2 polygon
+1 1.000 -480 576 -472 544 2 polygon
+1 1.000 -448 576 -440 544 2 polygon
+1 1.000 -400 544 -392 576 -144 576 -136 544 4 polygon
+1 1.000 -368 576 -360 544 2 polygon
+1 1.000 -360 576 -368 544 2 polygon
+1 1.000 -328 576 -336 544 2 polygon
+1 1.000 -336 576 -328 544 2 polygon
+1 1.000 -296 576 -304 544 2 polygon
+1 1.000 -304 576 -296 544 2 polygon
+1 1.000 -264 576 -272 544 2 polygon
+1 1.000 -272 576 -264 544 2 polygon
+1 1.000 -232 576 -240 544 2 polygon
+1 1.000 -240 576 -232 544 2 polygon
+1 1.000 -200 576 -208 544 2 polygon
+1 1.000 -208 576 -200 544 2 polygon
+1 1.000 -168 576 -176 544 2 polygon
+1 1.000 -176 576 -168 544 2 polygon
+1 1.000 -88 576 -96 544 2 polygon
+1 1.000 -96 576 -88 544 2 polygon
+1 1.000 -56 576 -64 544 2 polygon
+1 1.000 -64 576 -56 544 2 polygon
+1 1.000 -24 576 -32 544 2 polygon
+1 1.000 -32 576 -24 544 2 polygon
+1 1.000 8 576 0 544 2 polygon
+1 1.000 0 576 8 544 2 polygon
+1 1.000 40 576 32 544 2 polygon
+1 1.000 32 576 40 544 2 polygon
+1 1.000 72 576 64 544 2 polygon
+1 1.000 64 576 72 544 2 polygon
+1 1.000 104 576 96 544 2 polygon
+1 1.000 96 576 104 544 2 polygon
+1 1.000 -128 544 136 544 2 polygon
+1 1.000 128 496 136 528 160 528 3 polygon
+1 1.000 160 496 128 496 2 polygon
+1 1.000 96 496 -136 496 2 polygon
+0.600 0.600 0.600 scb
+1 1.000 160 688 160 480 2 polygon
+1 1.000 176 688 176 480 2 polygon
+sce
+1 1.000 176 592 304 592 2 polygon
+1 1.000 176 544 304 544 2 polygon
+1 1.000 176 528 192 528 2 polygon
+1 1.000 176 496 192 496 2 polygon
+1 1.000 192 528 196 512 2 polygon
+1 1.000 196 512 192 496 2 polygon
+1 1.000 196 512 304 512 2 polygon
+1 1.000 -140 512 -136 496 2 polygon
+1 1.000 -140 512 -136 528 96 528 104 496 4 polygon
+1 1.000 -140 512 -736 512 2 polygon
+1 1.000 -96 528 -88 496 2 polygon
+1 1.000 -96 496 -88 528 2 polygon
+1 1.000 -64 528 -56 496 2 polygon
+1 1.000 -64 496 -56 528 2 polygon
+1 1.000 -32 528 -24 496 2 polygon
+1 1.000 -32 496 -24 528 2 polygon
+1 1.000 0 528 8 496 2 polygon
+1 1.000 0 496 8 528 2 polygon
+1 1.000 32 528 40 496 2 polygon
+1 1.000 32 496 40 528 2 polygon
+1 1.000 64 528 72 496 2 polygon
+1 1.000 64 496 72 528 2 polygon
+1 1.000 96 496 104 528 2 polygon
+1 1.000 96 528 136 528 2 polygon
+1 1.000 96 496 128 496 2 polygon
+1 1.000 128 528 136 496 2 polygon
+
+(All other words are reserved and act as no-operation if not defined by the SPI slave module.)
+{/Helvetica cf} 2 16 0.000 0.700 -864 -528 label
+1 1.000 176 640 192 640 192 672 304 672 4 polygon
+(additional data bytes) {/Helvetica cf} 2 28 0.000 0.500 176 456 label
+0.500 0.000 168 472 generic::arrow
+1 1.000 -672 480 -664 472 -416 472 -408 480 4 polygon
+(command) {/Helvetica cf} 2 29 0.000 0.500 -552 464 label
+1 1.000 -400 480 -392 472 -136 472 -128 480 4 polygon
+(address) {/Helvetica cf} 2 29 0.000 0.500 -272 464 label
+1 1.000 -120 480 -112 472 160 472 3 polygon
+1 1.000 176 472 200 472 208 480 3 polygon
+(data) {/Helvetica cf} 2 29 0.000 0.500 16 464 label
+(msb) {/Helvetica cf} 2 23 0.000 0.500 -688 568 label
+(msb) {/Helvetica cf} 2 19 0.000 0.500 -152 520 label
+(lsb) {/Helvetica cf} 2 16 0.000 0.500 200 520 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -652 560 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -620 560 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -588 560 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 -556 560 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 -524 560 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 -492 560 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 -460 560 label
+(0) {/Helvetica cf} 2 21 0.000 0.500 -428 560 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -380 560 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -348 560 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -316 560 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 -284 560 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 -252 560 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 -220 560 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 -188 560 label
+(0) {/Helvetica cf} 2 21 0.000 0.500 -156 560 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -108 560 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -76 560 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -44 560 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 -12 560 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 20 560 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 52 560 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 84 560 label
+(0) {/Helvetica cf} 2 21 0.000 0.500 116 560 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -108 512 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 -76 512 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -44 512 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 -12 512 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 20 512 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 52 512 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 84 512 label
+(0) {/Helvetica cf} 2 21 0.000 0.500 116 512 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 148 512 label
+(high impedence) {/Helvetica cf} 2 16 0.000 0.500 -648 520 label
+(data must be valid on SCK rising edge) {/Helvetica cf} 2 16 0.000 0.500 -656
+672 label
+(data valid on SCK falling edge) {/Helvetica cf} 2 16 0.000 0.500 -128 672
+label
+0.361 0.675 0.934 scb
+1 1.000 -112 584 -112 416 2 polygon
+sce
+(capture data on SCK rising edge) {/Helvetica cf} 2 16 0.000 0.500 -104 416
+label
+(Table 8) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -864 -176 label
+(Housekeeping SPI command word definition) {/Helvetica cf} 2 16 0.000 0.700
+-720 -176 label
+(Figure 2. Housekeeping SPI signaling) {/Helvetica-Oblique cf} 2 16 0.000
+0.700 -848 400 label
+0.800 0.800 0.800 scb
+224 1.000 -864 384 -864 704 384 704 384 384 4 polygon
+sce
+(page 8) {/Helvetica cf} 2 31 0.000 0.700 368 1168 label
+(11000100) {/Courier-Bold cf} 2 16 0.000 0.700 -736 -352 label
+(Pass-through \(management\) Read/Write in streaming mode) {/Helvetica cf} 2 16
+0.000 0.700 -448 -352 label
+(11000110) {/Courier-Bold cf} 2 16 360.000 0.700 -736 -384 label
+(Pass-through \(user\) Read/Write in streaming mode) {/Helvetica cf} 2 16 0.000
+0.700 -448 -384 label
+pgsave restore showpage
+
+%%Page: hkspi2 9
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1023 704 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -832 1216 -832 -512 416 -512 416 1216 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -832 1184 label
+1 1.000 -832 1168 416 1168 2 polygon
+(transfer. ) {CR}
+(incrementing for each byte. Streaming mode operation continues until CSB is raised to end the)
+{CR}
+(operation, data are sent or received continuously, one byte at a time, with the internal address)
+{CR}
+(The two basic modes of operation are "streaming mode" and "n-byte mode". In "streaming mode")
+{/Helvetica cf} 8 28 0.000 0.700 -832 1088 label
+(command.) {CR}
+(command. No toggling of CSB is required to end the command or to initiate the following)
+{CR}
+(mode\). After n bytes have been read and/or written, the SPI returns to waiting for the next)
+{CR}
+(command word, and may have a value from 1 to 7 \(note that a value of zero implies streaming)
+{CR}
+(In "n-byte mode" operation, the number of bytes to be read and/or written is encoded in the)
+{/Helvetica cf} 10 28 0.000 0.700 -832 944 label
+(\(continued\)) {/Helvetica-Oblique cf} (SPI protocol definition )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -832 1120 label
+(clock speed of the CPU. All other functions are purely for test and debug.)
+{CR}
+(Under normal working conditions, the SPI should not need to be accessed unless it is to adjust the)
+{/Helvetica cf} 4 28 0.000 0.700 -832 -32 label
+(manufacturer_ID) {/Helvetica-Bold cf} 2 16 0.000 0.700 -832 -272 label
+(The 12-bit manufacturer ID for efabless is 0x456) {/Helvetica cf} 2 16 0.000
+0.700 -768 -304 label
+(Housekeeping SPI registers) {/Helvetica-Bold cf} 2 16 0.000 0.700 -832 160
+label
+(register address 0x01 low 4 bits and register address 0x02) {/Helvetica cf} 2
+16 0.000 0.700 -496 -272 label
+(page 9) {/Helvetica cf} 2 31 0.000 0.700 400 1200 label
+(Pass-thru mode) {/Helvetica-Bold cf} 2 16 0.000 0.700 -832 752 label
+(program start address. ) {CR}
+(transfer to the QSPI flash. The CPU is brought out of reset, and starts executing instructions at the)
+{CR}
+(CSB pin is raised. When CSB is raised, the FLASH_CSB is also raised, terminating the data)
+{CR}
+(respectively\), and the QSPI flash data output \(pin FLASH_IO1\) is applied directly to SDO, until the)
+{CR}
+(signaling on SDI and SCK are applied directly to the QSPI flash \(pins FLASH_IO0 and FLASH_CLK,)
+{CR}
+(transfer to the QSPI flash. After the pass-thru command byte has been issued, all subsequent SPI)
+{CR}
+(The pass-thru mode puts the CPU into immediate reset, then sets FLASH_CSB low to initiate a data)
+{/Helvetica cf} 14 28 0.000 0.700 -832 720 label
+
+(the housekeeping SPI, without the need for additional wiring to the QSPI flash chip.)
+{CR}
+(This mode allows the QSPI flash to be programmed from the same SPI communication channel as)
+{/Helvetica cf} 4 28 0.000 0.700 -832 496 label
+(the SPI flash in quad mode using a 6-pin interface.) {CR}
+(flash chips, and so must operate only in the 4-pin SPI mode. The user project may elect to operate)
+{CR}
+(external access to the SPI flash. Both pass-thru modes only connect to I/O pins 0 and 1 of the SPI)
+{CR}
+(Caravel chip program either SPI flash chip from a host computer without requiring separate)
+{CR}
+(defined in the user project. The pass-thru mode allows a communications chip external to the)
+{CR}
+(management SoC. The second one corresponds to a secondary optional SPI flash that can be)
+{CR}
+(There are two pass-thru modes. The first one corresponds to the primary SPI flash used by the)
+{/Helvetica cf} 14 28 0.000 0.700 -832 416 label
+(frequency-locked loop generating the CPU core clock.) {CR}
+(potentially can be detrimental to the CPU operation, such as adjusting the trim value of the digital)
+{CR}
+(reset. Some control registers in the housekeeping SPI affect the behavior of the CPU in a way that)
+{CR}
+(independently of the CPU. The housekeeping SPI can be accessed even when the CPU is in full)
+{CR}
+(The purpose of the housekeeping SPI is to give access to certain system values and controls)
+{/Helvetica cf} 10 28 0.000 0.700 -832 128 label
+(the SPI master description for details.) {CR}
+(This configuration then allows a program to read, for example, the user project ID of the chip. See)
+{CR}
+(master, and enabling the bit that connects the internal SPI master directly to the housekeeping SPI.)
+{CR}
+(The housekeeping SPI can be accessed by the CPU from a running program by enabling the SPI)
+{/Helvetica cf} 8 28 0.000 0.700 -832 -112 label
+(product_ID) {/Helvetica-Bold cf} 2 16 0.000 0.700 -832 -368 label
+(The product ID for the Caravel harness chip is 0x10) {/Helvetica cf} 2 16
+0.000 0.700 -768 -400 label
+(register address 0x03) {/Helvetica cf} 2 16 0.000 0.700 -496 -368 label
+pgsave restore showpage
+
+%%Page: hskspi3 10
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1088 672 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -896 1248 -896 -480 352 -480 352 1248 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1216 label
+1 1.000 -896 1200 352 1200 2 polygon
+(\(continued\)) {/Helvetica-Oblique cf} (Housekeeping SPI registers )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1152 label
+(CPU reset) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 400 label
+(CPU trap) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 288 label
+(must be set back to zero manually to clear the reset state.) {CR}
+(The CPU reset bit puts the entire CPU into a reset state. This bit is not self-resetting and)
+{/Helvetica cf} 4 28 0.000 0.700 -832 384 label
+(the housekeeping SPI can be used to determine the true trap state.) {CR}
+(can be configured to be read from a GPIO pin, but as the GPIO state is potentially unknowable,)
+{CR}
+(If the CPU has stopped after encountering an error, it will raise the trap signal. The trap signal)
+{/Helvetica cf} 6 28 0.000 0.700 -832 272 label
+(CPU IRQ) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 544 label
+(zero before it can trigger another interrupt.) {CR}
+(resetting, so while the rising edge will trigger an interrupt, the signal must be manually set to)
+{CR}
+(This is a dedicated manual interrupt driving the CPU IRQ channel 6. The bit is not self-)
+{/Helvetica cf} 6 16 0.000 0.700 -832 448 label
+(PLL bypass) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 688 label
+(CMOS clock\).) {CR}
+(the external CMOS clock \(pin C9\). The default value is 0x1 \(CPU clock source is the external)
+{CR}
+(When enabled, the PLL bypass switches the clock source of the CPU from the PLL output to)
+{/Helvetica cf} 6 28 0.000 0.700 -832 672 label
+(register address 0x09 bit 0) {/Helvetica cf} 2 16 0.000 0.700 -560 696 label
+(register address 0x0A bit 0) {/Helvetica cf} 2 16 0.000 0.700 -560 552 label
+(register address 0x0B bit 0) {/Helvetica cf} 2 16 0.000 0.700 -560 408 label
+(register address 0x0C bit 0) {/Helvetica cf} 2 16 0.000 0.700 -560 296 label
+(page 10) {/Helvetica cf} 2 31 0.000 0.700 336 1240 label
+(PLL DCO enable) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 832 label
+(PLL enable) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 976 label
+(PLL trim) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 152 label
+(MHz.) {hS} (MHz while the slowest output frequency is approximately 90) {hS}
+(is approximately 215) {CR} (ns\). The fastest output frequency) {hS}
+(ps delay \(on top of a fixed delay of 4.67) {hS} (\(approximately\) 250) {CR}
+(Note that this is a thermometer-code trim, where each bit provides an additional)
+{CR}
+(\(trim value 0x3ffffff\) to the fastest \(trim value 0x0\). Default value is 0x3ffefff \(slow trim, -1\).)
+{CR}
+(The 26-bit trim value can adjust the DCO frequency over a factor of about two from the slowest)
+{/Helvetica cf} 18 28 0.000 0.700 -832 120 label
+(register address 0x08 bit 1) {/Helvetica cf} 2 16 0.000 0.700 -560 832 label
+(register address 0x08 bit 0) {/Helvetica cf} 2 16 0.000 0.700 -560 976 label
+(register addresses 0x0D \(all bits\) to 0x10 \(lower 2 bits\))
+{/Helvetica cf} 2 16 0.000 0.700 -560 152 label
+(with a unique number given to each user project.) {CR}
+(The 4-byte \(32 bit\) user project ID is metal-mask programmed on each project before tapeout,)
+{/Helvetica cf} 4 28 0.000 0.700 -832 1072 label
+(register addresses 0x04 to 0x07) {/Helvetica cf} 2 16 0.000 0.700 -560 1088
+label
+(user project ID) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 1088 label
+(PLL output divider \(2\)) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 -256
+label
+(register address 0x11 bit 5\2613) {/Helvetica cf} 2 16 0.000 0.700 -560 -256
+label
+(drive the CPU clock.) {CR}
+(applied prior to turning off the PLL bypass to allow the PLL time to stabilize before using it to)
+{CR}
+(This bit enables the digital frequency-locked-loop clock multiplier. The enable should be)
+{/Helvetica cf} 6 28 0.000 0.700 -832 960 label
+(between approximately 90 to 200 MHz by setting the trim bits \(see below\).)
+{CR}
+(and the system operates in free-running mode, driven by the ring oscillator which can be tuned)
+{CR}
+(The PLL can be run in DCO mode, in which the feedback loop to the driving clock is removed,)
+{/Helvetica cf} 6 28 0.000 0.700 -832 816 label
+(PLL output divider) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 -64 label
+(register address 0x11 bits 2\2610) {/Helvetica cf} 2 16 0.000 0.700 -560 -64
+label
+(operate at these frequencies\). ) {CR}
+(undivided PLL clock directly to the core \(and should not be used, as the processor does not)
+{CR}
+(This 3-bit divider can generate a clock divided by 2 to 7. Values 0 and 1 both pass the)
+{CR}
+(The PLL output can be divided down by an integer divider to provide the core clock frequency.)
+{/Helvetica cf} 8 28 0.000 0.700 -832 -96 label
+
+(undivided PLL clock, while values 2 to 7 pass the clock divided by 2 to 7, respectively.)
+{CR}
+(and provided to the user project space as a secondary clock. Values 0 and 1 both pass the)
+{CR}
+(The PLL 90-degree phase output is passed through an independent 3-bit integer clock divider)
+{/Helvetica cf} 6 28 0.000 0.700 -832 -272 label
+pgsave restore showpage
+
+%%Page: hkspi4 11
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1080 808 translate
+
+0.898 0.898 0.898 scb
+496 1.000 -768 -608 -768 -512 -368 -512 -368 -608 4 polygon
+496 1.000 -768 416 -768 496 -288 496 -288 416 4 polygon
+496 1.000 -768 -512 -768 -416 -528 -416 -528 -512 4 polygon
+496 1.000 -768 64 -768 160 -64 160 -64 64 4 polygon
+0.679 1.000 0.184 scb
+512 1.000 -896 1120 -896 -624 368 -624 368 1120 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1088 label
+1 1.000 -896 1072 368 1072 2 polygon
+(\(continued\)) {/Helvetica-Oblique cf} (Housekeeping SPI registers )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1024 label
+0.898 0.898 0.898 scb
+496 1.000 -768 -320 -768 64 64 64 64 -320 4 polygon
+sce
+1 1.000 -896 496 368 496 2 polygon
+(msb) {/Helvetica-Oblique cf} 2 17 0.000 0.700 -720 640 label
+(lsb) {/Helvetica-Oblique cf} 2 17 0.000 0.700 112 640 label
+(manufacturer_ID[7:0] \(= 0x56\)) {/Helvetica cf} 2 21 0.000 0.700 -288 384
+label
+1 1.000 -896 336 368 336 2 polygon
+1 1.000 -896 624 -896 -608 2 polygon
+(Address) {CR} (Register) {/Helvetica-Oblique cf} 4 17 0.000 0.700 -832 608
+label
+1 1.000 -896 592 368 592 2 polygon
+1 1.000 -896 256 368 256 2 polygon
+(product_ID \(= 0x10\)) {/Helvetica cf} 2 21 0.000 0.700 -272 304 label
+(0x00) {/Helvetica cf} 2 17 0.000 0.700 -832 528 label
+(0x01) {/Helvetica cf} 2 17 0.000 0.700 -832 448 label
+1 1.000 -896 -32 368 -32 2 polygon
+1 1.000 -656 624 -656 592 2 polygon
+1 1.000 -528 624 -528 592 2 polygon
+1 1.000 -400 624 -400 592 2 polygon
+1 1.000 -288 624 -288 592 2 polygon
+1 1.000 -176 624 -176 592 2 polygon
+1 1.000 -64 624 -64 592 2 polygon
+1 1.000 64 624 64 592 2 polygon
+1 1.000 176 624 176 -608 2 polygon
+(7) {/Helvetica cf} 2 16 0.000 0.700 -720 608 label
+(6) {/Helvetica cf} 2 16 0.000 0.700 -608 608 label
+(5) {/Helvetica cf} 2 16 0.000 0.700 -480 608 label
+(4) {/Helvetica cf} 2 16 0.000 0.700 -352 608 label
+(3) {/Helvetica cf} 2 16 0.000 0.700 -240 608 label
+(2) {/Helvetica cf} 2 16 0.000 0.700 -128 608 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -16 608 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 112 608 label
+(comments) {/Helvetica-Oblique cf} 2 17 0.000 0.700 256 608 label
+1 1.000 -896 -128 368 -128 2 polygon
+1 1.000 -896 -224 368 -224 2 polygon
+1 1.000 -896 64 368 64 2 polygon
+1 1.000 -896 160 368 160 2 polygon
+1 1.000 -896 416 368 416 2 polygon
+(0x02) {/Helvetica cf} 2 17 0.000 0.700 -832 368 label
+1 1.000 -288 496 -288 416 2 polygon
+(manufacturer_ID[11:8] \(= 0x4\)) {/Helvetica cf} 2 21 0.000 0.700 -64 464
+label
+(0x03) {/Helvetica cf} 2 17 0.000 0.700 -832 288 label
+(0x08) {/Helvetica cf} 2 17 0.000 0.700 -832 96 label
+(0x09) {/Helvetica cf} 2 17 0.000 0.700 -832 0 label
+(0x0A) {/Helvetica cf} 2 17 0.000 0.700 -832 -96 label
+(0x0B) {/Helvetica cf} 2 17 0.000 0.700 -832 -192 label
+(0x0C) {/Helvetica cf} 2 17 0.000 0.700 -832 -288 label
+(0x12) {/Helvetica cf} 2 17 0.000 0.700 -832 -576 label
+(SPI status and control) {/Helvetica cf} 2 21 0.000 0.700 -272 544 label
+(read-only) {/Helvetica cf} 2 21 0.000 0.700 272 464 label
+(read-only) {/Helvetica cf} 2 21 0.000 0.700 272 384 label
+(read-only) {/Helvetica cf} 2 21 0.000 0.700 272 304 label
+(undefined) {CR} (unused/) {/Helvetica cf} 4 1045 0.000 0.700 256 544 label
+1 1.000 -768 624 -768 -608 2 polygon
+(read-only) {/Helvetica cf} 2 21 0.000 0.700 272 -272 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -368 -272 label
+1 1.000 64 160 64 64 2 polygon
+1 1.000 -64 160 -64 64 2 polygon
+(enable) {CR} (DCO) {CR} (PLL) {/Helvetica cf} 6 1045 0.000 0.700 0 112 label
+(default 0x02) {/Helvetica cf} 2 21 0.000 0.700 272 112 label
+1 1.000 64 64 64 -32 2 polygon
+(bypass) {CR} (PLL) {/Helvetica cf} 4 1045 0.000 0.700 120 16 label
+(default 0x01) {/Helvetica cf} 2 21 0.000 0.700 272 16 label
+1 1.000 64 -32 64 -128 2 polygon
+1 1.000 64 -128 64 -224 2 polygon
+1 1.000 64 -224 64 -320 2 polygon
+(IRQ) {CR} (CPU) {/Helvetica cf} 4 1045 0.000 0.700 112 -80 label
+(reset) {CR} (CPU) {/Helvetica cf} 4 1045 0.000 0.700 112 -176 label
+(trap) {CR} (CPU) {/Helvetica cf} 4 1045 0.000 0.700 112 -272 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -368 -176 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -368 -80 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -368 16 label
+(default 0x00) {/Helvetica cf} 2 21 0.000 0.700 272 -80 label
+(default 0x00) {/Helvetica cf} 2 21 0.000 0.700 272 -176 label
+(Table 9) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -608 672 label
+(Housekeeping SPI register map) {/Helvetica-Bold cf} 2 16 0.000 0.700 -448 672
+label
+1 1.000 -896 -320 368 -320 2 polygon
+1 1.000 -896 -416 368 -416 2 polygon
+1 1.000 -896 -608 368 -608 2 polygon
+(0x10) {CR} (0x0D\261) {/Helvetica cf} 4 21 0.000 0.700 -832 -368 label
+(0x11) {/Helvetica cf} 2 17 0.000 0.700 -832 -480 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -456 112 label
+(enable) {CR} (PLL) {/Helvetica cf} 4 1045 0.000 0.700 120 112 label
+1 1.000 -528 -416 -528 -512 2 polygon
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -656 -464 label
+(default 0x12) {/Helvetica cf} 2 21 0.000 0.700 272 -464 label
+(0x3ffefff) {CR} (default) {/Helvetica cf} 4 1045 0.000 0.700 272 -368 label
+1 1.000 368 624 368 -608 2 polygon
+(page 11) {/Helvetica cf} 2 31 0.000 0.700 352 1112 label
+(PLL feedback divider) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 960 label
+(register address 0x12 bits 4\2610) {/Helvetica cf} 2 16 0.000 0.700 -560 960
+label
+(MHz. ) {hS}
+(implies that the external clock should be no slower than around 4 to 5) {CR}
+(be set to 19 \(19 * 8 = 152\). The DCO range and the number of bits of the feedback divider)
+{CR} (MHz external clock, the divider should) {hS}
+(MHz\). For example, when using an 8) {hS} (approximately 150) {CR}
+(divider value falls between 90 and 214 MHz \(preferably centered on this range, or)
+{CR}
+(feedback divider must be set such that the external clock rate multiplied by the feedback)
+{CR}
+(divided by the feedback divider value \(when running in PLL mode, not DCO mode\). The)
+{CR}
+(The PLL operates by comparing the input clock \(pin C9\) rate to the rate of the PLL clock)
+{/Helvetica cf} 20 28 0.000 0.700 -832 944 label
+1 1.000 -896 -512 368 -512 2 polygon
+(0x07) {CR} (0x04\261) {/Helvetica cf} 4 21 0.000 0.700 -832 208 label
+(unused) {/Helvetica cf} 2 17 0.000 0.700 -544 448 label
+(user_project_ID \(unique value per project\)) {/Helvetica cf} 2 21 0.000 0.700
+-304 208 label
+(read-only) {/Helvetica cf} 2 21 0.000 0.700 272 208 label
+(unused) {/Helvetica cf} 2 21 0.000 0.700 -528 -560 label
+1 1.000 -368 -512 -368 -608 2 polygon
+1 1.000 -176 -416 -176 -512 2 polygon
+(default 0x04) {/Helvetica cf} 2 21 0.000 0.700 272 -560 label
+(PLL feedback divider) {/Helvetica cf} 2 21 0.000 0.700 -96 -560 label
+(PLL output divider) {/Helvetica cf} 2 21 0.000 0.700 0 -464 label
+(PLL output divider 2) {/Helvetica cf} 2 21 0.000 0.700 -352 -464 label
+(DCO trim \(26 bits\) \(= 0x3ffefff\)) {/Helvetica cf} 2 21 0.000 0.700 -288
+-368 label
+pgsave restore showpage
+
+%%Page: spimemio 12
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1184 1408 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -992 512 -992 -1216 256 -1216 256 512 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -992 480 label
+1 1.000 -992 464 256 464 2 polygon
+(QSPI Flash interface) {/Helvetica-Bold cf} 2 16 0.000 0.700 -992 416 label
+(flash io0\2611 \(pins D10 to D9\), flash csb \(pin C10\), and) {/Helvetica cf}
+2 16 0.000 0.700 -416 416 label
+(flash clk \(pin D8\)) {/Helvetica cf} 2 16 0.000 0.700 -416 384 label
+(S25FL256L.) {CR} (Cypress) {/Helvetica cf} (e.g., ) {/Helvetica-Oblique cf}
+("flash io1" acting as SDO \(data from CPU to flash\). Protocol is according to, )
+{CR}
+(sequence in single-bit mode with pin "flash io0" acting as SDI \(data from flash to CPU\) and pin)
+{CR}
+(The QSPI flash controller is automatically enabled on power-up, and will immediately initiate a read)
+{/Helvetica cf} 12 28 0.000 0.700 -992 352 label
+0 1.000 -944 -336 -944 -288 80 -288 80 -336 4 polygon
+1 1.000 -912 -336 -912 -384 2 polygon
+1 1.000 -880 -336 -880 -384 2 polygon
+1 1.000 -848 -336 -848 -384 2 polygon
+1 1.000 -816 -336 -816 -384 2 polygon
+1 1.000 -784 -336 -784 -384 2 polygon
+1 1.000 -752 -336 -752 -384 2 polygon
+1 1.000 -720 -336 -720 -384 2 polygon
+1 1.000 -688 -336 -688 -384 2 polygon
+1 1.000 -656 -336 -656 -384 2 polygon
+1 1.000 -624 -336 -624 -384 2 polygon
+1 1.000 -592 -336 -592 -384 2 polygon
+1 1.000 -560 -336 -560 -384 2 polygon
+1 1.000 -528 -336 -528 -384 2 polygon
+1 1.000 -496 -336 -496 -384 2 polygon
+1 1.000 -464 -336 -464 -384 2 polygon
+1 1.000 -400 -336 -400 -384 2 polygon
+1 1.000 -368 -336 -368 -384 2 polygon
+1 1.000 -336 -336 -336 -384 2 polygon
+1 1.000 -304 -336 -304 -384 2 polygon
+1 1.000 -272 -336 -272 -384 2 polygon
+1 1.000 -240 -336 -240 -384 2 polygon
+1 1.000 -208 -336 -208 -384 2 polygon
+1 1.000 -176 -336 -176 -384 2 polygon
+1 1.000 -144 -336 -144 -384 2 polygon
+1 1.000 -112 -336 -112 -384 2 polygon
+1 1.000 -80 -336 -80 -384 2 polygon
+1 1.000 -48 -336 -48 -384 2 polygon
+1 1.000 -16 -336 -16 -384 2 polygon
+1 1.000 16 -336 16 -384 2 polygon
+1 1.000 48 -336 48 -384 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 64 -360 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 32 -360 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 0 -360 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 -32 -360 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 -64 -360 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 -96 -360 label
+0.600 0.600 0.600 scb
+(6) {/Helvetica cf} 2 21 0.000 0.500 -128 -360 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 -160 -360 label
+sce
+(8) {/Helvetica cf} 2 21 0.000 0.500 -192 -360 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -224 -360 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -256 -360 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -288 -360 label
+0.600 0.600 0.600 scb
+(12) {/Helvetica cf} 2 21 0.000 0.500 -320 -360 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -352 -360 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -384 -360 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -416 -360 label
+sce
+(16) {/Helvetica cf} 2 21 0.000 0.500 -448 -360 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -480 -360 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -512 -360 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -544 -360 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -576 -360 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -608 -360 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -640 -360 label
+0.600 0.600 0.600 scb
+(23) {/Helvetica cf} 2 21 0.000 0.500 -672 -360 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -704 -360 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -736 -360 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -768 -360 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -800 -360 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -832 -360 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -864 -360 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -896 -360 label
+sce
+(31) {/Helvetica cf} 2 21 0.000 0.500 -928 -360 label
+(bit) {/Helvetica cf} 2 20 0.000 0.700 112 -352 label
+(0x2d000000) {/Courier-Bold cf} 2 16 0.000 0.700 -128 -272 label
+1 1.000 -176 -288 -176 -240 2 polygon
+1 1.000 -688 -288 -688 -240 2 polygon
+1 1.000 -944 -240 -944 -288 2 polygon
+1 1.000 80 -240 80 -288 2 polygon
+1 1.000 80 -336 80 -384 2 polygon
+1 1.000 -944 -336 -944 -384 2 polygon
+(0x2d000001) {/Courier-Bold cf} 2 16 360.000 0.700 -384 -272 label
+(0x2d000002) {/Courier-Bold cf} 2 16 360.000 0.700 -640 -272 label
+(0x2d000003) {/Courier-Bold cf} 2 16 0.000 0.700 -896 -272 label
+(address) {/Helvetica cf} 2 17 0.000 0.700 160 -272 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 112 -304 label
+1 1.000 -944 -240 80 -240 2 polygon
+1 1.000 -944 -384 80 -384 2 polygon
+(reg_spictrl) {/Courier-Bold cf} 2 16 0.000 0.700 -528 -224 label
+1 1.000 -432 -240 -432 -288 2 polygon
+1 1.000 -432 -336 -432 -384 2 polygon
+(\(see below\)) {/Helvetica cf} 2 17 0.000 0.700 -528 -320 label
+(mask bit) {/Helvetica cf} 2 16 0.000 0.700 -896 -432 label
+(description) {/Helvetica cf} 2 16 0.000 0.700 -400 -432 label
+1 1.000 -912 -448 96 -448 2 polygon
+(31) {/Helvetica cf} 2 16 0.000 0.700 -896 -480 label
+1 1.000 -912 -336 -912 -288 2 polygon
+1 1.000 -656 -336 -656 -288 2 polygon
+(\(unused\)) {/Helvetica cf} 2 17 0.000 0.700 -784 -320 label
+1 1.000 -432 -288 -432 -336 2 polygon
+1 1.000 -304 -288 -304 -336 2 polygon
+(\(unused\)) {/Helvetica cf} 2 17 0.000 0.700 -368 -320 label
+1 1.000 -176 -288 -176 -336 2 polygon
+1 1.000 -112 -288 -112 -336 2 polygon
+(22\26120) {/Helvetica cf} 2 16 0.000 0.700 -896 -512 label
+(19\26116) {/Helvetica cf} 2 16 0.000 0.700 -896 -544 label
+(11\2618) {/Helvetica cf} 2 16 0.000 0.700 -896 -576 label
+(5) {/Helvetica cf} 2 16 0.000 0.700 -896 -608 label
+(4) {/Helvetica cf} 2 16 0.000 0.700 -896 -640 label
+(3\2610) {/Helvetica cf} 2 16 0.000 0.700 -896 -672 label
+(default) {/Helvetica cf} 2 16 0.000 0.700 -704 -432 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -688 -480 label
+(QSPI flash interface enable) {/Helvetica cf} 2 16 0.000 0.700 -400 -480 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -688 -512 label
+(Access mode \(see table below\)) {/Helvetica cf} 2 16 0.000 0.700 -400 -512
+label
+(8) {/Helvetica cf} 2 16 0.000 0.700 -688 -544 label
+(Dummy clock cycle count) {/Helvetica cf} 2 16 0.000 0.700 -400 -544 label
+(Bit-bang OE FLASH_IO3\261FLASH_IO0) {/Helvetica cf} 2 16 0.000 0.700 -400 -576
+label
+(Bit-bang FLASH_CSB) {/Helvetica cf} 2 16 0.000 0.700 -400 -608 label
+(Bit-bang FLASH_CLK) {/Helvetica cf} 2 16 0.000 0.700 -400 -640 label
+(Bit-bang value FLASH_IO3\261FLASH_IO0) {/Helvetica cf} 2 16 0.000 0.700 -400
+-672 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -688 -576 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -688 -608 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -688 -640 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -688 -672 label
+(0xFF) {/Courier-Bold cf} 2 16 0.000 0.700 -928 128 label
+(0xAB) {/Courier-Bold cf} 2 16 0.000 0.700 -928 96 label
+(Mode bit reset) {/Helvetica cf} 2 16 0.000 0.700 -800 128 label
+(Release from deep power-down) {/Helvetica cf} 2 16 0.000 0.700 -800 96 label
+(0x03) {/Courier-Bold cf} 2 16 0.000 0.700 -928 64 label
+(Read w/3 byte address) {/Helvetica cf} 2 16 0.000 0.700 -800 64 label
+(0x00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 32 label
+(0x00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 0 label
+(0x00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 -32 label
+(\) \(3 bytes\) \(upper byte is ignored\)) {/Helvetica cf} (0x10000000)
+{/Courier-Bold cf} (Program start address \() {/Helvetica cf} 6 16 0.000 0.700
+-800 32 label
+(The initial SPI instruction sequence is as follows:) {/Helvetica cf} 2 16
+0.000 0.700 -992 176 label
+(read command to read from a new address.) {CR}
+(The QSPI flash continues to read bytes, either sequentially on the same command, or issuing a new)
+{/Helvetica cf} 4 28 0.000 0.700 -992 -64 label
+
+(The behavior of the QSPI flash controller can be modified by changing values in the register below:)
+{/Helvetica cf} 2 16 0.000 0.700 -992 -160 label
+(Access mode bit selection \(bits 22\26120\):) {/Helvetica cf} 2 16 0.000 0.700
+-976 -720 label
+(0) {/Helvetica cf} 2 16 0.000 0.700 -976 -768 label
+(1) {/Helvetica cf} 2 16 0.000 0.700 -976 -800 label
+(000) {/Courier-Bold cf} 2 16 0.000 0.700 -912 -768 label
+(001) {/Courier-Bold cf} 2 16 0.000 0.700 -912 -800 label
+(Single bit per clock) {/Helvetica cf} 2 16 0.000 0.700 -784 -768 label
+(Single bit per clock \(same as 0\)) {/Helvetica cf} 2 16 0.000 0.700 -784 -800
+label
+1 1.000 -976 -736 -64 -736 2 polygon
+
+(entire routine to access the SPI flash must be read into SRAM and executed from the SRAM.)
+{CR}
+(The SPI flash can be accessed by bit banging when the enable is off. To do this from the CPU, the)
+{/Helvetica cf} 4 16 0.000 0.700 -992 -976 label
+(Table 10) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -944 -224 label
+(page 12) {/Helvetica cf} 2 31 0.000 0.700 240 496 label
+(\(see below\)) {/Helvetica cf} 2 17 0.000 0.700 -16 -320 label
+(has pins for data lines 0 and 1.) {CR}
+(All additional modes \(QSPI dual and quad modes\) cannot be used, as the management SoC only)
+{/Helvetica cf} 4 28 0.000 0.700 -992 -832 label
+(Interrupt) {/Helvetica-Bold cf} 2 16 0.000 0.700 -992 -1120 label
+(IRQ \(pin E5\)) {/Helvetica cf} 2 16 0.000 0.700 -480 -1120 label
+(The interrupt pin triggers the CPU interrupt channel 5.) {/Helvetica cf} 2 28
+0.000 0.700 -928 -1152 label
+pgsave restore showpage
+
+%%Page: uart 13
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 992 736 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -800 1184 -800 -544 448 -544 448 1184 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -800 1152 label
+1 1.000 -800 1136 448 1136 2 polygon
+(External clock) {/Helvetica-Bold cf} 2 16 0.000 0.700 -800 1088 label
+(UART) {/Helvetica-Bold cf} 2 16 0.000 0.700 -800 864 label
+(ser tx \(pin F7\) and ser rx \(pin E7\)) {/Helvetica cf} 2 16 0.000 0.700 -288
+864 label
+(clock \(pin C9\)) {/Helvetica cf} 2 16 0.000 0.700 -288 1088 label
+
+(blocking operations which will generate CPU wait states until the data transfer is completed.)
+{CR}
+(at a fixed baud rate. Although the UART operates independently of the CPU, data transfers are)
+{CR}
+(The UART is a standard 2-pin serial interface that can communicate with most similar interfaces)
+{/Helvetica cf} 6 28 0.000 0.700 -800 832 label
+0 1.000 -752 512 -752 560 272 560 272 512 4 polygon
+1 1.000 -720 512 -720 464 2 polygon
+1 1.000 -688 512 -688 464 2 polygon
+1 1.000 -656 512 -656 464 2 polygon
+1 1.000 -624 512 -624 464 2 polygon
+1 1.000 -592 512 -592 464 2 polygon
+1 1.000 -560 512 -560 464 2 polygon
+1 1.000 -528 512 -528 464 2 polygon
+1 1.000 -496 512 -496 464 2 polygon
+1 1.000 -464 512 -464 464 2 polygon
+1 1.000 -432 512 -432 464 2 polygon
+1 1.000 -400 512 -400 464 2 polygon
+1 1.000 -368 512 -368 464 2 polygon
+1 1.000 -336 512 -336 464 2 polygon
+1 1.000 -304 512 -304 464 2 polygon
+1 1.000 -272 512 -272 464 2 polygon
+1 1.000 -208 512 -208 464 2 polygon
+1 1.000 -176 512 -176 464 2 polygon
+1 1.000 -144 512 -144 464 2 polygon
+1 1.000 -112 512 -112 464 2 polygon
+1 1.000 -80 512 -80 464 2 polygon
+1 1.000 -48 512 -48 464 2 polygon
+1 1.000 -16 512 -16 464 2 polygon
+1 1.000 16 512 16 464 2 polygon
+1 1.000 48 512 48 464 2 polygon
+1 1.000 80 512 80 464 2 polygon
+1 1.000 112 512 112 464 2 polygon
+1 1.000 144 512 144 464 2 polygon
+1 1.000 176 512 176 464 2 polygon
+1 1.000 208 512 208 464 2 polygon
+1 1.000 240 512 240 464 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 488 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 488 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 488 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 488 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 488 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 488 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 488 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 488 label
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 488 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 488 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 488 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 488 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 488 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 488 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 488 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 488 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 488 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 488 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 488 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 488 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 488 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 488 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 488 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 488 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 488 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 488 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 488 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 488 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 488 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 488 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 488 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 488 label
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 496 label
+(0x20000000) {/Courier-Bold cf} 2 16 0.000 0.700 64 576 label
+1 1.000 16 560 16 608 2 polygon
+1 1.000 -496 560 -496 608 2 polygon
+1 1.000 -752 608 -752 560 2 polygon
+1 1.000 272 608 272 560 2 polygon
+1 1.000 272 512 272 464 2 polygon
+1 1.000 -752 512 -752 464 2 polygon
+(0x20000001) {/Courier-Bold cf} 2 16 360.000 0.700 -192 576 label
+(0x20000002) {/Courier-Bold cf} 2 16 360.000 0.700 -448 576 label
+(0x20000003) {/Courier-Bold cf} 2 16 0.000 0.700 -704 576 label
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 576 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 544 label
+1 1.000 -752 608 272 608 2 polygon
+1 1.000 -752 464 272 464 2 polygon
+(reg_uart_clkdiv) {/Courier-Bold cf} 2 16 0.000 0.700 -336 624 label
+1 1.000 -240 608 -240 560 2 polygon
+1 1.000 -240 512 -240 464 2 polygon
+
+(The behavior of the UART can be modified by changing values in the registers below:)
+{/Helvetica cf} 2 16 0.000 0.700 -800 688 label
+(Table 11) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 624 label
+0 1.000 -752 96 -752 144 272 144 272 96 4 polygon
+1 1.000 -720 96 -720 48 2 polygon
+1 1.000 -688 96 -688 48 2 polygon
+1 1.000 -656 96 -656 48 2 polygon
+1 1.000 -624 96 -624 48 2 polygon
+1 1.000 -592 96 -592 48 2 polygon
+1 1.000 -560 96 -560 48 2 polygon
+1 1.000 -528 96 -528 48 2 polygon
+1 1.000 -496 96 -496 48 2 polygon
+1 1.000 -464 96 -464 48 2 polygon
+1 1.000 -432 96 -432 48 2 polygon
+1 1.000 -400 96 -400 48 2 polygon
+1 1.000 -368 96 -368 48 2 polygon
+1 1.000 -336 96 -336 48 2 polygon
+1 1.000 -304 96 -304 48 2 polygon
+1 1.000 -272 96 -272 48 2 polygon
+1 1.000 -208 96 -208 48 2 polygon
+1 1.000 -176 96 -176 48 2 polygon
+1 1.000 -144 96 -144 48 2 polygon
+1 1.000 -112 96 -112 48 2 polygon
+1 1.000 -80 96 -80 48 2 polygon
+1 1.000 -48 96 -48 48 2 polygon
+1 1.000 -16 96 -16 48 2 polygon
+1 1.000 16 96 16 48 2 polygon
+1 1.000 48 96 48 48 2 polygon
+1 1.000 80 96 80 48 2 polygon
+1 1.000 112 96 112 48 2 polygon
+1 1.000 144 96 144 48 2 polygon
+1 1.000 176 96 176 48 2 polygon
+1 1.000 208 96 208 48 2 polygon
+1 1.000 240 96 240 48 2 polygon
+(0) {/Helvetica cf} 2 21 0.000 0.500 256 72 label
+(1) {/Helvetica cf} 2 21 0.000 0.500 224 72 label
+(2) {/Helvetica cf} 2 21 0.000 0.500 192 72 label
+(3) {/Helvetica cf} 2 21 0.000 0.500 160 72 label
+(4) {/Helvetica cf} 2 21 0.000 0.500 128 72 label
+(5) {/Helvetica cf} 2 21 0.000 0.500 96 72 label
+(6) {/Helvetica cf} 2 21 0.000 0.500 64 72 label
+(7) {/Helvetica cf} 2 21 0.000 0.500 32 72 label
+0.600 0.600 0.600 scb
+(8) {/Helvetica cf} 2 21 0.000 0.500 0 72 label
+(9) {/Helvetica cf} 2 21 0.000 0.500 -32 72 label
+(10) {/Helvetica cf} 2 21 0.000 0.500 -64 72 label
+(11) {/Helvetica cf} 2 21 0.000 0.500 -96 72 label
+(12) {/Helvetica cf} 2 21 0.000 0.500 -128 72 label
+(13) {/Helvetica cf} 2 21 0.000 0.500 -160 72 label
+(14) {/Helvetica cf} 2 21 0.000 0.500 -192 72 label
+(15) {/Helvetica cf} 2 21 0.000 0.500 -224 72 label
+(16) {/Helvetica cf} 2 21 0.000 0.500 -256 72 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -288 72 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -320 72 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -352 72 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -384 72 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -416 72 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -448 72 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -480 72 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -512 72 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -544 72 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -576 72 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -608 72 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -640 72 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -672 72 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -704 72 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -736 72 label
+sce
+(bit) {/Helvetica cf} 2 20 0.000 0.700 304 80 label
+(0x20000004) {/Courier-Bold cf} 2 16 0.000 0.700 64 160 label
+1 1.000 16 144 16 192 2 polygon
+1 1.000 -496 144 -496 192 2 polygon
+1 1.000 -752 192 -752 144 2 polygon
+1 1.000 272 192 272 144 2 polygon
+1 1.000 272 96 272 48 2 polygon
+1 1.000 -752 96 -752 48 2 polygon
+0.600 0.600 0.600 scb
+(0x20000005) {/Courier-Bold cf} 2 16 360.000 0.700 -192 160 label
+(0x20000006) {/Courier-Bold cf} 2 16 360.000 0.700 -448 160 label
+(0x20000007) {/Courier-Bold cf} 2 16 0.000 0.700 -704 160 label
+sce
+(address) {/Helvetica cf} 2 17 0.000 0.700 352 160 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 304 128 label
+1 1.000 -752 192 272 192 2 polygon
+1 1.000 -752 48 272 48 2 polygon
+(reg_uart_data) {/Courier-Bold cf} 2 16 0.000 0.700 -336 208 label
+1 1.000 -240 192 -240 144 2 polygon
+1 1.000 -240 96 -240 48 2 polygon
+(\(unused, value is 0x0\)) {/Helvetica cf} 2 17 0.000 0.700 -352 112 label
+1 1.000 16 144 16 96 2 polygon
+(Table 12) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -752 208 label
+(UART clock divider) {/Helvetica cf} 2 17 0.000 0.700 -240 528 label
+(data bit rate \(baud rate\). The default value is 1.) {CR}
+(The entire 32 bit word encodes the number of CPU core cycles to divide down to get the UART)
+{/Helvetica cf} 4 28 0.000 0.700 -752 432 label
+(To get 9600 baud, 100E6 / 9600 = 10417 \(hex value 0x28b1\).) {CR} (MHz.) {qS}
+(MHz, then the core CPU clock runs at 100) {qS}
+(If the external crystal is 12.5) {/Helvetica cf} (Example: )
+{/Helvetica-Oblique cf} 10 28 0.000 0.700 -752 336 label
+
+(buffer for additional reads. Note that there is no FIFO associated with the UART.)
+{CR}
+(the receive buffer, and returns the value of the receive buffer otherwise, and clears the receive)
+{CR}
+(buffer overflow. Reading a value from this register returns 255 \(0xff\) if no valid data byte is in)
+{CR}
+(expensive operation on the CPU, but avoids the necessity of buffering data and checking for)
+{CR}
+(is complete before starting the new write operation. This makes the UART transmit a relatively)
+{CR}
+(UART write operation is pending, then the CPU will be blocked with wait states until the transfer)
+{CR}
+(Writing a value to this register will immediately start a data transfer on the SER_TX pin. If a)
+{/Helvetica cf} 14 28 0.000 0.700 -752 16 label
+(page 13) {/Helvetica cf} 2 31 0.000 0.700 432 1168 label
+(processor is driven by a trimmed free-running ring oscillator.) {CR}
+(clock is multiplied up by the feedback divider value to obtain the core clock. In DCO mode, the)
+{CR}
+(SPI to set the processor into PLL mode or DCO free-running mode. In PLL mode, the external)
+{CR}
+(runs at the same rate as the external clock. The processor program may access the housekeeping)
+{CR}
+(The external clock functions as the source clock for the entire processor. On start-up, the processor)
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+(value) {/Helvetica cf} 2 20 0.000 0.700 304 -336 label
+1 1.000 -752 -272 272 -272 2 polygon
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+(\(unused, value is 0x0\)) {/Helvetica cf} 2 17 0.000 0.700 -352 -352 label
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+(The UART must be enabled to run \(default disabled\)) {/Helvetica cf} 2 16
+0.000 0.700 -752 -464 label
+pgsave restore showpage
+
+%%Page: spi_master 14
+%%PageOrientation: Portrait
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+
+(spi sdi \(pin E9\), spi csb \(pin E8\), spi sck \(pin F8\), and spi sdo \(pin F9\))
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+(The byte at 0x24000004 holds the SPI data \(either read or write\))
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+(Bit 13) {/Helvetica cf} 2 16 0.000 0.700 -688 560 label
+(Bit 12) {/Helvetica cf} 2 16 0.000 0.700 -688 496 label
+(Bit 11) {/Helvetica cf} 2 16 0.000 0.700 -688 432 label
+(Bit 10) {/Helvetica cf} 2 16 0.000 0.700 -688 368 label
+(Bit 9) {/Helvetica cf} 2 16 0.000 0.700 -688 304 label
+(Bit 8) {/Helvetica cf} 2 16 0.000 0.700 -688 240 label
+(Bits 7\2610) {/Helvetica cf} 2 16 0.000 0.700 -688 176 label
+(SPI interrupt enable) {/Helvetica cf} 2 16 0.000 0.700 -544 624 label
+(SPI system enable) {/Helvetica cf} 2 16 0.000 0.700 -544 560 label
+(stream) {/Helvetica cf} 2 16 0.000 0.700 -544 496 label
+(mode) {/Helvetica cf} 2 16 0.000 0.700 -544 432 label
+(invert SCK) {/Helvetica cf} 2 16 0.000 0.700 -544 368 label
+(invert CSB) {/Helvetica cf} 2 16 0.000 0.700 -544 304 label
+(MLB) {/Helvetica cf} 2 16 0.000 0.700 -544 240 label
+(prescaler) {/Helvetica cf} 2 16 0.000 0.700 -544 176 label
+(0 = apply/release CSB separately for each byte) {/Helvetica cf} 2 16 0.000
+0.700 -256 496 label
+(1 = apply CSB until stream bit is cleared \(manually\)) {/Helvetica cf} 2 16
+0.000 0.700 -256 464 label
+(0 = read and change data on opposite SCK edges) {/Helvetica cf} 2 16 0.000
+0.700 -256 432 label
+(1 = read and change data on the same SCK edge) {/Helvetica cf} 2 16 0.000
+0.700 -256 400 label
+(0 = normal SCK) {/Helvetica cf} 2 16 0.000 0.700 -256 368 label
+(1= inverted SCK) {/Helvetica cf} 2 16 0.000 0.700 -256 336 label
+(0 = normal CSB \(low is active\)) {/Helvetica cf} 2 16 0.000 0.700 -256 304
+label
+(1 = inverted CSB \(high is active\)) {/Helvetica cf} 2 16 0.000 0.700 -256 272
+label
+(count \(in master clock cycles\) of 1/2 SCK cycle) {/Helvetica cf} 2 16 0.000
+0.700 -256 176 label
+(0 = msb first) {/Helvetica cf} 2 16 0.000 0.700 -256 240 label
+(1 = lsb first) {/Helvetica cf} 2 16 0.000 0.700 -256 208 label
+(0 = SPI disabled) {/Helvetica cf} 2 16 0.000 0.700 -256 560 label
+(1 = SPI enabled) {/Helvetica cf} 2 16 0.000 0.700 -256 528 label
+(0 = interrupt disabled) {/Helvetica cf} 2 16 0.000 0.700 -256 624 label
+(1 = interrupt enabled) {/Helvetica cf} 2 16 0.000 0.700 -256 592 label
+(\(default value 2\)) {/Helvetica cf} 2 16 0.000 0.700 -256 144 label
+1 1.000 -688 720 416 720 2 polygon
+(Configuration bit defintions) {/Helvetica cf} 2 16 0.000 0.700 -688 736 label
+(All configuration bits other than the prescaler default to value zero.)
+{/Helvetica cf} 2 16 0.000 0.700 -688 96 label
+(there is no FIFO associated with the SPI master.) {CR}
+(relatively expensive operations that tie up the CPU, but will not lose or overwrite data. Note that)
+{CR}
+(is still in progress. There is no FIFO buffer for data. Therefore SPI reads and writes are)
+{CR}
+(still in progress. Reading from the SPI will also stall the CPU if an incomplete SPI transmission)
+{CR}
+(is similar to the UART. A write operation will stall the CPU if an incomplete SPI transmission is)
+{CR}
+(in the configuration register, and writing values to or reading from reg_spi_data. The protocol)
+{CR}
+(Reading to and writing from the SPI master is simply a matter of setting the required values)
+{/Helvetica cf} 14 28 0.000 0.700 -688 -288 label
+(page 14) {/Helvetica cf} 2 31 0.000 0.700 496 1136 label
+(Bit 15) {/Helvetica cf} 2 16 0.000 0.700 -688 688 label
+(Housekeeping) {/Helvetica cf} 2 16 0.000 0.700 -544 688 label
+(0 = SPI master connected to external pins) {/Helvetica cf} 2 16 0.000 0.700
+-256 688 label
+(1 = SPI master connected directly to housekeeping SPI) {/Helvetica cf} 2 16
+0.000 0.700 -256 656 label
+pgsave restore showpage
+
+%%Page: counter_timer 15
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+(16) {/Helvetica cf} 2 21 0.000 0.500 -288 664 label
+(17) {/Helvetica cf} 2 21 0.000 0.500 -320 664 label
+(18) {/Helvetica cf} 2 21 0.000 0.500 -352 664 label
+(19) {/Helvetica cf} 2 21 0.000 0.500 -384 664 label
+(20) {/Helvetica cf} 2 21 0.000 0.500 -416 664 label
+(21) {/Helvetica cf} 2 21 0.000 0.500 -448 664 label
+(22) {/Helvetica cf} 2 21 0.000 0.500 -480 664 label
+(23) {/Helvetica cf} 2 21 0.000 0.500 -512 664 label
+(24) {/Helvetica cf} 2 21 0.000 0.500 -544 664 label
+(25) {/Helvetica cf} 2 21 0.000 0.500 -576 664 label
+(26) {/Helvetica cf} 2 21 0.000 0.500 -608 664 label
+(27) {/Helvetica cf} 2 21 0.000 0.500 -640 664 label
+(28) {/Helvetica cf} 2 21 0.000 0.500 -672 664 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -704 664 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -736 664 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -768 664 label
+(bit) {/Helvetica cf} 2 20 0.000 0.700 272 672 label
+(0x23000004) {/Courier-Bold cf} 2 16 0.000 0.700 32 752 label
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+1 1.000 240 688 240 640 2 polygon
+1 1.000 -784 688 -784 640 2 polygon
+(address) {/Helvetica cf} 2 17 0.000 0.700 320 752 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 272 720 label
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+1 1.000 -784 640 240 640 2 polygon
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+1 1.000 144 384 144 336 2 polygon
+1 1.000 176 384 176 336 2 polygon
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+(22) {/Helvetica cf} 2 21 0.000 0.500 -480 360 label
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+(28) {/Helvetica cf} 2 21 0.000 0.500 -672 360 label
+(29) {/Helvetica cf} 2 21 0.000 0.500 -704 360 label
+(30) {/Helvetica cf} 2 21 0.000 0.500 -736 360 label
+(31) {/Helvetica cf} 2 21 0.000 0.500 -768 360 label
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+1 1.000 -528 432 -528 480 2 polygon
+1 1.000 -784 480 -784 432 2 polygon
+1 1.000 240 480 240 432 2 polygon
+1 1.000 240 384 240 336 2 polygon
+1 1.000 -784 384 -784 336 2 polygon
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+(0x2300000a) {/Courier-Bold cf} 2 16 0.000 0.700 -480 448 label
+(0x2300000b) {/Courier-Bold cf} 2 16 0.000 0.700 -736 448 label
+(address) {/Helvetica cf} 2 17 0.000 0.700 320 448 label
+(value) {/Helvetica cf} 2 20 0.000 0.700 272 416 label
+1 1.000 -784 480 240 480 2 polygon
+1 1.000 -784 336 240 336 2 polygon
+(reg_timer1_data) {/Courier-Bold cf} 2 16 360.000 0.700 -368 496 label
+1 1.000 -272 480 -272 432 2 polygon
+1 1.000 -272 384 -272 336 2 polygon
+(Table 21) {/Helvetica-Oblique cf} 2 16 360.000 0.700 -784 496 label
+(Timer value) {/Helvetica cf} 2 17 0.000 0.700 -272 704 label
+(0x23000005) {/Courier-Bold cf} 2 16 0.000 0.700 -224 752 label
+(0x23000006) {/Courier-Bold cf} 2 16 0.000 0.700 -480 752 label
+(0x23000007) {/Courier-Bold cf} 2 16 0.000 0.700 -736 752 label
+(Timer data) {/Helvetica cf} 2 17 0.000 0.700 -272 400 label
+(Timer configuration bit definitions) {/Helvetica cf} 2 16 0.000 0.700 -784
+1120 label
+1 1.000 -784 1104 240 1104 2 polygon
+(Bit 3) {/Helvetica cf} 2 16 0.000 0.700 -784 1072 label
+(Bit 2) {/Helvetica cf} 2 16 0.000 0.700 -784 1008 label
+(Bit 1) {/Helvetica cf} 2 16 0.000 0.700 -784 944 label
+(Bit 0) {/Helvetica cf} 2 16 0.000 0.700 -784 880 label
+(Counter/timer enable) {/Helvetica cf} 2 16 0.000 0.700 -672 1072 label
+(1 = counter/timer enabled) {/Helvetica cf} 2 16 0.000 0.700 -288 1072 label
+(0 = counter/timer disabled) {/Helvetica cf} 2 16 0.000 0.700 -288 1040 label
+(Oneshot mode) {/Helvetica cf} 2 16 0.000 0.700 -672 1008 label
+(1 = oneshot mode) {/Helvetica cf} 2 16 0.000 0.700 -288 1008 label
+(0 = continuous mode) {/Helvetica cf} 2 16 0.000 0.700 -288 976 label
+(Updown) {/Helvetica cf} 2 16 0.000 0.700 -672 944 label
+(1 = count up) {/Helvetica cf} 2 16 0.000 0.700 -288 944 label
+(0 = count down) {/Helvetica cf} 2 16 0.000 0.700 -288 912 label
+(Interrupt enable) {/Helvetica cf} 2 16 0.000 0.700 -672 880 label
+(1 = interrupt enabled) {/Helvetica cf} 2 16 0.000 0.700 -288 880 label
+(0 = interrupt disabled) {/Helvetica cf} 2 16 0.000 0.700 -288 848 label
+(register is read-write and can be used to reset the timer.) {CR}
+(The value in this register is the current value of the counter. Value is 32 bits. The)
+{/Helvetica cf} 4 28 0.000 0.700 -784 608 label
+(The value in this register is the reset value for the comparator.)
+{/Helvetica cf} 2 28 0.000 0.700 -784 304 label
+(reg_timer_value register.) {CR}
+(timer in a hold state. When re-enabled, counting resumes. To reset the timer, write zero to the)
+{CR}
+(Note: When the counter/timer is disabled, the reg_timer_value remains unchanged, which puts the)
+{/Helvetica cf} 6 16 0.000 0.700 -832 -144 label
+(If counting down, the count continues until the counter reaches zero.) {CR}
+(the counter is enabled. If counting up, the count continues until the counter reaches reg_timer_data.)
+{CR}
+(When enabled, the counter counts up or down from the value set in reg_timer_value at the time)
+{/Helvetica cf} 6 28 0.000 0.700 -832 240 label
+
+(reaches the value of reg_timer_data \(up count\) or zero \(down count\), and stops.)
+{CR}
+(In one-shot mode, the counter triggers an interrupt \(IRQ channel 11; see next page\) when it)
+{/Helvetica cf} 4 28 0.000 0.700 -832 16 label
+(the counter will generate an interrupt on every cycle.) {CR}
+(reg_timer_data if counting down, and the count continues immediately. If the interrupt is enabled,)
+{CR}
+(In continuous mode, the counter resets to zero if counting up, and resets to the value in)
+{/Helvetica cf} 6 28 0.000 0.700 -832 128 label
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -832 1536 label
+(addresses for the controls, as shown in the tables below.) {CR}
+(The second counter/timer is functionally identical to the first, with different memory mapped)
+{/Helvetica cf} 4 28 0.000 0.700 -832 1472 label
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+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1216 label
+1 1.000 -896 1200 352 1200 2 polygon
+(Interrupts \(IRQ\)) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 1152 label
+(have value zero. ) {CR}
+(uses only a handful, as described in the table below. All IRQ channels not in the list below always)
+{CR}
+(handler to memory location 0. The PicoRV32 defines 32 IRQ channels, of which the Caravel chip)
+{CR}
+(this location when an interrupt is received. To enable interrupts, it is necessary to copy an interrupt)
+{CR}
+(The interrupt vector is set to memory addres 0 \(bottom of SRAM\). The program counter switches to)
+{/Helvetica cf} 10 28 0.000 0.700 -896 1120 label
+(Table 19) {/Helvetica-Oblique cf} 2 16 360.000 0.700 -832 928 label
+(CPU IRQ channel definitions) {/Helvetica cf} 2 16 0.000 0.700 -672 928 label
+(IRQ channel) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -768 864 label
+(description) {/Helvetica-Oblique cf} 2 16 0.000 0.700 -512 864 label
+1 1.000 -768 848 160 848 2 polygon
+(5) {/Helvetica cf} 2 19 0.000 0.700 -640 784 label
+(6) {/Helvetica cf} 2 19 0.000 0.700 -640 752 label
+(7) {/Helvetica cf} 2 19 0.000 0.700 -640 720 label
+
+(The Caravel PicoRV32 implementation does not enable IRQ QREGS \(see PicoRV32 description\).)
+{/Helvetica cf} 2 16 0.000 0.700 -896 448 label
+(description\). All interrupts are masked and must be enabled in software.)
+{CR}
+(The handling of interrupts is beyond the scope of this document \(see RISC-V instruction set)
+{/Helvetica cf} 4 28 0.000 0.700 -896 416 label
+(IRQ external pin \(pin E5\)) {/Helvetica cf} 2 16 0.000 0.700 -512 784 label
+(Housekeeping SPI IRQ) {/Helvetica cf} 2 16 0.000 0.700 -512 752 label
+(Assignable interrupt \(see Table 7\)) {/Helvetica cf} 2 16 0.000 0.700 -512
+720 label
+(4) {/Helvetica cf} 2 19 0.000 0.700 -640 816 label
+(UART data available) {/Helvetica cf} 2 16 0.000 0.700 -512 816 label
+(9) {/Helvetica cf} 2 19 0.000 0.700 -640 688 label
+(SPI master data available, when enabled \(see Table 14\)) {/Helvetica cf} 2 16
+0.000 0.700 -512 688 label
+(10) {/Helvetica cf} 2 19 0.000 0.700 -640 656 label
+(Timer 0 expired, when enabled \(see Table 16\)) {/Helvetica cf} 2 16 0.000
+0.700 -512 656 label
+(page 17) {/Helvetica cf} 2 31 0.000 0.700 336 1232 label
+(11) {/Helvetica cf} 2 19 0.000 0.700 -640 624 label
+(Timer 1 expired, when enabled \(see Table 19\)) {/Helvetica cf} 2 16 0.000
+0.700 -512 624 label
+(Management area SRAM) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 144 label
+
+(at address 0 \(zero\). There are additional blocks of memory above this area, size and location TBD.)
+{CR}
+(The Caravel chip has an on-board memory of 256 words of width 32 bits. The memory is located)
+{/Helvetica cf} 4 28 0.000 0.700 -896 112 label
+(Storage area SRAM) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 -208 label
+(the user area.) {CR}
+(area is connected into the user area 2 power supply, and so is nominally considered to be part of)
+{CR}
+(either the management SoC or the user project, through the wishbone bus interface. The storage)
+{CR}
+(The Caravel chip has a \252storage area\272 SRAM block that is auxiliary space that can be used by)
+{/Helvetica cf} 8 28 0.000 0.700 -896 -240 label
+(configuration of the SRAM block.) {CR}
+(making use of this space, the user should notify efabless of their requirement for the size and)
+{CR}
+(The storage area may be used as an experimentation area for OpenRAM, so for any user project)
+{/Helvetica cf} 6 28 0.000 0.700 -896 -384 label
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+
+0.679 1.000 0.184 scb
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+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1216 label
+1 1.000 -896 1200 352 1200 2 polygon
+(page 18) {/Helvetica cf} 2 31 0.000 0.700 336 1232 label
+(Logic Analyzer) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 1152 label
+(User area wishbone base) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 544 label
+pgsave restore showpage
+
+%%Page: references 19
+%%PageOrientation: Portrait
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+
+0.679 1.000 0.184 scb
+512 1.000 -896 1184 -896 -544 352 -544 352 1184 4 polygon
+sce
+(\(cont.\)) {/Helvetica-Oblique cf} (Functional Description )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -896 1152 label
+1 1.000 -896 1136 352 1136 2 polygon
+(Caravel management SoC simplified block diagram) {/Helvetica-Bold cf} 2 16
+0.000 0.700 -896 1088 label
+0.420 0.000 -366 638 ::raven_block_diagram
+(Programming) {/Helvetica-Bold cf} 2 16 0.000 0.700 -892 208 label
+(Additional references) {/Helvetica-Bold cf} 2 16 0.000 0.700 -896 -448 label
+(file section \252Building a pure RV32I Toolchain.\272) {/Helvetica cf}
+(README.md ) {/Courier-Bold cf} (Specifically, see the top-level ) {CR} {CR}
+(.) {/Helvetica cf} (http://github.com/cliffordwolf/picorv32)
+{/Courier-Bold cf} ( ) {CR} {CR}
+(compiler version is the PicoRV32 source at) {CR}
+( compiler. The best reference for getting the correct cross-) {/Helvetica cf}
+(gcc) {/Helvetica-Bold cf} (The RISC-V architecture has a ) {/Helvetica cf} 22
+28 0.000 0.700 -892 176 label
+(RISC-V gcc toolchain as described above\), see) {CR}
+(For programming examples specifically for the Caravel chip \(assuming a correct installation of a)
+{/Helvetica cf} 4 28 0.000 0.700 -892 -16 label
+1.000 0.000 0.000 scb
+(http://github.com/efabless/caravel) {/Courier-Bold cf} 2 16 0.000 0.700 -844
+-112 label
+sce
+(text.) {CR}
+(that defines the memory-mapped locations as described throughout this)
+{/Helvetica cf} (defs.h ) {/Courier-Bold cf} (the header file ) {CR}
+(contains example source code to program the Ravenna chip along with)
+{/Helvetica cf} (verilog/dv ) {/Courier-Bold cf} (The directory )
+{/Helvetica cf} 14 16 0.000 0.700 -892 -224 label
+(number of test programs that exercise various features of the chip.) {CR}
+(that compiles hex files and runs simulations of a) {/Helvetica cf} (Makefile )
+{/Courier-Bold cf} (directory contains a ) {/Helvetica cf} (verilog/dv )
+{/Courier-Bold cf} (The ) {/Helvetica cf} 12 28 0.000 0.700 -892 -256 label
+(driver software.) {CR}
+(Additional documentation exists on the same site for the provided demonstration circuit board and)
+{/Helvetica cf} 4 28 0.000 0.700 -892 -336 label
+(http://riscv.org/software-status/) {Tf} {CR} (http://riscv.org/)
+{/Courier-Bold cf} {Ts} (See ) {/Helvetica cf} 8 28 0.000 0.700 -896 -480
+label
+(page 19) {/Helvetica cf} 2 31 0.000 0.700 336 1168 label
+pgsave restore showpage
+
+%%Page: memmap1 20
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+
+0.679 1.000 0.184 scb
+512 1.000 -1056 784 -1056 -1232 384 -1232 384 784 4 polygon
+sce
+1 1.000 -1056 736 384 736 2 polygon
+(Memory Mapped I/O summary by address) {/Helvetica-Bold cf} 2 16 0.000 0.700
+-1056 704 label
+1 1.000 -816 672 -816 -1232 2 polygon
+(Address \(bytes\)) {/Helvetica cf} 2 16 360.000 0.700 -1056 656 label
+1 1.000 -1056 640 384 640 2 polygon
+(Function) {/Helvetica cf} 2 16 0.000 0.700 -800 656 label
+(0x00 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 608 label
+(Flash SPI / overlaid SRAM \(4k words\) start of memory block) {/Helvetica cf}
+2 16 0.000 0.700 -800 608 label
+(0x10 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 528 label
+(Flash SPI start of program block) {/Helvetica cf} 2 16 0.000 0.700 -800 528
+label
+(0x21 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 304 label
+(GPIO input/output \(bit 16/bit 0\)) {/Helvetica cf} 2 16 0.000 0.700 -800 304
+label
+(0x21 00 00 04) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 272 label
+(GPIO output enable \(1 = output, 0 = input\)) {/Helvetica cf} 2 16 360.000
+0.700 -800 272 label
+(0x21 00 00 08) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 240 label
+(GPIO pullup enable \(1 = pullup, 0 = none\)) {/Helvetica cf} 2 16 0.000 0.700
+-800 240 label
+(0x21 00 00 0c) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 208 label
+(GPIO pulldown enable \(1 = pulldown, 0 = none\)) {/Helvetica cf} 2 16 360.000
+0.700 -800 208 label
+(Program to run starts here on reset.) {/Helvetica cf} 2 16 0.000 0.700 -144
+528 label
+(1 general-purpose digital, management area only) {/Helvetica cf} 2 16 0.000
+0.700 -240 304 label
+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -1056 784
+label
+(page 20) {/Helvetica cf} 2 31 0.000 0.700 368 768 label
+(0x00 00 3f ff) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 576 label
+(End of SRAM) {/Helvetica cf} 2 16 0.000 0.700 -800 576 label
+(0x1f ff ff ff) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 464 label
+(MB\)) {qS} (Maximum SPI flash addressable space \(32) {/Helvetica cf} 4 16
+0.000 0.700 -800 464 label
+(0x10 ff ff ff) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 496 label
+(MB\) with QSPI 3-byte addressing) {qS}
+(Maximum SPI flash addressable space \(16) {/Helvetica cf} 4 16 0.000 0.700
+-800 496 label
+(UART clock divider select \(system clock freq. / baud rate\)) {/Helvetica cf}
+2 16 0.000 0.700 -800 416 label
+(0x20 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 416 label
+(if receiver buffer is empty\)) {/Helvetica cf} (0xffffffff ) {/Courier cf}
+(UART data \(returns ) {/Helvetica cf} 6 16 360.000 0.700 -800 384 label
+(0x20 00 00 04) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 384 label
+(UART enable) {/Helvetica cf} 2 16 360.000 0.700 -800 352 label
+(0x20 00 00 08) {/Courier-Bold cf} 2 16 0.000 0.700 -1056 352 label
+(0x22 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 160 label
+(Counter/Timer 0 configuration register \(lower 4 bits\)) {/Helvetica cf} 2 16
+0.000 0.700 -800 160 label
+(0x22 00 00 04) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -32 label
+(Counter/Timer 0 current value) {/Helvetica cf} 2 16 0.000 0.700 -800 -32 label
+(0x22 00 00 08) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -112 label
+(Counter/Timer 0 reset value) {/Helvetica cf} 2 16 0.000 0.700 -800 -112 label
+(bit 0 = enable \(0 = hold, 1 = count\)) {/Helvetica cf} 2 16 0.000 0.700 -736
+112 label
+(Set or read the 32-bit current value.) {/Helvetica cf} 2 16 0.000 0.700 -736
+-64 label
+(Set or read the 32-bit reset \(down-count\) or compare \(up-count\) value.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 -144 label
+(bit 1 = oneshot \(0 = continuous count, 1 = one-shot count\)) {/Helvetica cf}
+2 16 0.000 0.700 -736 80 label
+(bit 2 = updown \(0 = count down, 1 = count up\)) {/Helvetica cf} 2 16 0.000
+0.700 -736 48 label
+(bit 3 = irq enable \(0 = disabled, 1 = trigger IRQ channel 10 on timeout\))
+{/Helvetica cf} 2 16 0.000 0.700 -736 16 label
+(0x23 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -192 label
+(Counter/Timer 1 configuration register \(lower 4 bits\)) {/Helvetica cf} 2 16
+0.000 0.700 -800 -192 label
+(0x23 00 00 04) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -384 label
+(Counter/Timer 1 current value) {/Helvetica cf} 2 16 0.000 0.700 -800 -384
+label
+(0x23 00 00 08) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -464 label
+(Counter/Timer 1 reset value) {/Helvetica cf} 2 16 0.000 0.700 -800 -464 label
+(bit 0 = enable \(0 = hold, 1 = count\)) {/Helvetica cf} 2 16 0.000 0.700 -736
+-240 label
+(Set or read the 32-bit current value.) {/Helvetica cf} 2 16 0.000 0.700 -736
+-416 label
+(Set or read the 32-bit reset \(down-count\) or compare \(up-count\) value.)
+{/Helvetica cf} 2 16 0.000 0.700 -752 -496 label
+(bit 1 = oneshot \(0 = continuous count, 1 = one-shot count\)) {/Helvetica cf}
+2 16 0.000 0.700 -736 -272 label
+(bit 2 = updown \(0 = count down, 1 = count up\)) {/Helvetica cf} 2 16 0.000
+0.700 -736 -304 label
+(bit 3 = irq enable \(0 = disabled, 1 = trigger IRQ channel 11 on timeout\))
+{/Helvetica cf} 2 16 0.000 0.700 -736 -336 label
+(0x24 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -544 label
+(SPI master configuration register) {/Helvetica cf} 2 16 0.000 0.700 -800 -544
+label
+(0x24 00 00 04) {/Courier-Bold cf} 2 16 360.000 0.700 -1056 -896 label
+(SPI master data register \(low 8 bits\)) {/Helvetica cf} 2 16 0.000 0.700 -800
+-896 label
+
+(bits 0\2617 = prescaler \(core clock / \(prescaler + 1\) = SPI clock rate / 2\) \(default 2\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -592 label
+(bit 8 = mlb \(0 = msb first, 1 = lsb first\) \(default 0\)) {/Helvetica cf} 2
+16 0.000 0.700 -720 -624 label
+(bit 9 = invcsb \(0 = csb active low, 1 = csb active high\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -656 label
+(bit 10 = invsck \(0 = normal sck, 1 = inverted sck\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -688 label
+
+(bit 11 = mode \(0 = read/write on opposite sck edge, 1 = same edge\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -720 label
+
+(bit 12 = stream \(0 = raise csb after each byte, 1 = keep csb low until stream bit cleared\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -752 label
+(bit 13 = enable \(0 = SPI master disabled, 1 = SPI master enabled\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -784 label
+
+(bit 14 = irq enable \(0 = disabled, 1 = SPI read valid triggers interrupt channel 9\))
+{/Helvetica cf} 2 16 0.000 0.700 -720 -816 label
+(Write data to send to low byte or read received data from low byte.)
+{/Helvetica cf} 2 16 0.000 0.700 -720 -944 label
+(bit 15 = housekeeping \(0 = disconnected, 1 = connected\)) {/Helvetica cf} 2
+16 0.000 0.700 -720 -848 label
+pgsave restore showpage
+
+%%Page: memmap2 21
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+0.679 1.000 0.184 scb
+512 1.000 -928 896 -928 -1120 512 -1120 512 896 4 polygon
+sce
+1 1.000 -688 784 -688 -1120 2 polygon
+(Address \(bytes\)) {/Helvetica cf} 2 16 360.000 0.700 -928 768 label
+(Function) {/Helvetica cf} 2 16 0.000 0.700 -672 768 label
+1 1.000 -928 752 512 752 2 polygon
+(\(continued\)) {/Helvetica-Oblique cf} (Memory Mapped I/O summary by address )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -928 816 label
+1 1.000 -928 848 512 848 2 polygon
+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 896 label
+(page 21) {/Helvetica cf} 2 31 0.000 0.700 496 880 label
+(0x25 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 704 label
+(Logic Analyzer Data 0) {/Helvetica cf} 2 16 0.000 0.700 -672 704 label
+(0x25 00 00 04) {/Courier-Bold cf} 2 16 0.000 0.700 -928 672 label
+(Logic Analyzer Data 1) {/Helvetica cf} 2 16 0.000 0.700 -672 672 label
+(0x25 00 00 08) {/Courier-Bold cf} 2 16 0.000 0.700 -928 640 label
+(Logic Analyzer Data 2) {/Helvetica cf} 2 16 0.000 0.700 -672 640 label
+(0x25 00 00 0c) {/Courier-Bold cf} 2 16 0.000 0.700 -928 608 label
+(Logic Analyzer Data 3) {/Helvetica cf} 2 16 0.000 0.700 -672 608 label
+(0x25 00 00 10) {/Courier-Bold cf} 2 16 0.000 0.700 -928 560 label
+(Logic Analyzer Enable 0) {/Helvetica cf} 2 16 0.000 0.700 -672 560 label
+(0x25 00 00 14) {/Courier-Bold cf} 2 16 0.000 0.700 -928 528 label
+(Logic Analyzer Enable 1) {/Helvetica cf} 2 16 0.000 0.700 -672 528 label
+(0x25 00 00 18) {/Courier-Bold cf} 2 16 0.000 0.700 -928 496 label
+(Logic Analyzer Enable 2) {/Helvetica cf} 2 16 0.000 0.700 -672 496 label
+(0x25 00 00 1c) {/Courier-Bold cf} 2 16 0.000 0.700 -928 464 label
+(Logic Analyzer Enable 3) {/Helvetica cf} 2 16 0.000 0.700 -672 464 label
+(0x26 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 400 label
+(User project area GPIO data \(L\)) {/Helvetica cf} 2 16 0.000 0.700 -672 400
+label
+(0x26 00 00 04) {/Courier-Bold cf} 2 16 0.000 0.700 -928 368 label
+(User project area GPIO data \(H\)) {/Helvetica cf} 2 16 0.000 0.700 -672 368
+label
+(0x26 00 00 08) {/Courier-Bold cf} 2 16 0.000 0.700 -928 336 label
+(User project area GPIO data transfer \(bit 0, auto-zeroing\)) {/Helvetica cf}
+2 16 0.000 0.700 -672 336 label
+(0x26 00 00 0c) {/Courier-Bold cf} 2 16 0.000 0.700 -928 304 label
+(0x26 00 00 a0) {/Courier-Bold cf} 2 16 0.000 0.700 -928 224 label
+(. . .) {/Helvetica cf} 2 21 90.000 0.700 -816 272 label
+(User project area GPIO mprj_io[0] configure) {/Helvetica cf} 2 16 0.000 0.700
+-672 304 label
+(User project area GPIO mprj_io[37] configure) {/Helvetica cf} 2 16 0.000 0.700
+-672 224 label
+(User project area GPIO power[0] configure) {/Helvetica cf} 2 16 0.000 0.700
+-672 -608 label
+(0x26 00 00 a4) {/Courier-Bold cf} 2 16 0.000 0.700 -928 -608 label
+(0x26 00 01 b4) {/Courier-Bold cf} 2 16 0.000 0.700 -928 -640 label
+(User project area GPIO power[3] configure) {/Helvetica cf} 2 16 0.000 0.700
+-672 -640 label
+1 1.000 -112 -592 -96 -608 -96 -624 -112 -640 4 polygon
+(These are currently undefined/unused.) {/Helvetica cf} 2 16 0.000 0.700 -64
+-624 label
+(bits 10\26112 = digital mode \(see below\) \(default 001\)) {/Helvetica cf} 2
+16 0.000 0.700 -608 -176 label
+
+(bit 0 = management control enable \(0 = user control, 1 = management control\) \(default 1\))
+{/Helvetica cf} 2 16 0.000 0.700 -608 144 label
+
+(bit 1 = output disable \(0 = output enabled, 1 = output disabled\) \(default 1\))
+{/Helvetica cf} 2 16 0.000 0.700 -608 112 label
+(bit 2 = hold override value \(value = value during hold mode\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -608 80 label
+(bit 3 = input disable \(0 = input enabled, 1 = input disabled\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -608 48 label
+(bit 4 = IB mode select \(0 = , 1 = \)) {/Helvetica cf} 2 16 0.000 0.700 -608
+16 label
+(bit 5 = analog bus enable \(0 = disabled, 1 = enabled\)) {/Helvetica cf} 2 16
+0.000 0.700 -608 -16 label
+(bit 6 = analog bus select \(0 = , 1 = \)) {/Helvetica cf} 2 16 0.000 0.700
+-608 -48 label
+(bit 7 = analog bus polarity \(0 = , 1 = \)) {/Helvetica cf} 2 16 0.000 0.700
+-608 -80 label
+(bit 8 = slow slew \(0 = fast slew, 1 = slow slew\) \(default 0\))
+{/Helvetica cf} 2 16 0.000 0.700 -608 -112 label
+(bit 9 = input voltage trip point select \(0 = , 1 = \)) {/Helvetica cf} 2 16
+0.000 0.700 -608 -144 label
+(Digital mode bits) {/Helvetica cf} 2 16 0.000 0.700 -672 -240 label
+(Digital mode description) {/Helvetica cf} 2 16 0.000 0.700 -352 -240 label
+(bit 12 11 10) {/Helvetica cf} 2 16 0.000 0.700 -640 -288 label
+(0 0 0) {/Courier cf} 2 16 0.000 0.700 -576 -320 label
+(0 0 1) {/Courier cf} 2 16 0.000 0.700 -576 -352 label
+(0 1 0) {/Courier cf} 2 16 0.000 0.700 -576 -384 label
+(0 1 1) {/Courier cf} 2 16 0.000 0.700 -576 -416 label
+(1 0 0) {/Courier cf} 2 16 0.000 0.700 -576 -448 label
+(1 0 1) {/Courier cf} 2 16 0.000 0.700 -576 -480 label
+(1 1 0) {/Courier cf} 2 16 0.000 0.700 -576 -512 label
+(1 1 1) {/Courier cf} 2 16 0.000 0.700 -576 -544 label
+(0x2d 00 00 00) {/Courier-Bold cf} 2 16 0.000 0.700 -928 -704 label
+(QSPI controller config) {/Helvetica cf} 2 16 0.000 0.700 -672 -704 label
+(bits 3-0 Data bits \(bit bang mode\)) {CR}
+(bit 4 Serial clock line \(bit bang mode\)) {CR}
+(bit 5 Chip select line \(bit bang mode\)) {CR}
+(bits 11-8 I/O output enable bits \(bit bang mode\)) {CR}
+(bits 19-16 Read latency cycles) {CR} (bit 20 CRM enable) {CR}
+(bit 21 QSPI enable) {CR} (bit 22 DDR enable) {CR}
+(bit 31 MEMIO enable \(reset = 1\) 0 = bit-bang mode) {/Helvetica cf} 18 16
+0.000 0.700 -624 -976 label
+1 1.000 32 -768 48 -784 48 -832 32 -848 4 polygon
+(to the limited number of data pins.) {CR} (Note: These cannot be used due)
+{/Helvetica cf} 4 16 0.000 0.700 80 -832 label
+pgsave restore showpage
+
+%%Page: memmap3 22
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+
+0.679 1.000 0.184 scb
+512 1.000 -864 912 -864 -1104 576 -1104 576 912 4 polygon
+sce
+1 1.000 -608 800 -608 -1104 2 polygon
+(Address \(bytes\)) {/Helvetica cf} 2 16 360.000 0.700 -864 784 label
+(Function) {/Helvetica cf} 2 16 0.000 0.700 -592 784 label
+1 1.000 -864 768 576 768 2 polygon
+1 1.000 -864 864 576 864 2 polygon
+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -864 912 label
+(\(continued\)) {/Helvetica-Oblique cf} (Memory Mapped I/O summary by address )
+{/Helvetica-Bold cf} 4 16 0.000 0.700 -864 832 label
+(page 22) {/Helvetica cf} 2 31 0.000 0.700 560 896 label
+(0x2f 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 720 label
+(PLL clock output destination \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700
+-592 720 label
+(0 =) {/Helvetica cf} 2 16 0.000 0.700 -416 688 label
+(1 =) {/Helvetica cf} 2 16 0.000 0.700 -416 656 label
+(0x2f 00 00 04) {/Courier-Bold cf} 2 16 360.000 0.700 -864 512 label
+(Trap output destination \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700 -592 512
+label
+(0 =) {/Helvetica cf} 2 16 0.000 0.700 -416 480 label
+(1 =) {/Helvetica cf} 2 16 0.000 0.700 -416 448 label
+(0x2f 00 00 08) {/Courier-Bold cf} 2 16 360.000 0.700 -864 400 label
+(IRQ 7 input source \(low bit\)) {/Helvetica cf} 2 16 0.000 0.700 -592 400
+label
+(0 =) {/Helvetica cf} 2 16 0.000 0.700 -416 368 label
+(1 =) {/Helvetica cf} 2 16 0.000 0.700 -416 336 label
+(none) {/Helvetica cf} 2 16 0.000 0.700 -352 688 label
+(GPIO) {/Helvetica cf} 2 16 0.000 0.700 -352 656 label
+(none) {/Helvetica cf} 2 16 0.000 0.700 -352 480 label
+(GPIO) {/Helvetica cf} 2 16 0.000 0.700 -352 448 label
+(GPIO) {/Helvetica cf} 2 16 0.000 0.700 -352 336 label
+(none) {/Helvetica cf} 2 16 0.000 0.700 -352 368 label
+(toggle the GPIO at full swing, but is detectable.) {CR}
+(full-speed \(100MHz\) clock will be able to) {CR}
+(for PLL clock output. It is unlikely that a) {CR}
+(be used as general-purpose I/O when selected) {CR}
+(the GPIO pin. The GPIO pin cannot) {CR}
+(multiplied up by PLL\) can be viewed on) {CR}
+(The PLL clock \(crystal oscillator clock) {/Helvetica cf} 14 28 0.000 0.700
+-16 736 label
+(trap state externally.) {CR} (the GPIO pin as a way to monitor the CPU) {CR}
+(The CPU fault state \(trap\) can be viewed at) {/Helvetica cf} 6 28 0.000
+0.700 -16 528 label
+(the GPIO pin must be configured as an input.) {CR}
+(channel 7. When used as an IRQ source,) {CR}
+(source and passed to the CPU through IRQ) {CR}
+(The GPIO input can be used as an IRQ event) {/Helvetica cf} 8 28 0.000 0.700
+-16 416 label
+(0x30 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 224 label
+(User area base) {/Helvetica cf} 2 16 0.000 0.700 -592 224 label
+(at this address.) {CR}
+(A user project may define additional wishbone slave modules starting)
+{/Helvetica cf} 4 28 0.000 0.700 -336 240 label
+(0x80 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 128 label
+(0x90 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 96 label
+(0xa0 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 64 label
+(0xb0 00 00 00) {/Courier-Bold cf} 2 16 360.000 0.700 -864 32 label
+(QSPI controller) {/Helvetica cf} 2 16 0.000 0.700 -592 128 label
+(Storage area SRAM) {/Helvetica cf} 2 16 0.000 0.700 -592 96 label
+(Any slave 1) {/Helvetica cf} 2 16 0.000 0.700 -592 64 label
+(Any slave 2) {/Helvetica cf} 2 16 0.000 0.700 -592 32 label
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+0.679 1.000 0.184 scb
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+sce
+1 1.000 -896 1200 544 1200 2 polygon
+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -896 1248
+label
+(page 23) {/Helvetica cf} 2 31 0.000 0.700 528 1232 label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -896 1152 label
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+0.700 0.000 -176 -352 ::gpio_pad_serial
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+1 1.000 -928 1200 512 1200 2 polygon
+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 1248
+label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -928 1152 label
+(page 24) {/Helvetica cf} 2 31 0.000 0.700 496 1232 label
+0.500 0.000 -256 608 ::gpio_pad_type1
+0.500 0.000 -208 -320 ::gpio_pad_type2
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+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 1248
+label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -928 1152 label
+(page 25) {/Helvetica cf} 2 31 0.000 0.700 496 1232 label
+0.375 0.000 -144 168 ::caravel_areas
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+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 1248
+label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -928 1152 label
+(page 26) {/Helvetica cf} 2 31 0.000 0.700 496 1232 label
+0.340 0.000 -208 200 ::caravel_clamp_plan
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+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 1248
+label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -928 1152 label
+(page 27) {/Helvetica cf} 2 31 0.000 0.700 496 1232 label
+0.350 0.000 -208 144 ::caravel_bump_plan
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+(Efabless Caravel PicoRV32 SoC) {/Helvetica cf} 2 28 0.000 1.000 -928 1248
+label
+(Supplementary material \(to be incorporated into the documentation text\):)
+{/Helvetica-Bold cf} 2 16 0.000 1.000 -928 1152 label
+(page 28) {/Helvetica cf} 2 31 0.000 0.700 496 1232 label
+0.375 0.000 -396 156 ::caravel_pcb_footprint_plan
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+0.679 1.000 0.184 scb
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+sce
+(Absolute maximum ratings) {/Helvetica-Bold cf} 2 16 0.000 0.700 -768 992 label
+1 1.000 -768 976 480 976 2 polygon
+(Supply voltage \(VDDIO\):) {/Helvetica cf} 2 16 0.000 0.700 -768 848 label
+(3.3) {/Helvetica cf} 2 16 0.000 0.700 -160 848 label
+(1.8) {/Helvetica cf} 2 16 0.000 0.700 -352 848 label
+{Ts} (5.0) {/Helvetica cf} 3 16 0.000 0.700 32 848 label
+(\(VCCD\):) {CR} (Core digital supply voltage) {/Helvetica cf} 4 28 0.000 0.700
+-768 800 label
+(1.8) {/Helvetica cf} 2 16 0.000 0.700 -160 784 label
+(1.62) {/Helvetica cf} 2 16 0.000 0.700 -352 784 label
+{Ts} (1.98) {/Helvetica cf} 3 16 0.000 0.700 32 784 label
+(Junction temperature:) {/Helvetica cf} 2 16 0.000 0.700 -768 688 label
+(27) {/Helvetica cf} 2 16 0.000 0.700 -160 688 label
+(\26140) {/Helvetica cf} 2 16 0.000 0.700 -352 688 label
+(OH) {ss} (V) {/Helvetica cf} 4 16 0.000 0.700 -768 624 label
+(OL) {ss} (V) {/Helvetica cf} 4 16 0.000 0.700 -768 560 label
+1 1.000 -768 896 304 896 2 polygon
+1 1.000 -416 896 -416 240 2 polygon
+1 1.000 -224 896 -224 240 2 polygon
+1 1.000 -32 896 -32 240 2 polygon
+1 1.000 144 896 144 240 2 polygon
+(minimum) {/Helvetica-Oblique cf} 2 17 0.000 0.700 -336 912 label
+(typical) {/Helvetica-Oblique cf} 2 17 0.000 0.700 -144 912 label
+(maximum) {/Helvetica-Oblique cf} 2 17 0.000 0.700 64 912 label
+(units) {/Helvetica-Oblique cf} 2 17 0.000 0.700 224 912 label
+(\260C) {/HelveticaISO cf} {/Helvetica cf} 3 16 0.000 0.700 192 688 label
+(V) {/Helvetica cf} 2 16 0.000 0.700 208 848 label
+(V) {/Helvetica cf} 2 16 0.000 0.700 208 784 label
+(100) {/Helvetica cf} 2 16 0.000 0.700 32 688 label
+1 1.000 304 896 304 240 2 polygon
+(VDDIO) {qS} (0.8 \264) {/Helvetica cf} 4 16 0.000 0.700 -400 624 label
+(0.4) {/Helvetica cf} 2 16 0.000 0.700 32 544 label
+(V) {/Helvetica cf} 2 16 0.000 0.700 208 624 label
+(V) {/Helvetica cf} 2 16 0.000 0.700 208 544 label
+(Management area power) {/Helvetica cf} 2 16 0.000 0.700 -768 480 label
+(TBD) {/Helvetica cf} 2 17 0.000 0.700 -144 480 label
+(mW) {/Helvetica cf} 2 17 0.000 0.700 208 480 label
+(page 29) {/Helvetica cf} 2 31 0.000 0.700 464 1008 label
+(Storage area power) {/Helvetica cf} 2 16 0.000 0.700 -768 432 label
+(TBD) {/Helvetica cf} 2 17 0.000 0.700 -144 432 label
+(mW) {/Helvetica cf} 2 17 0.000 0.700 208 432 label
+pgsave restore showpage
+
+%%Page: errata 30
+%%PageOrientation: Portrait
+%%PageBoundingBox: 0 0 612 792
+/pgsave save def bop
+1.0000 inchscale
+2.6000 setlinewidth 1152 1408 translate
+
+0.679 1.000 0.184 scb
+512 1.000 -960 512 -960 -1216 288 -1216 288 512 4 polygon
+sce
+(Errata) {/Helvetica-Bold cf} 2 16 0.000 0.700 -960 480 label
+1 1.000 -960 464 288 464 2 polygon
+(Known errors in the efabless Caravel harness version 1:) {/Helvetica cf} 2 16
+0.000 0.700 -960 416 label
+(page 30) {/Helvetica cf} 2 31 0.000 0.700 272 496 label
+(There are no known errors in Caravel version 1 at this time.) {/Helvetica cf}
+2 16 0.000 0.700 -928 352 label
+(Documentation errata:) {/Helvetica cf} 2 16 0.000 0.700 -960 288 label
+(There are no known errors in the Caravel documentation at this time.)
+{/Helvetica cf} 2 16 0.000 0.700 -928 224 label
+pgsave restore showpage
+
+%%Trailer
+XCIRCsave restore
+%%EOF
diff --git a/docs/ciic_harness.png b/docs/ciic_harness.png
new file mode 100644
index 0000000..0ae2d33
--- /dev/null
+++ b/docs/ciic_harness.png
Binary files differ
diff --git a/docs/counter_32.png b/docs/counter_32.png
new file mode 100644
index 0000000..cbe7e06
--- /dev/null
+++ b/docs/counter_32.png
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diff --git a/docs/docs b/docs/docs
new file mode 120000
index 0000000..5c457d7
--- /dev/null
+++ b/docs/docs
@@ -0,0 +1 @@
+docs
\ No newline at end of file
diff --git a/docs/final_summary_report.csv b/docs/final_summary_report.csv
new file mode 100644
index 0000000..3fb4d55
--- /dev/null
+++ b/docs/final_summary_report.csv
@@ -0,0 +1,6 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/home/cse-p07-2179-gaa/work/Chameleon_SoC/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,0h5m30s,10.2784,316.002490660025,632.00498132005,0,1834.17,3248,0,0,0,0,0,0,0,48,0,-1,959753,33620,0,0,0,-11.57,-0.42,0,0,0,-2455.59,-27.17,926721421,0,8.47,7.02,2.44,1.32,-1,3289,3907,946,1564,0,0,0,3248,82,2,20,28,155,53,68,814,709,650,13,7278,56562,0,63840,95.9692898272553,10.42,10,3,5,50,1,153.6,153.18,0.185,0.35,sky130_fd_sc_hd,8,4
+0,/project/openlane/apb_sys_0,apb_sys_0,apb_sys_0,0h6m17s,0.315,44136.5079365079,88273.0158730159,69,1327.83,13903,0,0,0,0,0,0,0,0,0,0,619566,117208,-7.56,-7.56,-7.56,-29.19,-12.03,-12270.81,-12506.84,-12270.81,-35841.42,-19467.59,461400025,0,49.25,61.41,17.22,34.22,-1,13873,13982,2217,2326,0,0,0,13903,299,5,464,210,1698,944,202,3490,2255,2225,23,498,3888,0,4386,49.9251123315027,20.03,8,2,5,50,1,153.6,153.18,0.65,0.3,sky130_fd_sc_hd,0,4
+0,/project/openlane/DFFRAM_4K,DFFRAM_4K,DFFRAM_4K,0h32m47s,1.54,52640.2597402597,105280.519480519,91,2600.92,81066,0,0,0,0,0,0,0,27,0,0,2967028,648946,-0.25,-0.43,-0.43,-1.46,-2.97,-58.28,-10.76,-10.76,-240.35,-118.82,1259329729,0,48.34,38.34,3.22,2.38,-1,48272,48346,48272,48346,0,0,0,81066,0,0,0,0,0,0,0,0,-1,-1,-1,1012,19556,0,20568,91.1577028258888,10.97,8,2,5,50,1,153.6,153.18,0.83,0,sky130_fd_sc_hd,0,4
+0,/project/openlane/DMC_32x16HC,DMC_32x16HC,DMC_32x16HC,0h3m20s,0.24,43720.8333333333,87441.6666666667,79,1296.4,10493,0,0,0,0,0,0,0,1,0,0,404130,82763,-1.53,-2.55,-2.55,-3.69,-2.49,-41.35,-81.28,-81.28,-115.09,-50.29,165242394,0,53.2,45.27,8.37,3.41,-1,6004,6208,1089,1293,0,0,0,10493,0,0,0,0,14,15,0,0,31,1,6,424,2889,0,3313,117.785630153121,8.49,6,2,5,50,1,153.6,153.18,0.78,0.25,sky130_fd_sc_hd,0,4
+0,/project/openlane/ibex_wrapper,ibex_wrapper,ibex_wrapper,0h13m29s,0.48,42172.9166666667,84345.8333333333,65,1274.23,20243,0,0,0,0,0,0,0,2,0,0,1165507,191544,-17.63,-18.5,-18.5,-24.7,-17.98,-35151.34,-37925.8,-37925.8,-63679.46,-44330.45,888512219,0,50.93,60.08,34.81,43.28,-1,20186,20319,1982,2115,0,0,0,20243,677,0,386,751,2456,787,375,6115,2025,2018,65,572,5904,0,6476,38.4911470361817,25.98,8,3,5,50,1,153.6,153.18,0.7,0.25,sky130_fd_sc_hd,0,4
diff --git a/docs/gds.png b/docs/gds.png
new file mode 100644
index 0000000..f8589c9
--- /dev/null
+++ b/docs/gds.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-10-29 at 11.03.24 AM.png b/docs/images/caravel.Screen Shot 2020-10-29 at 11.03.24 AM.png
new file mode 100644
index 0000000..f95afc4
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-10-29 at 11.03.24 AM.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.31 PM.png b/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.31 PM.png
new file mode 100644
index 0000000..57b6ac6
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.31 PM.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.35 PM.png b/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.35 PM.png
new file mode 100644
index 0000000..4bc96f7
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-11-04 at 7.36.35 PM.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.31 PM.png b/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.31 PM.png
new file mode 100644
index 0000000..3872504
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.31 PM.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.35 PM.png b/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.35 PM.png
new file mode 100644
index 0000000..24dab95
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-11-04 at 7.37.35 PM.png
Binary files differ
diff --git a/docs/images/caravel.Screen Shot 2020-11-04 at 7.38.22 PM.png b/docs/images/caravel.Screen Shot 2020-11-04 at 7.38.22 PM.png
new file mode 100644
index 0000000..b8dfa86
--- /dev/null
+++ b/docs/images/caravel.Screen Shot 2020-11-04 at 7.38.22 PM.png
Binary files differ
diff --git a/docs/images/caravel.caravel.nm.20201104.png b/docs/images/caravel.caravel.nm.20201104.png
new file mode 100644
index 0000000..a597890
--- /dev/null
+++ b/docs/images/caravel.caravel.nm.20201104.png
Binary files differ
diff --git a/docs/images/caravel.layout2.png b/docs/images/caravel.layout2.png
new file mode 100644
index 0000000..4a03281
--- /dev/null
+++ b/docs/images/caravel.layout2.png
Binary files differ
diff --git a/docs/images/caravel.screenshot_202011 5_05-03-48.png b/docs/images/caravel.screenshot_202011 5_05-03-48.png
new file mode 100644
index 0000000..ef432a3
--- /dev/null
+++ b/docs/images/caravel.screenshot_202011 5_05-03-48.png
Binary files differ
diff --git a/docs/manfucturability_report.rpt b/docs/manfucturability_report.rpt
new file mode 100644
index 0000000..736c176
--- /dev/null
+++ b/docs/manfucturability_report.rpt
@@ -0,0 +1,19 @@
+Design Name: user_project_wrapper
+Run Directory: /home/cse-p07-2179-gaa/work/Chameleon_SoC/openlane/user_project_wrapper/runs/user_project_wrapper/
+----------------------------------------
+
+Magic DRC Summary:
+Source: /home/cse-p07-2179-gaa/work/Chameleon_SoC/openlane/user_project_wrapper/runs/user_project_wrapper//logs/magic/magic.drc
+Total Magic DRC violations is 0
+----------------------------------------
+
+LVS Summary:
+Source: /home/cse-p07-2179-gaa/work/Chameleon_SoC/openlane/user_project_wrapper/runs/user_project_wrapper//results/lvs/user_project_wrapper.lvs_parsed.log
+LVS reports no net, device, pin, or property mismatches.
+Total errors = 0
+----------------------------------------
+
+Antenna Summary:
+Source: /home/cse-p07-2179-gaa/work/Chameleon_SoC/openlane/user_project_wrapper/runs/user_project_wrapper//reports/routing/antenna.rpt
+Number of pins violated: 48
+Number of nets violated: 36
\ No newline at end of file
diff --git a/docs/mgmt_soc_memory_map.png b/docs/mgmt_soc_memory_map.png
new file mode 100644
index 0000000..ff29081
--- /dev/null
+++ b/docs/mgmt_soc_memory_map.png
Binary files differ
diff --git a/gds/antenna_on_gds.tcl b/gds/antenna_on_gds.tcl
new file mode 100644
index 0000000..5f379c6
--- /dev/null
+++ b/gds/antenna_on_gds.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_ANTENNA).gds
+select top cell
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+extract unique
+# extract warn all
+extract
+feedback save ./tmp/$::env(DESIGN_IN_ANTENNA)_ext2spice.antenna.feedback.txt
+antennacheck debug
+antennacheck
diff --git a/gds/caravel.png b/gds/caravel.png
new file mode 100644
index 0000000..5a5b950
--- /dev/null
+++ b/gds/caravel.png
Binary files differ
diff --git a/gds/caravel_0001001f.gds.gz b/gds/caravel_0001001f.gds.gz
new file mode 100644
index 0000000..8539902
--- /dev/null
+++ b/gds/caravel_0001001f.gds.gz
Binary files differ
diff --git a/gds/caravel_0001001f_fill_pattern.gds.gz b/gds/caravel_0001001f_fill_pattern.gds.gz
new file mode 100644
index 0000000..b6d0613
--- /dev/null
+++ b/gds/caravel_0001001f_fill_pattern.gds.gz
Binary files differ
diff --git a/gds/caravel_0001001f_fill_pattern_orig.gds.gz b/gds/caravel_0001001f_fill_pattern_orig.gds.gz
new file mode 100644
index 0000000..56a0057
--- /dev/null
+++ b/gds/caravel_0001001f_fill_pattern_orig.gds.gz
Binary files differ
diff --git a/gds/caravel_bump_bond.gds.gz b/gds/caravel_bump_bond.gds.gz
new file mode 100644
index 0000000..02c84e7
--- /dev/null
+++ b/gds/caravel_bump_bond.gds.gz
Binary files differ
diff --git a/gds/drc_on_gds.tcl b/gds/drc_on_gds.tcl
new file mode 100644
index 0000000..8bb3035
--- /dev/null
+++ b/gds/drc_on_gds.tcl
@@ -0,0 +1,61 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_DRC).gds
+set fout [open ./tmp/$::env(DESIGN_IN_DRC).drc w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_IN_DRC)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $::env(DESIGN_IN_DRC)\n"
+flush stdout
+load $::env(DESIGN_IN_DRC)
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+set count 0
+puts $fout "$::env(DESIGN_IN_DRC)"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE (./tmp/$::env(DESIGN_IN_DRC).drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors(./tmp/$::env(DESIGN_IN_DRC).drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save ./tmp/$::env(DESIGN_IN_DRC).drc.drc.mag
+puts stdout "\[INFO\]: Saved"
diff --git a/gds/user_id_prog_zero.gds.gz b/gds/user_id_prog_zero.gds.gz
new file mode 100644
index 0000000..0ad9383
--- /dev/null
+++ b/gds/user_id_prog_zero.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper_new.gds.gz b/gds/user_project_wrapper_new.gds.gz
new file mode 100644
index 0000000..2184387
--- /dev/null
+++ b/gds/user_project_wrapper_new.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper_orig.gds.gz b/gds/user_project_wrapper_orig.gds.gz
new file mode 100644
index 0000000..0d14b52
--- /dev/null
+++ b/gds/user_project_wrapper_orig.gds.gz
Binary files differ
diff --git a/mag/alpha_0.mag b/mag/alpha_0.mag
new file mode 100644
index 0000000..5539e99
--- /dev/null
+++ b/mag/alpha_0.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598786981
+<< metal5 >>
+rect 0 90 45 105
+rect 0 15 15 90
+rect 30 15 45 90
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_1.mag b/mag/alpha_1.mag
new file mode 100644
index 0000000..0de4db8
--- /dev/null
+++ b/mag/alpha_1.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787010
+<< metal5 >>
+rect 15 90 30 105
+rect 0 75 30 90
+rect 15 15 30 75
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_2.mag b/mag/alpha_2.mag
new file mode 100644
index 0000000..26dc7b0
--- /dev/null
+++ b/mag/alpha_2.mag
@@ -0,0 +1,13 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787041
+<< metal5 >>
+rect 0 90 45 105
+rect 30 75 45 90
+rect 0 60 45 75
+rect 0 15 15 60
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_3.mag b/mag/alpha_3.mag
new file mode 100644
index 0000000..7ec3eac
--- /dev/null
+++ b/mag/alpha_3.mag
@@ -0,0 +1,13 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787077
+<< metal5 >>
+rect 0 90 45 105
+rect 30 75 45 90
+rect 0 60 45 75
+rect 30 15 45 60
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_4.mag b/mag/alpha_4.mag
new file mode 100644
index 0000000..809806a
--- /dev/null
+++ b/mag/alpha_4.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787136
+<< metal5 >>
+rect 0 75 15 90
+rect 30 75 45 105
+rect 0 60 45 75
+rect 30 0 45 60
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_5.mag b/mag/alpha_5.mag
new file mode 100644
index 0000000..be5ed52
--- /dev/null
+++ b/mag/alpha_5.mag
@@ -0,0 +1,13 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787165
+<< metal5 >>
+rect 0 90 45 105
+rect 0 75 15 90
+rect 0 60 45 75
+rect 30 15 45 60
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_6.mag b/mag/alpha_6.mag
new file mode 100644
index 0000000..91ff49f
--- /dev/null
+++ b/mag/alpha_6.mag
@@ -0,0 +1,14 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787225
+<< metal5 >>
+rect 0 90 45 105
+rect 0 75 15 90
+rect 0 60 45 75
+rect 0 15 15 60
+rect 30 15 45 60
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_7.mag b/mag/alpha_7.mag
new file mode 100644
index 0000000..61a2aeb
--- /dev/null
+++ b/mag/alpha_7.mag
@@ -0,0 +1,10 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787264
+<< metal5 >>
+rect 0 90 45 105
+rect 30 0 45 90
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_8.mag b/mag/alpha_8.mag
new file mode 100644
index 0000000..735bc4c
--- /dev/null
+++ b/mag/alpha_8.mag
@@ -0,0 +1,15 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787297
+<< metal5 >>
+rect 0 90 45 105
+rect 0 75 15 90
+rect 30 75 45 90
+rect 0 60 45 75
+rect 0 15 15 60
+rect 30 15 45 60
+rect 0 0 45 15
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_9.mag b/mag/alpha_9.mag
new file mode 100644
index 0000000..4bf894e
--- /dev/null
+++ b/mag/alpha_9.mag
@@ -0,0 +1,13 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598787355
+<< metal5 >>
+rect 0 90 45 105
+rect 0 75 15 90
+rect 30 75 45 90
+rect 0 60 45 75
+rect 30 0 45 60
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_A.mag b/mag/alpha_A.mag
new file mode 100644
index 0000000..e2e94f4
--- /dev/null
+++ b/mag/alpha_A.mag
@@ -0,0 +1,16 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598763107
+<< metal5 >>
+rect 10 100 35 105
+rect 5 95 40 100
+rect 0 85 45 95
+rect 0 45 15 85
+rect 30 45 45 85
+rect 0 30 45 45
+rect 0 0 15 30
+rect 30 0 45 30
+<< properties >>
+string FIXED_BBOX 0 -30 60 105
+<< end >>
diff --git a/mag/alpha_B.mag b/mag/alpha_B.mag
new file mode 100644
index 0000000..840c9a8
--- /dev/null
+++ b/mag/alpha_B.mag
@@ -0,0 +1,19 @@
+magic
+tech sky130A
+magscale 36 1
+timestamp 1598763267
+<< metal5 >>
+rect 0 100 35 105
+rect 0 95 40 100
+rect 0 85 45 95
+rect 0 60 15 85
+rect 30 60 45 85
+rect 0 45 45 60
+rect 0 20 15 45
+rect 30 20 45 45
+rect 0 10 45 20
+rect 0 5 40 10
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diff --git a/mag/bump_bond45.mag b/mag/bump_bond45.mag
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index 0000000..dd732f2
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diff --git a/mag/caravel_0001001f.mag b/mag/caravel_0001001f.mag
new file mode 100644
index 0000000..e53146a
--- /dev/null
+++ b/mag/caravel_0001001f.mag
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1613693951
+<< checkpaint >>
+rect -630 -630 360630 520630
+use advSeal_6um_gen advSeal_6um_gen_0
+timestamp 1584566829
+transform 1 0 0 0 1 0
+box 0 0 360000 520000
+use caravel_0001001f_fill_pattern caravel_0001001f_fill_pattern_0
+timestamp 1613693951
+transform 1 0 600 0 1 600
+box 0 0 358800 518800
+use caravel caravel_0
+timestamp 1613693951
+transform 1 0 600 0 1 600
+box 0 0 358800 518800
+<< end >>
diff --git a/mag/caravel_0001001f_fill_pattern_0_0.gds b/mag/caravel_0001001f_fill_pattern_0_0.gds
new file mode 100644
index 0000000..9e713d2
--- /dev/null
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diff --git a/mag/caravel_0001001f_fill_pattern_0_1.gds b/mag/caravel_0001001f_fill_pattern_0_1.gds
new file mode 100644
index 0000000..ff828d3
--- /dev/null
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Binary files differ
diff --git a/mag/caravel_0001001f_fill_pattern_0_2.gds b/mag/caravel_0001001f_fill_pattern_0_2.gds
new file mode 100644
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--- /dev/null
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Binary files differ
diff --git a/mag/caravel_0001001f_fill_pattern_0_3.gds b/mag/caravel_0001001f_fill_pattern_0_3.gds
new file mode 100644
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--- /dev/null
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diff --git a/mag/caravel_0001001f_fill_pattern_0_4.gds b/mag/caravel_0001001f_fill_pattern_0_4.gds
new file mode 100644
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new file mode 100644
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new file mode 100644
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diff --git a/mag/caravel_0001001f_fill_pattern_1_0.gds b/mag/caravel_0001001f_fill_pattern_1_0.gds
new file mode 100644
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--- /dev/null
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diff --git a/mag/caravel_0001001f_fill_pattern_1_1.gds b/mag/caravel_0001001f_fill_pattern_1_1.gds
new file mode 100644
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new file mode 100644
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new file mode 100644
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new file mode 100644
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new file mode 100644
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diff --git a/mag/caravel_0001001f_fill_pattern_2_0.gds b/mag/caravel_0001001f_fill_pattern_2_0.gds
new file mode 100644
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--- /dev/null
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new file mode 100644
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diff --git a/mag/caravel_0001001f_fill_pattern_2_2.gds b/mag/caravel_0001001f_fill_pattern_2_2.gds
new file mode 100644
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diff --git a/mag/caravel_0001001f_fill_pattern_2_3.gds b/mag/caravel_0001001f_fill_pattern_2_3.gds
new file mode 100644
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--- /dev/null
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new file mode 100644
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new file mode 100644
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new file mode 100644
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+transform 0 -1 108800 1 0 468800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_12
+timestamp 1611856895
+transform -1 0 108800 0 -1 368800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_11
+timestamp 1611856895
+transform 0 -1 208800 1 0 468800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_6
+timestamp 1611856895
+transform 0 -1 208800 1 0 368800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_14
+timestamp 1611856895
+transform 1 0 308800 0 1 468800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_7
+timestamp 1611856895
+transform 0 -1 308800 1 0 368800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_32
+timestamp 1611856895
+transform -1 0 508800 0 -1 468800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_15
+timestamp 1611856895
+transform -1 0 408800 0 -1 468800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_8
+timestamp 1611856895
+transform 0 1 408800 -1 0 368800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_12
+timestamp 1611856895
+transform 0 1 508800 -1 0 468800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_9
+timestamp 1611856895
+transform 0 1 508800 -1 0 368800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_16
+timestamp 1611856895
+transform 1 0 608800 0 1 468800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_13
+timestamp 1611856895
+transform 1 0 608800 0 1 368800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_21
+timestamp 1611856895
+transform -1 0 108800 0 -1 668800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_17
+timestamp 1611856895
+transform -1 0 108800 0 -1 568800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_22
+timestamp 1611856895
+transform -1 0 308800 0 -1 668800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_15
+timestamp 1611856895
+transform 0 -1 208800 1 0 668800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_18
+timestamp 1611856895
+transform 1 0 308800 0 1 568800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_13
+timestamp 1611856895
+transform 0 -1 208800 1 0 568800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_17
+timestamp 1611856895
+transform 0 1 508800 -1 0 668800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_16
+timestamp 1611856895
+transform 0 1 408800 -1 0 668800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_14
+timestamp 1611856895
+transform 0 1 508800 -1 0 568800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_19
+timestamp 1611856895
+transform -1 0 408800 0 -1 568800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_23
+timestamp 1611856895
+transform 1 0 608800 0 1 668800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_20
+timestamp 1611856895
+transform 1 0 608800 0 1 568800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_21
+timestamp 1611856895
+transform 0 -1 108800 1 0 868800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_25
+timestamp 1611856895
+transform -1 0 208800 0 -1 768800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_24
+timestamp 1611856895
+transform -1 0 108800 0 -1 768800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_23
+timestamp 1611856895
+transform 0 -1 308800 1 0 868800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_22
+timestamp 1611856895
+transform 0 -1 208800 1 0 868800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_18
+timestamp 1611856895
+transform 0 -1 308800 1 0 768800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_25
+timestamp 1611856895
+transform 1 0 508800 0 1 868800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_24
+timestamp 1611856895
+transform 1 0 408800 0 1 868800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_20
+timestamp 1611856895
+transform 0 1 508800 -1 0 768800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_19
+timestamp 1611856895
+transform 1 0 408800 0 1 768800
+box -27000 -27000 27000 27000
+use bump_bond45 bump_bond45_26
+timestamp 1611856895
+transform 1 0 608800 0 1 868800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_26
+timestamp 1611856895
+transform 1 0 608800 0 1 768800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_27
+timestamp 1611856895
+transform 0 -1 108800 1 0 968800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_29
+timestamp 1611856895
+transform 0 -1 308800 1 0 968800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_28
+timestamp 1611856895
+transform 0 -1 208800 1 0 968800
+box -26897 -26897 38184 26897
+use bump_bond45 bump_bond45_27
+timestamp 1611856895
+transform 1 0 508800 0 1 968800
+box -27000 -27000 27000 27000
+use bump_bond0 bump_bond0_30
+timestamp 1611856895
+transform 0 -1 408800 1 0 968800
+box -26897 -26897 38184 26897
+use bump_bond0 bump_bond0_31
+timestamp 1611856895
+transform 0 -1 608800 1 0 968800
+box -26897 -26897 38184 26897
+<< end >>
diff --git a/mag/copyright_block.mag b/mag/copyright_block.mag
new file mode 100644
index 0000000..c033892
--- /dev/null
+++ b/mag/copyright_block.mag
@@ -0,0 +1,252 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608325192
+<< checkpaint >>
+rect 20630 7518 37910 7764
+rect 20630 3780 52056 7518
+rect -1260 3060 2340 3780
+rect 7380 3060 15300 3780
+rect 16020 3060 52056 3780
+rect -1260 -1260 52056 3060
+rect -1142 -5542 52056 -1260
+rect -1024 -6116 2576 -5542
+rect 3178 -6116 6778 -5542
+rect 6896 -6116 10496 -5542
+rect 11458 -6116 20576 -5542
+rect -1024 -10436 20576 -6116
+rect 20630 -10596 52056 -5542
+rect 34776 -10842 52056 -10596
+<< fillblock >>
+rect -262 -266 26658 2764
+rect -140 -5140 35048 -1424
+rect 26 -9464 19562 -6358
+use font_65 font_65_6 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598775915
+transform 1 0 1676 0 1 -9176
+box 0 0 1080 1800
+use font_44 font_44_1 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598763661
+transform 1 0 236 0 1 -9176
+box 0 0 1080 2520
+use font_65 font_65_7
+timestamp 1598775915
+transform 1 0 4556 0 1 -9176
+box 0 0 1080 1800
+use font_63 font_63_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598836169
+transform 1 0 3116 0 1 -9176
+box 0 0 1080 1800
+use font_6D font_6D_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598776905
+transform 1 0 5996 0 1 -9176
+box 0 0 1800 1800
+use font_65 font_65_8
+timestamp 1598775915
+transform 1 0 9596 0 1 -9176
+box 0 0 1080 1800
+use font_62 font_62_1 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598775406
+transform 1 0 8156 0 1 -9176
+box 0 0 1080 2520
+use font_72 font_72_2 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777237
+transform 1 0 11036 0 1 -9176
+box 0 0 1080 1800
+use font_20 font_20_4 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598785497
+transform 1 0 12476 0 1 -9176
+box 0 0 1 1
+use font_32 font_32_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598787041
+transform 1 0 13916 0 1 -9176
+box 0 0 1080 2520
+use font_30 font_30_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598786981
+transform 1 0 15356 0 1 -9176
+box 0 0 1080 2520
+use font_32 font_32_1
+timestamp 1598787041
+transform 1 0 16796 0 1 -9176
+box 0 0 1080 2520
+use font_30 font_30_1
+timestamp 1598786981
+transform 1 0 18236 0 1 -9176
+box 0 0 1080 2520
+use font_47 font_47_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598765398
+transform 1 0 118 0 1 -4282
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+use font_6F font_6F_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777049
+transform 1 0 1558 0 1 -4282
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+use font_6F font_6F_1
+timestamp 1598777049
+transform 1 0 2998 0 1 -4282
+box 0 0 1080 1800
+use font_67 font_67_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598776042
+transform 1 0 4438 0 1 -4282
+box 0 -720 1080 1800
+use font_65 font_65_3
+timestamp 1598775915
+transform 1 0 6598 0 1 -4282
+box 0 0 1080 1800
+use font_6C font_6C_2 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598776550
+transform 1 0 5878 0 1 -4282
+box 0 0 360 2520
+use font_53 font_53_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598768855
+transform 1 0 9838 0 1 -4282
+box 0 0 1080 2520
+use font_79 font_79_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777870
+transform 1 0 12718 0 1 -4282
+box 0 -720 1080 1800
+use font_6B font_6B_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598776472
+transform 1 0 11278 0 1 -4282
+box 0 0 1080 2520
+use font_57 font_57_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598769216
+transform 1 0 14158 0 1 -4282
+box 0 0 1800 2520
+use font_74 font_74_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777367
+transform 1 0 17758 0 1 -4282
+box 0 0 1080 2160
+use font_61 font_61_3 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598775307
+transform 1 0 16318 0 1 -4282
+box 0 0 1080 1800
+use font_65 font_65_4
+timestamp 1598775915
+transform 1 0 19198 0 1 -4282
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+use font_72 font_72_1
+timestamp 1598777237
+transform 1 0 20638 0 1 -4282
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+use font_20 font_20_2
+timestamp 1598785497
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+use font_65 font_65_5
+timestamp 1598775915
+transform 1 0 26398 0 1 -4282
+box 0 0 1080 1800
+use font_70 font_70_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777090
+transform 1 0 24958 0 1 -4282
+box 0 -720 1080 1800
+use font_20 font_20_3
+timestamp 1598785497
+transform 1 0 29278 0 1 -5362
+box 0 0 1 1
+use font_6E font_6E_1 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598776997
+transform 1 0 27838 0 1 -4282
+box 0 0 1080 1800
+use font_50 font_50_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598768087
+transform 1 0 30718 0 1 -4282
+box 0 0 1080 2520
+use font_44 font_44_0
+timestamp 1598763661
+transform 1 0 32158 0 1 -4282
+box 0 0 1080 2520
+use font_4B font_4B_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598766293
+transform 1 0 33598 0 1 -4282
+box 0 0 1080 2520
+use font_2D font_2D_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598786817
+transform 1 0 8038 0 1 -4642
+box 0 1080 1440 1440
+use font_61 font_61_0
+timestamp 1598775307
+transform 1 0 1440 0 1 0
+box 0 0 1080 1800
+use font_43 font_43_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598763351
+transform 1 0 0 0 1 0
+box 0 0 1080 2520
+use font_72 font_72_0
+timestamp 1598777237
+transform 1 0 2880 0 1 0
+box 0 0 1080 1800
+use font_61 font_61_1
+timestamp 1598775307
+transform 1 0 4320 0 1 0
+box 0 0 1080 1800
+use font_65 font_65_0
+timestamp 1598775915
+transform 1 0 7200 0 1 0
+box 0 0 1080 1800
+use font_76 font_76_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777472
+transform 1 0 5760 0 1 0
+box 0 0 1080 1800
+use font_20 font_20_0
+timestamp 1598785497
+transform 1 0 9360 0 1 0
+box 0 0 1 1
+use font_6C font_6C_0
+timestamp 1598776550
+transform 1 0 8640 0 1 0
+box 0 0 360 2520
+use font_43 font_43_1
+timestamp 1598763351
+transform 1 0 11880 0 1 0
+box 0 0 1080 2520
+use font_28 font_28_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1606780629
+transform 1 0 10800 0 1 0
+box 0 0 720 2520
+use font_29 font_29_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598786350
+transform 1 0 13320 0 1 0
+box 0 0 720 2520
+use font_65 font_65_1
+timestamp 1598775915
+transform 1 0 15840 0 1 0
+box 0 0 1080 1800
+use font_20 font_20_1
+timestamp 1598785497
+transform 1 0 14400 0 1 0
+box 0 0 1 1
+use font_66 font_66_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598775974
+transform 1 0 17280 0 1 0
+box 0 0 1080 2520
+use font_62 font_62_0
+timestamp 1598775406
+transform 1 0 20160 0 1 0
+box 0 0 1080 2520
+use font_61 font_61_2
+timestamp 1598775307
+transform 1 0 18720 0 1 0
+box 0 0 1080 1800
+use font_65 font_65_2
+timestamp 1598775915
+transform 1 0 22320 0 1 0
+box 0 0 1080 1800
+use font_6C font_6C_1
+timestamp 1598776550
+transform 1 0 21600 0 1 0
+box 0 0 360 2520
+use font_73 font_73_0 $PDKPATH/libs.ref/sky130_ml_xx_hd/mag
+timestamp 1598777283
+transform 1 0 23760 0 1 0
+box 0 0 1080 1800
+use font_73 font_73_1
+timestamp 1598777283
+transform 1 0 25200 0 1 0
+box 0 0 1080 1800
+<< end >>
diff --git a/mag/open_source.mag b/mag/open_source.mag
new file mode 100644
index 0000000..6a6e87b
--- /dev/null
+++ b/mag/open_source.mag
@@ -0,0 +1,190 @@
+magic
+tech sky130A
+timestamp 1608325192
+<< checkpaint >>
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+rect 6486 3367 15698 3371
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+rect -630 -630 8010 2790
+<< metal5 >>
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+rect 1260 3060 2340 3240
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+rect 5040 2880 5580 3060
+<< fillblock >>
+rect 376 2582 6603 8121
+rect 6796 3824 14515 6352
+<< end >>
diff --git a/mag/user_id_textblock.mag b/mag/user_id_textblock.mag
new file mode 100644
index 0000000..0d4f3d0
--- /dev/null
+++ b/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_0 alphaX_7 hexdigits
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_6 hexdigits
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_5 hexdigits
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_1 alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_1 alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_F alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
new file mode 100644
index 0000000..30b0d8e
--- /dev/null
+++ b/maglef/user_project_wrapper.mag
@@ -0,0 +1,12295 @@
+magic
+tech sky130A
+timestamp 1606942031
+<< metal2 >>
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+<< labels >>
+rlabel metal3 s 291760 2898 292480 3018 6 analog_io[0]
+port 0 nsew default bidirectional
+rlabel metal3 s 291760 237498 292480 237618 6 analog_io[10]
+port 1 nsew default bidirectional
+rlabel metal3 s 291760 260958 292480 261078 6 analog_io[11]
+port 2 nsew default bidirectional
+rlabel metal3 s 291760 284418 292480 284538 6 analog_io[12]
+port 3 nsew default bidirectional
+rlabel metal3 s 291760 307878 292480 307998 6 analog_io[13]
+port 4 nsew default bidirectional
+rlabel metal3 s 291760 331338 292480 331458 6 analog_io[14]
+port 5 nsew default bidirectional
+rlabel metal2 s 287909 351760 287965 352480 6 analog_io[15]
+port 6 nsew default bidirectional
+rlabel metal2 s 255479 351760 255535 352480 6 analog_io[16]
+port 7 nsew default bidirectional
+rlabel metal2 s 223049 351760 223105 352480 6 analog_io[17]
+port 8 nsew default bidirectional
+rlabel metal2 s 190573 351760 190629 352480 6 analog_io[18]
+port 9 nsew default bidirectional
+rlabel metal2 s 158143 351760 158199 352480 6 analog_io[19]
+port 10 nsew default bidirectional
+rlabel metal3 s 291760 26358 292480 26478 6 analog_io[1]
+port 11 nsew default bidirectional
+rlabel metal2 s 125713 351760 125769 352480 6 analog_io[20]
+port 12 nsew default bidirectional
+rlabel metal2 s 93237 351760 93293 352480 6 analog_io[21]
+port 13 nsew default bidirectional
+rlabel metal2 s 60807 351760 60863 352480 6 analog_io[22]
+port 14 nsew default bidirectional
+rlabel metal2 s 28377 351760 28433 352480 6 analog_io[23]
+port 15 nsew default bidirectional
+rlabel metal3 s -480 348270 240 348390 4 analog_io[24]
+port 16 nsew default bidirectional
+rlabel metal3 s -480 319506 240 319626 4 analog_io[25]
+port 17 nsew default bidirectional
+rlabel metal3 s -480 290810 240 290930 4 analog_io[26]
+port 18 nsew default bidirectional
+rlabel metal3 s -480 262046 240 262166 4 analog_io[27]
+port 19 nsew default bidirectional
+rlabel metal3 s -480 233350 240 233470 4 analog_io[28]
+port 20 nsew default bidirectional
+rlabel metal3 s -480 204586 240 204706 4 analog_io[29]
+port 21 nsew default bidirectional
+rlabel metal3 s 291760 49818 292480 49938 6 analog_io[2]
+port 22 nsew default bidirectional
+rlabel metal3 s -480 175890 240 176010 4 analog_io[30]
+port 23 nsew default bidirectional
+rlabel metal3 s 291760 73278 292480 73398 6 analog_io[3]
+port 24 nsew default bidirectional
+rlabel metal3 s 291760 96738 292480 96858 6 analog_io[4]
+port 25 nsew default bidirectional
+rlabel metal3 s 291760 120198 292480 120318 6 analog_io[5]
+port 26 nsew default bidirectional
+rlabel metal3 s 291760 143658 292480 143778 6 analog_io[6]
+port 27 nsew default bidirectional
+rlabel metal3 s 291760 167118 292480 167238 6 analog_io[7]
+port 28 nsew default bidirectional
+rlabel metal3 s 291760 190578 292480 190698 6 analog_io[8]
+port 29 nsew default bidirectional
+rlabel metal3 s 291760 214038 292480 214158 6 analog_io[9]
+port 30 nsew default bidirectional
+rlabel metal3 s 291760 8746 292480 8866 6 io_in[0]
+port 31 nsew default input
+rlabel metal3 s 291760 243346 292480 243466 6 io_in[10]
+port 32 nsew default input
+rlabel metal3 s 291760 266874 292480 266994 6 io_in[11]
+port 33 nsew default input
+rlabel metal3 s 291760 290334 292480 290454 6 io_in[12]
+port 34 nsew default input
+rlabel metal3 s 291760 313794 292480 313914 6 io_in[13]
+port 35 nsew default input
+rlabel metal3 s 291760 337254 292480 337374 6 io_in[14]
+port 36 nsew default input
+rlabel metal2 s 279813 351760 279869 352480 6 io_in[15]
+port 37 nsew default input
+rlabel metal2 s 247383 351760 247439 352480 6 io_in[16]
+port 38 nsew default input
+rlabel metal2 s 214907 351760 214963 352480 6 io_in[17]
+port 39 nsew default input
+rlabel metal2 s 182477 351760 182533 352480 6 io_in[18]
+port 40 nsew default input
+rlabel metal2 s 150047 351760 150103 352480 6 io_in[19]
+port 41 nsew default input
+rlabel metal3 s 291760 32206 292480 32326 6 io_in[1]
+port 42 nsew default input
+rlabel metal2 s 117571 351760 117627 352480 6 io_in[20]
+port 43 nsew default input
+rlabel metal2 s 85141 351760 85197 352480 6 io_in[21]
+port 44 nsew default input
+rlabel metal2 s 52711 351760 52767 352480 6 io_in[22]
+port 45 nsew default input
+rlabel metal2 s 20235 351760 20291 352480 6 io_in[23]
+port 46 nsew default input
+rlabel metal3 s -480 341062 240 341182 4 io_in[24]
+port 47 nsew default input
+rlabel metal3 s -480 312366 240 312486 4 io_in[25]
+port 48 nsew default input
+rlabel metal3 s -480 283602 240 283722 4 io_in[26]
+port 49 nsew default input
+rlabel metal3 s -480 254906 240 255026 4 io_in[27]
+port 50 nsew default input
+rlabel metal3 s -480 226142 240 226262 4 io_in[28]
+port 51 nsew default input
+rlabel metal3 s -480 197446 240 197566 4 io_in[29]
+port 52 nsew default input
+rlabel metal3 s 291760 55666 292480 55786 6 io_in[2]
+port 53 nsew default input
+rlabel metal3 s -480 168682 240 168802 4 io_in[30]
+port 54 nsew default input
+rlabel metal3 s -480 147126 240 147246 4 io_in[31]
+port 55 nsew default input
+rlabel metal3 s -480 125570 240 125690 4 io_in[32]
+port 56 nsew default input
+rlabel metal3 s -480 104014 240 104134 4 io_in[33]
+port 57 nsew default input
+rlabel metal3 s -480 82458 240 82578 4 io_in[34]
+port 58 nsew default input
+rlabel metal3 s -480 60970 240 61090 4 io_in[35]
+port 59 nsew default input
+rlabel metal3 s -480 39414 240 39534 4 io_in[36]
+port 60 nsew default input
+rlabel metal3 s -480 17858 240 17978 4 io_in[37]
+port 61 nsew default input
+rlabel metal3 s 291760 79126 292480 79246 6 io_in[3]
+port 62 nsew default input
+rlabel metal3 s 291760 102586 292480 102706 6 io_in[4]
+port 63 nsew default input
+rlabel metal3 s 291760 126046 292480 126166 6 io_in[5]
+port 64 nsew default input
+rlabel metal3 s 291760 149506 292480 149626 6 io_in[6]
+port 65 nsew default input
+rlabel metal3 s 291760 172966 292480 173086 6 io_in[7]
+port 66 nsew default input
+rlabel metal3 s 291760 196426 292480 196546 6 io_in[8]
+port 67 nsew default input
+rlabel metal3 s 291760 219886 292480 220006 6 io_in[9]
+port 68 nsew default input
+rlabel metal3 s 291760 20442 292480 20562 6 io_oeb[0]
+port 69 nsew default tristate
+rlabel metal3 s 291760 255110 292480 255230 6 io_oeb[10]
+port 70 nsew default tristate
+rlabel metal3 s 291760 278570 292480 278690 6 io_oeb[11]
+port 71 nsew default tristate
+rlabel metal3 s 291760 302030 292480 302150 6 io_oeb[12]
+port 72 nsew default tristate
+rlabel metal3 s 291760 325490 292480 325610 6 io_oeb[13]
+port 73 nsew default tristate
+rlabel metal3 s 291760 348950 292480 349070 6 io_oeb[14]
+port 74 nsew default tristate
+rlabel metal2 s 263575 351760 263631 352480 6 io_oeb[15]
+port 75 nsew default tristate
+rlabel metal2 s 231145 351760 231201 352480 6 io_oeb[16]
+port 76 nsew default tristate
+rlabel metal2 s 198715 351760 198771 352480 6 io_oeb[17]
+port 77 nsew default tristate
+rlabel metal2 s 166239 351760 166295 352480 6 io_oeb[18]
+port 78 nsew default tristate
+rlabel metal2 s 133809 351760 133865 352480 6 io_oeb[19]
+port 79 nsew default tristate
+rlabel metal3 s 291760 43902 292480 44022 6 io_oeb[1]
+port 80 nsew default tristate
+rlabel metal2 s 101379 351760 101435 352480 6 io_oeb[20]
+port 81 nsew default tristate
+rlabel metal2 s 68903 351760 68959 352480 6 io_oeb[21]
+port 82 nsew default tristate
+rlabel metal2 s 36473 351760 36529 352480 6 io_oeb[22]
+port 83 nsew default tristate
+rlabel metal2 s 4043 351760 4099 352480 6 io_oeb[23]
+port 84 nsew default tristate
+rlabel metal3 s -480 326714 240 326834 4 io_oeb[24]
+port 85 nsew default tristate
+rlabel metal3 s -480 297950 240 298070 4 io_oeb[25]
+port 86 nsew default tristate
+rlabel metal3 s -480 269254 240 269374 4 io_oeb[26]
+port 87 nsew default tristate
+rlabel metal3 s -480 240490 240 240610 4 io_oeb[27]
+port 88 nsew default tristate
+rlabel metal3 s -480 211794 240 211914 4 io_oeb[28]
+port 89 nsew default tristate
+rlabel metal3 s -480 183030 240 183150 4 io_oeb[29]
+port 90 nsew default tristate
+rlabel metal3 s 291760 67362 292480 67482 6 io_oeb[2]
+port 91 nsew default tristate
+rlabel metal3 s -480 154334 240 154454 4 io_oeb[30]
+port 92 nsew default tristate
+rlabel metal3 s -480 132778 240 132898 4 io_oeb[31]
+port 93 nsew default tristate
+rlabel metal3 s -480 111222 240 111342 4 io_oeb[32]
+port 94 nsew default tristate
+rlabel metal3 s -480 89666 240 89786 4 io_oeb[33]
+port 95 nsew default tristate
+rlabel metal3 s -480 68110 240 68230 4 io_oeb[34]
+port 96 nsew default tristate
+rlabel metal3 s -480 46554 240 46674 4 io_oeb[35]
+port 97 nsew default tristate
+rlabel metal3 s -480 24998 240 25118 4 io_oeb[36]
+port 98 nsew default tristate
+rlabel metal3 s -480 3510 240 3630 4 io_oeb[37]
+port 99 nsew default tristate
+rlabel metal3 s 291760 90890 292480 91010 6 io_oeb[3]
+port 100 nsew default tristate
+rlabel metal3 s 291760 114350 292480 114470 6 io_oeb[4]
+port 101 nsew default tristate
+rlabel metal3 s 291760 137810 292480 137930 6 io_oeb[5]
+port 102 nsew default tristate
+rlabel metal3 s 291760 161270 292480 161390 6 io_oeb[6]
+port 103 nsew default tristate
+rlabel metal3 s 291760 184730 292480 184850 6 io_oeb[7]
+port 104 nsew default tristate
+rlabel metal3 s 291760 208190 292480 208310 6 io_oeb[8]
+port 105 nsew default tristate
+rlabel metal3 s 291760 231650 292480 231770 6 io_oeb[9]
+port 106 nsew default tristate
+rlabel metal3 s 291760 14594 292480 14714 6 io_out[0]
+port 107 nsew default tristate
+rlabel metal3 s 291760 249262 292480 249382 6 io_out[10]
+port 108 nsew default tristate
+rlabel metal3 s 291760 272722 292480 272842 6 io_out[11]
+port 109 nsew default tristate
+rlabel metal3 s 291760 296182 292480 296302 6 io_out[12]
+port 110 nsew default tristate
+rlabel metal3 s 291760 319642 292480 319762 6 io_out[13]
+port 111 nsew default tristate
+rlabel metal3 s 291760 343102 292480 343222 6 io_out[14]
+port 112 nsew default tristate
+rlabel metal2 s 271717 351760 271773 352480 6 io_out[15]
+port 113 nsew default tristate
+rlabel metal2 s 239241 351760 239297 352480 6 io_out[16]
+port 114 nsew default tristate
+rlabel metal2 s 206811 351760 206867 352480 6 io_out[17]
+port 115 nsew default tristate
+rlabel metal2 s 174381 351760 174437 352480 6 io_out[18]
+port 116 nsew default tristate
+rlabel metal2 s 141905 351760 141961 352480 6 io_out[19]
+port 117 nsew default tristate
+rlabel metal3 s 291760 38054 292480 38174 6 io_out[1]
+port 118 nsew default tristate
+rlabel metal2 s 109475 351760 109531 352480 6 io_out[20]
+port 119 nsew default tristate
+rlabel metal2 s 77045 351760 77101 352480 6 io_out[21]
+port 120 nsew default tristate
+rlabel metal2 s 44569 351760 44625 352480 6 io_out[22]
+port 121 nsew default tristate
+rlabel metal2 s 12139 351760 12195 352480 6 io_out[23]
+port 122 nsew default tristate
+rlabel metal3 s -480 333922 240 334042 4 io_out[24]
+port 123 nsew default tristate
+rlabel metal3 s -480 305158 240 305278 4 io_out[25]
+port 124 nsew default tristate
+rlabel metal3 s -480 276462 240 276582 4 io_out[26]
+port 125 nsew default tristate
+rlabel metal3 s -480 247698 240 247818 4 io_out[27]
+port 126 nsew default tristate
+rlabel metal3 s -480 218934 240 219054 4 io_out[28]
+port 127 nsew default tristate
+rlabel metal3 s -480 190238 240 190358 4 io_out[29]
+port 128 nsew default tristate
+rlabel metal3 s 291760 61514 292480 61634 6 io_out[2]
+port 129 nsew default tristate
+rlabel metal3 s -480 161474 240 161594 4 io_out[30]
+port 130 nsew default tristate
+rlabel metal3 s -480 139986 240 140106 4 io_out[31]
+port 131 nsew default tristate
+rlabel metal3 s -480 118430 240 118550 4 io_out[32]
+port 132 nsew default tristate
+rlabel metal3 s -480 96874 240 96994 4 io_out[33]
+port 133 nsew default tristate
+rlabel metal3 s -480 75318 240 75438 4 io_out[34]
+port 134 nsew default tristate
+rlabel metal3 s -480 53762 240 53882 4 io_out[35]
+port 135 nsew default tristate
+rlabel metal3 s -480 32206 240 32326 4 io_out[36]
+port 136 nsew default tristate
+rlabel metal3 s -480 10650 240 10770 4 io_out[37]
+port 137 nsew default tristate
+rlabel metal3 s 291760 84974 292480 85094 6 io_out[3]
+port 138 nsew default tristate
+rlabel metal3 s 291760 108434 292480 108554 6 io_out[4]
+port 139 nsew default tristate
+rlabel metal3 s 291760 131894 292480 132014 6 io_out[5]
+port 140 nsew default tristate
+rlabel metal3 s 291760 155354 292480 155474 6 io_out[6]
+port 141 nsew default tristate
+rlabel metal3 s 291760 178882 292480 179002 6 io_out[7]
+port 142 nsew default tristate
+rlabel metal3 s 291760 202342 292480 202462 6 io_out[8]
+port 143 nsew default tristate
+rlabel metal3 s 291760 225802 292480 225922 6 io_out[9]
+port 144 nsew default tristate
+rlabel metal2 s 63291 -480 63347 240 8 la_data_in[0]
+port 145 nsew default input
+rlabel metal2 s 241725 -480 241781 240 8 la_data_in[100]
+port 146 nsew default input
+rlabel metal2 s 243473 -480 243529 240 8 la_data_in[101]
+port 147 nsew default input
+rlabel metal2 s 245267 -480 245323 240 8 la_data_in[102]
+port 148 nsew default input
+rlabel metal2 s 247061 -480 247117 240 8 la_data_in[103]
+port 149 nsew default input
+rlabel metal2 s 248855 -480 248911 240 8 la_data_in[104]
+port 150 nsew default input
+rlabel metal2 s 250603 -480 250659 240 8 la_data_in[105]
+port 151 nsew default input
+rlabel metal2 s 252397 -480 252453 240 8 la_data_in[106]
+port 152 nsew default input
+rlabel metal2 s 254191 -480 254247 240 8 la_data_in[107]
+port 153 nsew default input
+rlabel metal2 s 255985 -480 256041 240 8 la_data_in[108]
+port 154 nsew default input
+rlabel metal2 s 257779 -480 257835 240 8 la_data_in[109]
+port 155 nsew default input
+rlabel metal2 s 81139 -480 81195 240 8 la_data_in[10]
+port 156 nsew default input
+rlabel metal2 s 259527 -480 259583 240 8 la_data_in[110]
+port 157 nsew default input
+rlabel metal2 s 261321 -480 261377 240 8 la_data_in[111]
+port 158 nsew default input
+rlabel metal2 s 263115 -480 263171 240 8 la_data_in[112]
+port 159 nsew default input
+rlabel metal2 s 264909 -480 264965 240 8 la_data_in[113]
+port 160 nsew default input
+rlabel metal2 s 266703 -480 266759 240 8 la_data_in[114]
+port 161 nsew default input
+rlabel metal2 s 268451 -480 268507 240 8 la_data_in[115]
+port 162 nsew default input
+rlabel metal2 s 270245 -480 270301 240 8 la_data_in[116]
+port 163 nsew default input
+rlabel metal2 s 272039 -480 272095 240 8 la_data_in[117]
+port 164 nsew default input
+rlabel metal2 s 273833 -480 273889 240 8 la_data_in[118]
+port 165 nsew default input
+rlabel metal2 s 275581 -480 275637 240 8 la_data_in[119]
+port 166 nsew default input
+rlabel metal2 s 82933 -480 82989 240 8 la_data_in[11]
+port 167 nsew default input
+rlabel metal2 s 277375 -480 277431 240 8 la_data_in[120]
+port 168 nsew default input
+rlabel metal2 s 279169 -480 279225 240 8 la_data_in[121]
+port 169 nsew default input
+rlabel metal2 s 280963 -480 281019 240 8 la_data_in[122]
+port 170 nsew default input
+rlabel metal2 s 282757 -480 282813 240 8 la_data_in[123]
+port 171 nsew default input
+rlabel metal2 s 284505 -480 284561 240 8 la_data_in[124]
+port 172 nsew default input
+rlabel metal2 s 286299 -480 286355 240 8 la_data_in[125]
+port 173 nsew default input
+rlabel metal2 s 288093 -480 288149 240 8 la_data_in[126]
+port 174 nsew default input
+rlabel metal2 s 289887 -480 289943 240 8 la_data_in[127]
+port 175 nsew default input
+rlabel metal2 s 84681 -480 84737 240 8 la_data_in[12]
+port 176 nsew default input
+rlabel metal2 s 86475 -480 86531 240 8 la_data_in[13]
+port 177 nsew default input
+rlabel metal2 s 88269 -480 88325 240 8 la_data_in[14]
+port 178 nsew default input
+rlabel metal2 s 90063 -480 90119 240 8 la_data_in[15]
+port 179 nsew default input
+rlabel metal2 s 91857 -480 91913 240 8 la_data_in[16]
+port 180 nsew default input
+rlabel metal2 s 93605 -480 93661 240 8 la_data_in[17]
+port 181 nsew default input
+rlabel metal2 s 95399 -480 95455 240 8 la_data_in[18]
+port 182 nsew default input
+rlabel metal2 s 97193 -480 97249 240 8 la_data_in[19]
+port 183 nsew default input
+rlabel metal2 s 65085 -480 65141 240 8 la_data_in[1]
+port 184 nsew default input
+rlabel metal2 s 98987 -480 99043 240 8 la_data_in[20]
+port 185 nsew default input
+rlabel metal2 s 100735 -480 100791 240 8 la_data_in[21]
+port 186 nsew default input
+rlabel metal2 s 102529 -480 102585 240 8 la_data_in[22]
+port 187 nsew default input
+rlabel metal2 s 104323 -480 104379 240 8 la_data_in[23]
+port 188 nsew default input
+rlabel metal2 s 106117 -480 106173 240 8 la_data_in[24]
+port 189 nsew default input
+rlabel metal2 s 107911 -480 107967 240 8 la_data_in[25]
+port 190 nsew default input
+rlabel metal2 s 109659 -480 109715 240 8 la_data_in[26]
+port 191 nsew default input
+rlabel metal2 s 111453 -480 111509 240 8 la_data_in[27]
+port 192 nsew default input
+rlabel metal2 s 113247 -480 113303 240 8 la_data_in[28]
+port 193 nsew default input
+rlabel metal2 s 115041 -480 115097 240 8 la_data_in[29]
+port 194 nsew default input
+rlabel metal2 s 66879 -480 66935 240 8 la_data_in[2]
+port 195 nsew default input
+rlabel metal2 s 116835 -480 116891 240 8 la_data_in[30]
+port 196 nsew default input
+rlabel metal2 s 118583 -480 118639 240 8 la_data_in[31]
+port 197 nsew default input
+rlabel metal2 s 120377 -480 120433 240 8 la_data_in[32]
+port 198 nsew default input
+rlabel metal2 s 122171 -480 122227 240 8 la_data_in[33]
+port 199 nsew default input
+rlabel metal2 s 123965 -480 124021 240 8 la_data_in[34]
+port 200 nsew default input
+rlabel metal2 s 125713 -480 125769 240 8 la_data_in[35]
+port 201 nsew default input
+rlabel metal2 s 127507 -480 127563 240 8 la_data_in[36]
+port 202 nsew default input
+rlabel metal2 s 129301 -480 129357 240 8 la_data_in[37]
+port 203 nsew default input
+rlabel metal2 s 131095 -480 131151 240 8 la_data_in[38]
+port 204 nsew default input
+rlabel metal2 s 132889 -480 132945 240 8 la_data_in[39]
+port 205 nsew default input
+rlabel metal2 s 68627 -480 68683 240 8 la_data_in[3]
+port 206 nsew default input
+rlabel metal2 s 134637 -480 134693 240 8 la_data_in[40]
+port 207 nsew default input
+rlabel metal2 s 136431 -480 136487 240 8 la_data_in[41]
+port 208 nsew default input
+rlabel metal2 s 138225 -480 138281 240 8 la_data_in[42]
+port 209 nsew default input
+rlabel metal2 s 140019 -480 140075 240 8 la_data_in[43]
+port 210 nsew default input
+rlabel metal2 s 141813 -480 141869 240 8 la_data_in[44]
+port 211 nsew default input
+rlabel metal2 s 143561 -480 143617 240 8 la_data_in[45]
+port 212 nsew default input
+rlabel metal2 s 145355 -480 145411 240 8 la_data_in[46]
+port 213 nsew default input
+rlabel metal2 s 147149 -480 147205 240 8 la_data_in[47]
+port 214 nsew default input
+rlabel metal2 s 148943 -480 148999 240 8 la_data_in[48]
+port 215 nsew default input
+rlabel metal2 s 150691 -480 150747 240 8 la_data_in[49]
+port 216 nsew default input
+rlabel metal2 s 70421 -480 70477 240 8 la_data_in[4]
+port 217 nsew default input
+rlabel metal2 s 152485 -480 152541 240 8 la_data_in[50]
+port 218 nsew default input
+rlabel metal2 s 154279 -480 154335 240 8 la_data_in[51]
+port 219 nsew default input
+rlabel metal2 s 156073 -480 156129 240 8 la_data_in[52]
+port 220 nsew default input
+rlabel metal2 s 157867 -480 157923 240 8 la_data_in[53]
+port 221 nsew default input
+rlabel metal2 s 159615 -480 159671 240 8 la_data_in[54]
+port 222 nsew default input
+rlabel metal2 s 161409 -480 161465 240 8 la_data_in[55]
+port 223 nsew default input
+rlabel metal2 s 163203 -480 163259 240 8 la_data_in[56]
+port 224 nsew default input
+rlabel metal2 s 164997 -480 165053 240 8 la_data_in[57]
+port 225 nsew default input
+rlabel metal2 s 166791 -480 166847 240 8 la_data_in[58]
+port 226 nsew default input
+rlabel metal2 s 168539 -480 168595 240 8 la_data_in[59]
+port 227 nsew default input
+rlabel metal2 s 72215 -480 72271 240 8 la_data_in[5]
+port 228 nsew default input
+rlabel metal2 s 170333 -480 170389 240 8 la_data_in[60]
+port 229 nsew default input
+rlabel metal2 s 172127 -480 172183 240 8 la_data_in[61]
+port 230 nsew default input
+rlabel metal2 s 173921 -480 173977 240 8 la_data_in[62]
+port 231 nsew default input
+rlabel metal2 s 175669 -480 175725 240 8 la_data_in[63]
+port 232 nsew default input
+rlabel metal2 s 177463 -480 177519 240 8 la_data_in[64]
+port 233 nsew default input
+rlabel metal2 s 179257 -480 179313 240 8 la_data_in[65]
+port 234 nsew default input
+rlabel metal2 s 181051 -480 181107 240 8 la_data_in[66]
+port 235 nsew default input
+rlabel metal2 s 182845 -480 182901 240 8 la_data_in[67]
+port 236 nsew default input
+rlabel metal2 s 184593 -480 184649 240 8 la_data_in[68]
+port 237 nsew default input
+rlabel metal2 s 186387 -480 186443 240 8 la_data_in[69]
+port 238 nsew default input
+rlabel metal2 s 74009 -480 74065 240 8 la_data_in[6]
+port 239 nsew default input
+rlabel metal2 s 188181 -480 188237 240 8 la_data_in[70]
+port 240 nsew default input
+rlabel metal2 s 189975 -480 190031 240 8 la_data_in[71]
+port 241 nsew default input
+rlabel metal2 s 191769 -480 191825 240 8 la_data_in[72]
+port 242 nsew default input
+rlabel metal2 s 193517 -480 193573 240 8 la_data_in[73]
+port 243 nsew default input
+rlabel metal2 s 195311 -480 195367 240 8 la_data_in[74]
+port 244 nsew default input
+rlabel metal2 s 197105 -480 197161 240 8 la_data_in[75]
+port 245 nsew default input
+rlabel metal2 s 198899 -480 198955 240 8 la_data_in[76]
+port 246 nsew default input
+rlabel metal2 s 200647 -480 200703 240 8 la_data_in[77]
+port 247 nsew default input
+rlabel metal2 s 202441 -480 202497 240 8 la_data_in[78]
+port 248 nsew default input
+rlabel metal2 s 204235 -480 204291 240 8 la_data_in[79]
+port 249 nsew default input
+rlabel metal2 s 75757 -480 75813 240 8 la_data_in[7]
+port 250 nsew default input
+rlabel metal2 s 206029 -480 206085 240 8 la_data_in[80]
+port 251 nsew default input
+rlabel metal2 s 207823 -480 207879 240 8 la_data_in[81]
+port 252 nsew default input
+rlabel metal2 s 209571 -480 209627 240 8 la_data_in[82]
+port 253 nsew default input
+rlabel metal2 s 211365 -480 211421 240 8 la_data_in[83]
+port 254 nsew default input
+rlabel metal2 s 213159 -480 213215 240 8 la_data_in[84]
+port 255 nsew default input
+rlabel metal2 s 214953 -480 215009 240 8 la_data_in[85]
+port 256 nsew default input
+rlabel metal2 s 216747 -480 216803 240 8 la_data_in[86]
+port 257 nsew default input
+rlabel metal2 s 218495 -480 218551 240 8 la_data_in[87]
+port 258 nsew default input
+rlabel metal2 s 220289 -480 220345 240 8 la_data_in[88]
+port 259 nsew default input
+rlabel metal2 s 222083 -480 222139 240 8 la_data_in[89]
+port 260 nsew default input
+rlabel metal2 s 77551 -480 77607 240 8 la_data_in[8]
+port 261 nsew default input
+rlabel metal2 s 223877 -480 223933 240 8 la_data_in[90]
+port 262 nsew default input
+rlabel metal2 s 225625 -480 225681 240 8 la_data_in[91]
+port 263 nsew default input
+rlabel metal2 s 227419 -480 227475 240 8 la_data_in[92]
+port 264 nsew default input
+rlabel metal2 s 229213 -480 229269 240 8 la_data_in[93]
+port 265 nsew default input
+rlabel metal2 s 231007 -480 231063 240 8 la_data_in[94]
+port 266 nsew default input
+rlabel metal2 s 232801 -480 232857 240 8 la_data_in[95]
+port 267 nsew default input
+rlabel metal2 s 234549 -480 234605 240 8 la_data_in[96]
+port 268 nsew default input
+rlabel metal2 s 236343 -480 236399 240 8 la_data_in[97]
+port 269 nsew default input
+rlabel metal2 s 238137 -480 238193 240 8 la_data_in[98]
+port 270 nsew default input
+rlabel metal2 s 239931 -480 239987 240 8 la_data_in[99]
+port 271 nsew default input
+rlabel metal2 s 79345 -480 79401 240 8 la_data_in[9]
+port 272 nsew default input
+rlabel metal2 s 63889 -480 63945 240 8 la_data_out[0]
+port 273 nsew default tristate
+rlabel metal2 s 242277 -480 242333 240 8 la_data_out[100]
+port 274 nsew default tristate
+rlabel metal2 s 244071 -480 244127 240 8 la_data_out[101]
+port 275 nsew default tristate
+rlabel metal2 s 245865 -480 245921 240 8 la_data_out[102]
+port 276 nsew default tristate
+rlabel metal2 s 247659 -480 247715 240 8 la_data_out[103]
+port 277 nsew default tristate
+rlabel metal2 s 249453 -480 249509 240 8 la_data_out[104]
+port 278 nsew default tristate
+rlabel metal2 s 251201 -480 251257 240 8 la_data_out[105]
+port 279 nsew default tristate
+rlabel metal2 s 252995 -480 253051 240 8 la_data_out[106]
+port 280 nsew default tristate
+rlabel metal2 s 254789 -480 254845 240 8 la_data_out[107]
+port 281 nsew default tristate
+rlabel metal2 s 256583 -480 256639 240 8 la_data_out[108]
+port 282 nsew default tristate
+rlabel metal2 s 258377 -480 258433 240 8 la_data_out[109]
+port 283 nsew default tristate
+rlabel metal2 s 81737 -480 81793 240 8 la_data_out[10]
+port 284 nsew default tristate
+rlabel metal2 s 260125 -480 260181 240 8 la_data_out[110]
+port 285 nsew default tristate
+rlabel metal2 s 261919 -480 261975 240 8 la_data_out[111]
+port 286 nsew default tristate
+rlabel metal2 s 263713 -480 263769 240 8 la_data_out[112]
+port 287 nsew default tristate
+rlabel metal2 s 265507 -480 265563 240 8 la_data_out[113]
+port 288 nsew default tristate
+rlabel metal2 s 267255 -480 267311 240 8 la_data_out[114]
+port 289 nsew default tristate
+rlabel metal2 s 269049 -480 269105 240 8 la_data_out[115]
+port 290 nsew default tristate
+rlabel metal2 s 270843 -480 270899 240 8 la_data_out[116]
+port 291 nsew default tristate
+rlabel metal2 s 272637 -480 272693 240 8 la_data_out[117]
+port 292 nsew default tristate
+rlabel metal2 s 274431 -480 274487 240 8 la_data_out[118]
+port 293 nsew default tristate
+rlabel metal2 s 276179 -480 276235 240 8 la_data_out[119]
+port 294 nsew default tristate
+rlabel metal2 s 83531 -480 83587 240 8 la_data_out[11]
+port 295 nsew default tristate
+rlabel metal2 s 277973 -480 278029 240 8 la_data_out[120]
+port 296 nsew default tristate
+rlabel metal2 s 279767 -480 279823 240 8 la_data_out[121]
+port 297 nsew default tristate
+rlabel metal2 s 281561 -480 281617 240 8 la_data_out[122]
+port 298 nsew default tristate
+rlabel metal2 s 283355 -480 283411 240 8 la_data_out[123]
+port 299 nsew default tristate
+rlabel metal2 s 285103 -480 285159 240 8 la_data_out[124]
+port 300 nsew default tristate
+rlabel metal2 s 286897 -480 286953 240 8 la_data_out[125]
+port 301 nsew default tristate
+rlabel metal2 s 288691 -480 288747 240 8 la_data_out[126]
+port 302 nsew default tristate
+rlabel metal2 s 290485 -480 290541 240 8 la_data_out[127]
+port 303 nsew default tristate
+rlabel metal2 s 85279 -480 85335 240 8 la_data_out[12]
+port 304 nsew default tristate
+rlabel metal2 s 87073 -480 87129 240 8 la_data_out[13]
+port 305 nsew default tristate
+rlabel metal2 s 88867 -480 88923 240 8 la_data_out[14]
+port 306 nsew default tristate
+rlabel metal2 s 90661 -480 90717 240 8 la_data_out[15]
+port 307 nsew default tristate
+rlabel metal2 s 92409 -480 92465 240 8 la_data_out[16]
+port 308 nsew default tristate
+rlabel metal2 s 94203 -480 94259 240 8 la_data_out[17]
+port 309 nsew default tristate
+rlabel metal2 s 95997 -480 96053 240 8 la_data_out[18]
+port 310 nsew default tristate
+rlabel metal2 s 97791 -480 97847 240 8 la_data_out[19]
+port 311 nsew default tristate
+rlabel metal2 s 65683 -480 65739 240 8 la_data_out[1]
+port 312 nsew default tristate
+rlabel metal2 s 99585 -480 99641 240 8 la_data_out[20]
+port 313 nsew default tristate
+rlabel metal2 s 101333 -480 101389 240 8 la_data_out[21]
+port 314 nsew default tristate
+rlabel metal2 s 103127 -480 103183 240 8 la_data_out[22]
+port 315 nsew default tristate
+rlabel metal2 s 104921 -480 104977 240 8 la_data_out[23]
+port 316 nsew default tristate
+rlabel metal2 s 106715 -480 106771 240 8 la_data_out[24]
+port 317 nsew default tristate
+rlabel metal2 s 108509 -480 108565 240 8 la_data_out[25]
+port 318 nsew default tristate
+rlabel metal2 s 110257 -480 110313 240 8 la_data_out[26]
+port 319 nsew default tristate
+rlabel metal2 s 112051 -480 112107 240 8 la_data_out[27]
+port 320 nsew default tristate
+rlabel metal2 s 113845 -480 113901 240 8 la_data_out[28]
+port 321 nsew default tristate
+rlabel metal2 s 115639 -480 115695 240 8 la_data_out[29]
+port 322 nsew default tristate
+rlabel metal2 s 67431 -480 67487 240 8 la_data_out[2]
+port 323 nsew default tristate
+rlabel metal2 s 117387 -480 117443 240 8 la_data_out[30]
+port 324 nsew default tristate
+rlabel metal2 s 119181 -480 119237 240 8 la_data_out[31]
+port 325 nsew default tristate
+rlabel metal2 s 120975 -480 121031 240 8 la_data_out[32]
+port 326 nsew default tristate
+rlabel metal2 s 122769 -480 122825 240 8 la_data_out[33]
+port 327 nsew default tristate
+rlabel metal2 s 124563 -480 124619 240 8 la_data_out[34]
+port 328 nsew default tristate
+rlabel metal2 s 126311 -480 126367 240 8 la_data_out[35]
+port 329 nsew default tristate
+rlabel metal2 s 128105 -480 128161 240 8 la_data_out[36]
+port 330 nsew default tristate
+rlabel metal2 s 129899 -480 129955 240 8 la_data_out[37]
+port 331 nsew default tristate
+rlabel metal2 s 131693 -480 131749 240 8 la_data_out[38]
+port 332 nsew default tristate
+rlabel metal2 s 133487 -480 133543 240 8 la_data_out[39]
+port 333 nsew default tristate
+rlabel metal2 s 69225 -480 69281 240 8 la_data_out[3]
+port 334 nsew default tristate
+rlabel metal2 s 135235 -480 135291 240 8 la_data_out[40]
+port 335 nsew default tristate
+rlabel metal2 s 137029 -480 137085 240 8 la_data_out[41]
+port 336 nsew default tristate
+rlabel metal2 s 138823 -480 138879 240 8 la_data_out[42]
+port 337 nsew default tristate
+rlabel metal2 s 140617 -480 140673 240 8 la_data_out[43]
+port 338 nsew default tristate
+rlabel metal2 s 142365 -480 142421 240 8 la_data_out[44]
+port 339 nsew default tristate
+rlabel metal2 s 144159 -480 144215 240 8 la_data_out[45]
+port 340 nsew default tristate
+rlabel metal2 s 145953 -480 146009 240 8 la_data_out[46]
+port 341 nsew default tristate
+rlabel metal2 s 147747 -480 147803 240 8 la_data_out[47]
+port 342 nsew default tristate
+rlabel metal2 s 149541 -480 149597 240 8 la_data_out[48]
+port 343 nsew default tristate
+rlabel metal2 s 151289 -480 151345 240 8 la_data_out[49]
+port 344 nsew default tristate
+rlabel metal2 s 71019 -480 71075 240 8 la_data_out[4]
+port 345 nsew default tristate
+rlabel metal2 s 153083 -480 153139 240 8 la_data_out[50]
+port 346 nsew default tristate
+rlabel metal2 s 154877 -480 154933 240 8 la_data_out[51]
+port 347 nsew default tristate
+rlabel metal2 s 156671 -480 156727 240 8 la_data_out[52]
+port 348 nsew default tristate
+rlabel metal2 s 158465 -480 158521 240 8 la_data_out[53]
+port 349 nsew default tristate
+rlabel metal2 s 160213 -480 160269 240 8 la_data_out[54]
+port 350 nsew default tristate
+rlabel metal2 s 162007 -480 162063 240 8 la_data_out[55]
+port 351 nsew default tristate
+rlabel metal2 s 163801 -480 163857 240 8 la_data_out[56]
+port 352 nsew default tristate
+rlabel metal2 s 165595 -480 165651 240 8 la_data_out[57]
+port 353 nsew default tristate
+rlabel metal2 s 167343 -480 167399 240 8 la_data_out[58]
+port 354 nsew default tristate
+rlabel metal2 s 169137 -480 169193 240 8 la_data_out[59]
+port 355 nsew default tristate
+rlabel metal2 s 72813 -480 72869 240 8 la_data_out[5]
+port 356 nsew default tristate
+rlabel metal2 s 170931 -480 170987 240 8 la_data_out[60]
+port 357 nsew default tristate
+rlabel metal2 s 172725 -480 172781 240 8 la_data_out[61]
+port 358 nsew default tristate
+rlabel metal2 s 174519 -480 174575 240 8 la_data_out[62]
+port 359 nsew default tristate
+rlabel metal2 s 176267 -480 176323 240 8 la_data_out[63]
+port 360 nsew default tristate
+rlabel metal2 s 178061 -480 178117 240 8 la_data_out[64]
+port 361 nsew default tristate
+rlabel metal2 s 179855 -480 179911 240 8 la_data_out[65]
+port 362 nsew default tristate
+rlabel metal2 s 181649 -480 181705 240 8 la_data_out[66]
+port 363 nsew default tristate
+rlabel metal2 s 183443 -480 183499 240 8 la_data_out[67]
+port 364 nsew default tristate
+rlabel metal2 s 185191 -480 185247 240 8 la_data_out[68]
+port 365 nsew default tristate
+rlabel metal2 s 186985 -480 187041 240 8 la_data_out[69]
+port 366 nsew default tristate
+rlabel metal2 s 74607 -480 74663 240 8 la_data_out[6]
+port 367 nsew default tristate
+rlabel metal2 s 188779 -480 188835 240 8 la_data_out[70]
+port 368 nsew default tristate
+rlabel metal2 s 190573 -480 190629 240 8 la_data_out[71]
+port 369 nsew default tristate
+rlabel metal2 s 192321 -480 192377 240 8 la_data_out[72]
+port 370 nsew default tristate
+rlabel metal2 s 194115 -480 194171 240 8 la_data_out[73]
+port 371 nsew default tristate
+rlabel metal2 s 195909 -480 195965 240 8 la_data_out[74]
+port 372 nsew default tristate
+rlabel metal2 s 197703 -480 197759 240 8 la_data_out[75]
+port 373 nsew default tristate
+rlabel metal2 s 199497 -480 199553 240 8 la_data_out[76]
+port 374 nsew default tristate
+rlabel metal2 s 201245 -480 201301 240 8 la_data_out[77]
+port 375 nsew default tristate
+rlabel metal2 s 203039 -480 203095 240 8 la_data_out[78]
+port 376 nsew default tristate
+rlabel metal2 s 204833 -480 204889 240 8 la_data_out[79]
+port 377 nsew default tristate
+rlabel metal2 s 76355 -480 76411 240 8 la_data_out[7]
+port 378 nsew default tristate
+rlabel metal2 s 206627 -480 206683 240 8 la_data_out[80]
+port 379 nsew default tristate
+rlabel metal2 s 208421 -480 208477 240 8 la_data_out[81]
+port 380 nsew default tristate
+rlabel metal2 s 210169 -480 210225 240 8 la_data_out[82]
+port 381 nsew default tristate
+rlabel metal2 s 211963 -480 212019 240 8 la_data_out[83]
+port 382 nsew default tristate
+rlabel metal2 s 213757 -480 213813 240 8 la_data_out[84]
+port 383 nsew default tristate
+rlabel metal2 s 215551 -480 215607 240 8 la_data_out[85]
+port 384 nsew default tristate
+rlabel metal2 s 217299 -480 217355 240 8 la_data_out[86]
+port 385 nsew default tristate
+rlabel metal2 s 219093 -480 219149 240 8 la_data_out[87]
+port 386 nsew default tristate
+rlabel metal2 s 220887 -480 220943 240 8 la_data_out[88]
+port 387 nsew default tristate
+rlabel metal2 s 222681 -480 222737 240 8 la_data_out[89]
+port 388 nsew default tristate
+rlabel metal2 s 78149 -480 78205 240 8 la_data_out[8]
+port 389 nsew default tristate
+rlabel metal2 s 224475 -480 224531 240 8 la_data_out[90]
+port 390 nsew default tristate
+rlabel metal2 s 226223 -480 226279 240 8 la_data_out[91]
+port 391 nsew default tristate
+rlabel metal2 s 228017 -480 228073 240 8 la_data_out[92]
+port 392 nsew default tristate
+rlabel metal2 s 229811 -480 229867 240 8 la_data_out[93]
+port 393 nsew default tristate
+rlabel metal2 s 231605 -480 231661 240 8 la_data_out[94]
+port 394 nsew default tristate
+rlabel metal2 s 233399 -480 233455 240 8 la_data_out[95]
+port 395 nsew default tristate
+rlabel metal2 s 235147 -480 235203 240 8 la_data_out[96]
+port 396 nsew default tristate
+rlabel metal2 s 236941 -480 236997 240 8 la_data_out[97]
+port 397 nsew default tristate
+rlabel metal2 s 238735 -480 238791 240 8 la_data_out[98]
+port 398 nsew default tristate
+rlabel metal2 s 240529 -480 240585 240 8 la_data_out[99]
+port 399 nsew default tristate
+rlabel metal2 s 79943 -480 79999 240 8 la_data_out[9]
+port 400 nsew default tristate
+rlabel metal2 s 64487 -480 64543 240 8 la_oen[0]
+port 401 nsew default input
+rlabel metal2 s 242875 -480 242931 240 8 la_oen[100]
+port 402 nsew default input
+rlabel metal2 s 244669 -480 244725 240 8 la_oen[101]
+port 403 nsew default input
+rlabel metal2 s 246463 -480 246519 240 8 la_oen[102]
+port 404 nsew default input
+rlabel metal2 s 248257 -480 248313 240 8 la_oen[103]
+port 405 nsew default input
+rlabel metal2 s 250051 -480 250107 240 8 la_oen[104]
+port 406 nsew default input
+rlabel metal2 s 251799 -480 251855 240 8 la_oen[105]
+port 407 nsew default input
+rlabel metal2 s 253593 -480 253649 240 8 la_oen[106]
+port 408 nsew default input
+rlabel metal2 s 255387 -480 255443 240 8 la_oen[107]
+port 409 nsew default input
+rlabel metal2 s 257181 -480 257237 240 8 la_oen[108]
+port 410 nsew default input
+rlabel metal2 s 258929 -480 258985 240 8 la_oen[109]
+port 411 nsew default input
+rlabel metal2 s 82335 -480 82391 240 8 la_oen[10]
+port 412 nsew default input
+rlabel metal2 s 260723 -480 260779 240 8 la_oen[110]
+port 413 nsew default input
+rlabel metal2 s 262517 -480 262573 240 8 la_oen[111]
+port 414 nsew default input
+rlabel metal2 s 264311 -480 264367 240 8 la_oen[112]
+port 415 nsew default input
+rlabel metal2 s 266105 -480 266161 240 8 la_oen[113]
+port 416 nsew default input
+rlabel metal2 s 267853 -480 267909 240 8 la_oen[114]
+port 417 nsew default input
+rlabel metal2 s 269647 -480 269703 240 8 la_oen[115]
+port 418 nsew default input
+rlabel metal2 s 271441 -480 271497 240 8 la_oen[116]
+port 419 nsew default input
+rlabel metal2 s 273235 -480 273291 240 8 la_oen[117]
+port 420 nsew default input
+rlabel metal2 s 275029 -480 275085 240 8 la_oen[118]
+port 421 nsew default input
+rlabel metal2 s 276777 -480 276833 240 8 la_oen[119]
+port 422 nsew default input
+rlabel metal2 s 84083 -480 84139 240 8 la_oen[11]
+port 423 nsew default input
+rlabel metal2 s 278571 -480 278627 240 8 la_oen[120]
+port 424 nsew default input
+rlabel metal2 s 280365 -480 280421 240 8 la_oen[121]
+port 425 nsew default input
+rlabel metal2 s 282159 -480 282215 240 8 la_oen[122]
+port 426 nsew default input
+rlabel metal2 s 283907 -480 283963 240 8 la_oen[123]
+port 427 nsew default input
+rlabel metal2 s 285701 -480 285757 240 8 la_oen[124]
+port 428 nsew default input
+rlabel metal2 s 287495 -480 287551 240 8 la_oen[125]
+port 429 nsew default input
+rlabel metal2 s 289289 -480 289345 240 8 la_oen[126]
+port 430 nsew default input
+rlabel metal2 s 291083 -480 291139 240 8 la_oen[127]
+port 431 nsew default input
+rlabel metal2 s 85877 -480 85933 240 8 la_oen[12]
+port 432 nsew default input
+rlabel metal2 s 87671 -480 87727 240 8 la_oen[13]
+port 433 nsew default input
+rlabel metal2 s 89465 -480 89521 240 8 la_oen[14]
+port 434 nsew default input
+rlabel metal2 s 91259 -480 91315 240 8 la_oen[15]
+port 435 nsew default input
+rlabel metal2 s 93007 -480 93063 240 8 la_oen[16]
+port 436 nsew default input
+rlabel metal2 s 94801 -480 94857 240 8 la_oen[17]
+port 437 nsew default input
+rlabel metal2 s 96595 -480 96651 240 8 la_oen[18]
+port 438 nsew default input
+rlabel metal2 s 98389 -480 98445 240 8 la_oen[19]
+port 439 nsew default input
+rlabel metal2 s 66281 -480 66337 240 8 la_oen[1]
+port 440 nsew default input
+rlabel metal2 s 100183 -480 100239 240 8 la_oen[20]
+port 441 nsew default input
+rlabel metal2 s 101931 -480 101987 240 8 la_oen[21]
+port 442 nsew default input
+rlabel metal2 s 103725 -480 103781 240 8 la_oen[22]
+port 443 nsew default input
+rlabel metal2 s 105519 -480 105575 240 8 la_oen[23]
+port 444 nsew default input
+rlabel metal2 s 107313 -480 107369 240 8 la_oen[24]
+port 445 nsew default input
+rlabel metal2 s 109061 -480 109117 240 8 la_oen[25]
+port 446 nsew default input
+rlabel metal2 s 110855 -480 110911 240 8 la_oen[26]
+port 447 nsew default input
+rlabel metal2 s 112649 -480 112705 240 8 la_oen[27]
+port 448 nsew default input
+rlabel metal2 s 114443 -480 114499 240 8 la_oen[28]
+port 449 nsew default input
+rlabel metal2 s 116237 -480 116293 240 8 la_oen[29]
+port 450 nsew default input
+rlabel metal2 s 68029 -480 68085 240 8 la_oen[2]
+port 451 nsew default input
+rlabel metal2 s 117985 -480 118041 240 8 la_oen[30]
+port 452 nsew default input
+rlabel metal2 s 119779 -480 119835 240 8 la_oen[31]
+port 453 nsew default input
+rlabel metal2 s 121573 -480 121629 240 8 la_oen[32]
+port 454 nsew default input
+rlabel metal2 s 123367 -480 123423 240 8 la_oen[33]
+port 455 nsew default input
+rlabel metal2 s 125161 -480 125217 240 8 la_oen[34]
+port 456 nsew default input
+rlabel metal2 s 126909 -480 126965 240 8 la_oen[35]
+port 457 nsew default input
+rlabel metal2 s 128703 -480 128759 240 8 la_oen[36]
+port 458 nsew default input
+rlabel metal2 s 130497 -480 130553 240 8 la_oen[37]
+port 459 nsew default input
+rlabel metal2 s 132291 -480 132347 240 8 la_oen[38]
+port 460 nsew default input
+rlabel metal2 s 134039 -480 134095 240 8 la_oen[39]
+port 461 nsew default input
+rlabel metal2 s 69823 -480 69879 240 8 la_oen[3]
+port 462 nsew default input
+rlabel metal2 s 135833 -480 135889 240 8 la_oen[40]
+port 463 nsew default input
+rlabel metal2 s 137627 -480 137683 240 8 la_oen[41]
+port 464 nsew default input
+rlabel metal2 s 139421 -480 139477 240 8 la_oen[42]
+port 465 nsew default input
+rlabel metal2 s 141215 -480 141271 240 8 la_oen[43]
+port 466 nsew default input
+rlabel metal2 s 142963 -480 143019 240 8 la_oen[44]
+port 467 nsew default input
+rlabel metal2 s 144757 -480 144813 240 8 la_oen[45]
+port 468 nsew default input
+rlabel metal2 s 146551 -480 146607 240 8 la_oen[46]
+port 469 nsew default input
+rlabel metal2 s 148345 -480 148401 240 8 la_oen[47]
+port 470 nsew default input
+rlabel metal2 s 150139 -480 150195 240 8 la_oen[48]
+port 471 nsew default input
+rlabel metal2 s 151887 -480 151943 240 8 la_oen[49]
+port 472 nsew default input
+rlabel metal2 s 71617 -480 71673 240 8 la_oen[4]
+port 473 nsew default input
+rlabel metal2 s 153681 -480 153737 240 8 la_oen[50]
+port 474 nsew default input
+rlabel metal2 s 155475 -480 155531 240 8 la_oen[51]
+port 475 nsew default input
+rlabel metal2 s 157269 -480 157325 240 8 la_oen[52]
+port 476 nsew default input
+rlabel metal2 s 159017 -480 159073 240 8 la_oen[53]
+port 477 nsew default input
+rlabel metal2 s 160811 -480 160867 240 8 la_oen[54]
+port 478 nsew default input
+rlabel metal2 s 162605 -480 162661 240 8 la_oen[55]
+port 479 nsew default input
+rlabel metal2 s 164399 -480 164455 240 8 la_oen[56]
+port 480 nsew default input
+rlabel metal2 s 166193 -480 166249 240 8 la_oen[57]
+port 481 nsew default input
+rlabel metal2 s 167941 -480 167997 240 8 la_oen[58]
+port 482 nsew default input
+rlabel metal2 s 169735 -480 169791 240 8 la_oen[59]
+port 483 nsew default input
+rlabel metal2 s 73411 -480 73467 240 8 la_oen[5]
+port 484 nsew default input
+rlabel metal2 s 171529 -480 171585 240 8 la_oen[60]
+port 485 nsew default input
+rlabel metal2 s 173323 -480 173379 240 8 la_oen[61]
+port 486 nsew default input
+rlabel metal2 s 175117 -480 175173 240 8 la_oen[62]
+port 487 nsew default input
+rlabel metal2 s 176865 -480 176921 240 8 la_oen[63]
+port 488 nsew default input
+rlabel metal2 s 178659 -480 178715 240 8 la_oen[64]
+port 489 nsew default input
+rlabel metal2 s 180453 -480 180509 240 8 la_oen[65]
+port 490 nsew default input
+rlabel metal2 s 182247 -480 182303 240 8 la_oen[66]
+port 491 nsew default input
+rlabel metal2 s 183995 -480 184051 240 8 la_oen[67]
+port 492 nsew default input
+rlabel metal2 s 185789 -480 185845 240 8 la_oen[68]
+port 493 nsew default input
+rlabel metal2 s 187583 -480 187639 240 8 la_oen[69]
+port 494 nsew default input
+rlabel metal2 s 75205 -480 75261 240 8 la_oen[6]
+port 495 nsew default input
+rlabel metal2 s 189377 -480 189433 240 8 la_oen[70]
+port 496 nsew default input
+rlabel metal2 s 191171 -480 191227 240 8 la_oen[71]
+port 497 nsew default input
+rlabel metal2 s 192919 -480 192975 240 8 la_oen[72]
+port 498 nsew default input
+rlabel metal2 s 194713 -480 194769 240 8 la_oen[73]
+port 499 nsew default input
+rlabel metal2 s 196507 -480 196563 240 8 la_oen[74]
+port 500 nsew default input
+rlabel metal2 s 198301 -480 198357 240 8 la_oen[75]
+port 501 nsew default input
+rlabel metal2 s 200095 -480 200151 240 8 la_oen[76]
+port 502 nsew default input
+rlabel metal2 s 201843 -480 201899 240 8 la_oen[77]
+port 503 nsew default input
+rlabel metal2 s 203637 -480 203693 240 8 la_oen[78]
+port 504 nsew default input
+rlabel metal2 s 205431 -480 205487 240 8 la_oen[79]
+port 505 nsew default input
+rlabel metal2 s 76953 -480 77009 240 8 la_oen[7]
+port 506 nsew default input
+rlabel metal2 s 207225 -480 207281 240 8 la_oen[80]
+port 507 nsew default input
+rlabel metal2 s 208973 -480 209029 240 8 la_oen[81]
+port 508 nsew default input
+rlabel metal2 s 210767 -480 210823 240 8 la_oen[82]
+port 509 nsew default input
+rlabel metal2 s 212561 -480 212617 240 8 la_oen[83]
+port 510 nsew default input
+rlabel metal2 s 214355 -480 214411 240 8 la_oen[84]
+port 511 nsew default input
+rlabel metal2 s 216149 -480 216205 240 8 la_oen[85]
+port 512 nsew default input
+rlabel metal2 s 217897 -480 217953 240 8 la_oen[86]
+port 513 nsew default input
+rlabel metal2 s 219691 -480 219747 240 8 la_oen[87]
+port 514 nsew default input
+rlabel metal2 s 221485 -480 221541 240 8 la_oen[88]
+port 515 nsew default input
+rlabel metal2 s 223279 -480 223335 240 8 la_oen[89]
+port 516 nsew default input
+rlabel metal2 s 78747 -480 78803 240 8 la_oen[8]
+port 517 nsew default input
+rlabel metal2 s 225073 -480 225129 240 8 la_oen[90]
+port 518 nsew default input
+rlabel metal2 s 226821 -480 226877 240 8 la_oen[91]
+port 519 nsew default input
+rlabel metal2 s 228615 -480 228671 240 8 la_oen[92]
+port 520 nsew default input
+rlabel metal2 s 230409 -480 230465 240 8 la_oen[93]
+port 521 nsew default input
+rlabel metal2 s 232203 -480 232259 240 8 la_oen[94]
+port 522 nsew default input
+rlabel metal2 s 233951 -480 234007 240 8 la_oen[95]
+port 523 nsew default input
+rlabel metal2 s 235745 -480 235801 240 8 la_oen[96]
+port 524 nsew default input
+rlabel metal2 s 237539 -480 237595 240 8 la_oen[97]
+port 525 nsew default input
+rlabel metal2 s 239333 -480 239389 240 8 la_oen[98]
+port 526 nsew default input
+rlabel metal2 s 241127 -480 241183 240 8 la_oen[99]
+port 527 nsew default input
+rlabel metal2 s 80541 -480 80597 240 8 la_oen[9]
+port 528 nsew default input
+rlabel metal2 s 291681 -480 291737 240 8 user_clock2
+port 529 nsew default input
+rlabel metal2 s 271 -480 327 240 8 wb_clk_i
+port 530 nsew default input
+rlabel metal2 s 823 -480 879 240 8 wb_rst_i
+port 531 nsew default input
+rlabel metal2 s 1421 -480 1477 240 8 wbs_ack_o
+port 532 nsew default tristate
+rlabel metal2 s 3813 -480 3869 240 8 wbs_adr_i[0]
+port 533 nsew default input
+rlabel metal2 s 24053 -480 24109 240 8 wbs_adr_i[10]
+port 534 nsew default input
+rlabel metal2 s 25801 -480 25857 240 8 wbs_adr_i[11]
+port 535 nsew default input
+rlabel metal2 s 27595 -480 27651 240 8 wbs_adr_i[12]
+port 536 nsew default input
+rlabel metal2 s 29389 -480 29445 240 8 wbs_adr_i[13]
+port 537 nsew default input
+rlabel metal2 s 31183 -480 31239 240 8 wbs_adr_i[14]
+port 538 nsew default input
+rlabel metal2 s 32977 -480 33033 240 8 wbs_adr_i[15]
+port 539 nsew default input
+rlabel metal2 s 34725 -480 34781 240 8 wbs_adr_i[16]
+port 540 nsew default input
+rlabel metal2 s 36519 -480 36575 240 8 wbs_adr_i[17]
+port 541 nsew default input
+rlabel metal2 s 38313 -480 38369 240 8 wbs_adr_i[18]
+port 542 nsew default input
+rlabel metal2 s 40107 -480 40163 240 8 wbs_adr_i[19]
+port 543 nsew default input
+rlabel metal2 s 6205 -480 6261 240 8 wbs_adr_i[1]
+port 544 nsew default input
+rlabel metal2 s 41901 -480 41957 240 8 wbs_adr_i[20]
+port 545 nsew default input
+rlabel metal2 s 43649 -480 43705 240 8 wbs_adr_i[21]
+port 546 nsew default input
+rlabel metal2 s 45443 -480 45499 240 8 wbs_adr_i[22]
+port 547 nsew default input
+rlabel metal2 s 47237 -480 47293 240 8 wbs_adr_i[23]
+port 548 nsew default input
+rlabel metal2 s 49031 -480 49087 240 8 wbs_adr_i[24]
+port 549 nsew default input
+rlabel metal2 s 50779 -480 50835 240 8 wbs_adr_i[25]
+port 550 nsew default input
+rlabel metal2 s 52573 -480 52629 240 8 wbs_adr_i[26]
+port 551 nsew default input
+rlabel metal2 s 54367 -480 54423 240 8 wbs_adr_i[27]
+port 552 nsew default input
+rlabel metal2 s 56161 -480 56217 240 8 wbs_adr_i[28]
+port 553 nsew default input
+rlabel metal2 s 57955 -480 58011 240 8 wbs_adr_i[29]
+port 554 nsew default input
+rlabel metal2 s 8597 -480 8653 240 8 wbs_adr_i[2]
+port 555 nsew default input
+rlabel metal2 s 59703 -480 59759 240 8 wbs_adr_i[30]
+port 556 nsew default input
+rlabel metal2 s 61497 -480 61553 240 8 wbs_adr_i[31]
+port 557 nsew default input
+rlabel metal2 s 10943 -480 10999 240 8 wbs_adr_i[3]
+port 558 nsew default input
+rlabel metal2 s 13335 -480 13391 240 8 wbs_adr_i[4]
+port 559 nsew default input
+rlabel metal2 s 15129 -480 15185 240 8 wbs_adr_i[5]
+port 560 nsew default input
+rlabel metal2 s 16923 -480 16979 240 8 wbs_adr_i[6]
+port 561 nsew default input
+rlabel metal2 s 18671 -480 18727 240 8 wbs_adr_i[7]
+port 562 nsew default input
+rlabel metal2 s 20465 -480 20521 240 8 wbs_adr_i[8]
+port 563 nsew default input
+rlabel metal2 s 22259 -480 22315 240 8 wbs_adr_i[9]
+port 564 nsew default input
+rlabel metal2 s 2019 -480 2075 240 8 wbs_cyc_i
+port 565 nsew default input
+rlabel metal2 s 4411 -480 4467 240 8 wbs_dat_i[0]
+port 566 nsew default input
+rlabel metal2 s 24651 -480 24707 240 8 wbs_dat_i[10]
+port 567 nsew default input
+rlabel metal2 s 26399 -480 26455 240 8 wbs_dat_i[11]
+port 568 nsew default input
+rlabel metal2 s 28193 -480 28249 240 8 wbs_dat_i[12]
+port 569 nsew default input
+rlabel metal2 s 29987 -480 30043 240 8 wbs_dat_i[13]
+port 570 nsew default input
+rlabel metal2 s 31781 -480 31837 240 8 wbs_dat_i[14]
+port 571 nsew default input
+rlabel metal2 s 33575 -480 33631 240 8 wbs_dat_i[15]
+port 572 nsew default input
+rlabel metal2 s 35323 -480 35379 240 8 wbs_dat_i[16]
+port 573 nsew default input
+rlabel metal2 s 37117 -480 37173 240 8 wbs_dat_i[17]
+port 574 nsew default input
+rlabel metal2 s 38911 -480 38967 240 8 wbs_dat_i[18]
+port 575 nsew default input
+rlabel metal2 s 40705 -480 40761 240 8 wbs_dat_i[19]
+port 576 nsew default input
+rlabel metal2 s 6803 -480 6859 240 8 wbs_dat_i[1]
+port 577 nsew default input
+rlabel metal2 s 42453 -480 42509 240 8 wbs_dat_i[20]
+port 578 nsew default input
+rlabel metal2 s 44247 -480 44303 240 8 wbs_dat_i[21]
+port 579 nsew default input
+rlabel metal2 s 46041 -480 46097 240 8 wbs_dat_i[22]
+port 580 nsew default input
+rlabel metal2 s 47835 -480 47891 240 8 wbs_dat_i[23]
+port 581 nsew default input
+rlabel metal2 s 49629 -480 49685 240 8 wbs_dat_i[24]
+port 582 nsew default input
+rlabel metal2 s 51377 -480 51433 240 8 wbs_dat_i[25]
+port 583 nsew default input
+rlabel metal2 s 53171 -480 53227 240 8 wbs_dat_i[26]
+port 584 nsew default input
+rlabel metal2 s 54965 -480 55021 240 8 wbs_dat_i[27]
+port 585 nsew default input
+rlabel metal2 s 56759 -480 56815 240 8 wbs_dat_i[28]
+port 586 nsew default input
+rlabel metal2 s 58553 -480 58609 240 8 wbs_dat_i[29]
+port 587 nsew default input
+rlabel metal2 s 9149 -480 9205 240 8 wbs_dat_i[2]
+port 588 nsew default input
+rlabel metal2 s 60301 -480 60357 240 8 wbs_dat_i[30]
+port 589 nsew default input
+rlabel metal2 s 62095 -480 62151 240 8 wbs_dat_i[31]
+port 590 nsew default input
+rlabel metal2 s 11541 -480 11597 240 8 wbs_dat_i[3]
+port 591 nsew default input
+rlabel metal2 s 13933 -480 13989 240 8 wbs_dat_i[4]
+port 592 nsew default input
+rlabel metal2 s 15727 -480 15783 240 8 wbs_dat_i[5]
+port 593 nsew default input
+rlabel metal2 s 17475 -480 17531 240 8 wbs_dat_i[6]
+port 594 nsew default input
+rlabel metal2 s 19269 -480 19325 240 8 wbs_dat_i[7]
+port 595 nsew default input
+rlabel metal2 s 21063 -480 21119 240 8 wbs_dat_i[8]
+port 596 nsew default input
+rlabel metal2 s 22857 -480 22913 240 8 wbs_dat_i[9]
+port 597 nsew default input
+rlabel metal2 s 5009 -480 5065 240 8 wbs_dat_o[0]
+port 598 nsew default tristate
+rlabel metal2 s 25249 -480 25305 240 8 wbs_dat_o[10]
+port 599 nsew default tristate
+rlabel metal2 s 26997 -480 27053 240 8 wbs_dat_o[11]
+port 600 nsew default tristate
+rlabel metal2 s 28791 -480 28847 240 8 wbs_dat_o[12]
+port 601 nsew default tristate
+rlabel metal2 s 30585 -480 30641 240 8 wbs_dat_o[13]
+port 602 nsew default tristate
+rlabel metal2 s 32379 -480 32435 240 8 wbs_dat_o[14]
+port 603 nsew default tristate
+rlabel metal2 s 34127 -480 34183 240 8 wbs_dat_o[15]
+port 604 nsew default tristate
+rlabel metal2 s 35921 -480 35977 240 8 wbs_dat_o[16]
+port 605 nsew default tristate
+rlabel metal2 s 37715 -480 37771 240 8 wbs_dat_o[17]
+port 606 nsew default tristate
+rlabel metal2 s 39509 -480 39565 240 8 wbs_dat_o[18]
+port 607 nsew default tristate
+rlabel metal2 s 41303 -480 41359 240 8 wbs_dat_o[19]
+port 608 nsew default tristate
+rlabel metal2 s 7401 -480 7457 240 8 wbs_dat_o[1]
+port 609 nsew default tristate
+rlabel metal2 s 43051 -480 43107 240 8 wbs_dat_o[20]
+port 610 nsew default tristate
+rlabel metal2 s 44845 -480 44901 240 8 wbs_dat_o[21]
+port 611 nsew default tristate
+rlabel metal2 s 46639 -480 46695 240 8 wbs_dat_o[22]
+port 612 nsew default tristate
+rlabel metal2 s 48433 -480 48489 240 8 wbs_dat_o[23]
+port 613 nsew default tristate
+rlabel metal2 s 50227 -480 50283 240 8 wbs_dat_o[24]
+port 614 nsew default tristate
+rlabel metal2 s 51975 -480 52031 240 8 wbs_dat_o[25]
+port 615 nsew default tristate
+rlabel metal2 s 53769 -480 53825 240 8 wbs_dat_o[26]
+port 616 nsew default tristate
+rlabel metal2 s 55563 -480 55619 240 8 wbs_dat_o[27]
+port 617 nsew default tristate
+rlabel metal2 s 57357 -480 57413 240 8 wbs_dat_o[28]
+port 618 nsew default tristate
+rlabel metal2 s 59105 -480 59161 240 8 wbs_dat_o[29]
+port 619 nsew default tristate
+rlabel metal2 s 9747 -480 9803 240 8 wbs_dat_o[2]
+port 620 nsew default tristate
+rlabel metal2 s 60899 -480 60955 240 8 wbs_dat_o[30]
+port 621 nsew default tristate
+rlabel metal2 s 62693 -480 62749 240 8 wbs_dat_o[31]
+port 622 nsew default tristate
+rlabel metal2 s 12139 -480 12195 240 8 wbs_dat_o[3]
+port 623 nsew default tristate
+rlabel metal2 s 14531 -480 14587 240 8 wbs_dat_o[4]
+port 624 nsew default tristate
+rlabel metal2 s 16325 -480 16381 240 8 wbs_dat_o[5]
+port 625 nsew default tristate
+rlabel metal2 s 18073 -480 18129 240 8 wbs_dat_o[6]
+port 626 nsew default tristate
+rlabel metal2 s 19867 -480 19923 240 8 wbs_dat_o[7]
+port 627 nsew default tristate
+rlabel metal2 s 21661 -480 21717 240 8 wbs_dat_o[8]
+port 628 nsew default tristate
+rlabel metal2 s 23455 -480 23511 240 8 wbs_dat_o[9]
+port 629 nsew default tristate
+rlabel metal2 s 5607 -480 5663 240 8 wbs_sel_i[0]
+port 630 nsew default input
+rlabel metal2 s 7999 -480 8055 240 8 wbs_sel_i[1]
+port 631 nsew default input
+rlabel metal2 s 10345 -480 10401 240 8 wbs_sel_i[2]
+port 632 nsew default input
+rlabel metal2 s 12737 -480 12793 240 8 wbs_sel_i[3]
+port 633 nsew default input
+rlabel metal2 s 2617 -480 2673 240 8 wbs_stb_i
+port 634 nsew default input
+rlabel metal2 s 3215 -480 3271 240 8 wbs_we_i
+port 635 nsew default input
+rlabel metal4 s 288402 351760 288702 352900 6 vccd1
+port 636 nsew default input
+rlabel metal4 s 270402 351760 270702 352900 6 vccd1
+port 637 nsew default input
+rlabel metal4 s 252402 351760 252702 352900 6 vccd1
+port 638 nsew default input
+rlabel metal4 s 234402 351760 234702 352900 6 vccd1
+port 639 nsew default input
+rlabel metal4 s 216402 351760 216702 352900 6 vccd1
+port 640 nsew default input
+rlabel metal4 s 198402 351760 198702 352900 6 vccd1
+port 641 nsew default input
+rlabel metal4 s 180402 351760 180702 352900 6 vccd1
+port 642 nsew default input
+rlabel metal4 s 162402 351760 162702 352900 6 vccd1
+port 643 nsew default input
+rlabel metal4 s 144402 351760 144702 352900 6 vccd1
+port 644 nsew default input
+rlabel metal4 s 126402 351760 126702 352900 6 vccd1
+port 645 nsew default input
+rlabel metal4 s 108402 351760 108702 352900 6 vccd1
+port 646 nsew default input
+rlabel metal4 s 90402 351760 90702 352900 6 vccd1
+port 647 nsew default input
+rlabel metal4 s 72402 351760 72702 352900 6 vccd1
+port 648 nsew default input
+rlabel metal4 s 54402 351760 54702 352900 6 vccd1
+port 649 nsew default input
+rlabel metal4 s 36402 351760 36702 352900 6 vccd1
+port 650 nsew default input
+rlabel metal4 s 18402 351760 18702 352900 6 vccd1
+port 651 nsew default input
+rlabel metal4 s 402 351760 702 352900 6 vccd1
+port 652 nsew default input
+rlabel metal4 s 292660 -462 292960 352430 6 vccd1
+port 653 nsew default input
+rlabel metal4 s -998 -462 -698 352430 4 vccd1
+port 654 nsew default input
+rlabel metal4 s 288402 -932 288702 240 8 vccd1
+port 655 nsew default input
+rlabel metal4 s 270402 -932 270702 240 8 vccd1
+port 656 nsew default input
+rlabel metal4 s 252402 -932 252702 240 8 vccd1
+port 657 nsew default input
+rlabel metal4 s 234402 -932 234702 240 8 vccd1
+port 658 nsew default input
+rlabel metal4 s 216402 -932 216702 240 8 vccd1
+port 659 nsew default input
+rlabel metal4 s 198402 -932 198702 240 8 vccd1
+port 660 nsew default input
+rlabel metal4 s 180402 -932 180702 240 8 vccd1
+port 661 nsew default input
+rlabel metal4 s 162402 -932 162702 240 8 vccd1
+port 662 nsew default input
+rlabel metal4 s 144402 -932 144702 240 8 vccd1
+port 663 nsew default input
+rlabel metal4 s 126402 -932 126702 240 8 vccd1
+port 664 nsew default input
+rlabel metal4 s 108402 -932 108702 240 8 vccd1
+port 665 nsew default input
+rlabel metal4 s 90402 -932 90702 240 8 vccd1
+port 666 nsew default input
+rlabel metal4 s 72402 -932 72702 240 8 vccd1
+port 667 nsew default input
+rlabel metal4 s 54402 -932 54702 240 8 vccd1
+port 668 nsew default input
+rlabel metal4 s 36402 -932 36702 240 8 vccd1
+port 669 nsew default input
+rlabel metal4 s 18402 -932 18702 240 8 vccd1
+port 670 nsew default input
+rlabel metal4 s 402 -932 702 240 8 vccd1
+port 671 nsew default input
+rlabel metal5 s -998 352130 292960 352430 6 vccd1
+port 672 nsew default input
+rlabel metal5 s 291760 342938 293430 343238 6 vccd1
+port 673 nsew default input
+rlabel metal5 s -1468 342938 240 343238 4 vccd1
+port 674 nsew default input
+rlabel metal5 s 291760 324938 293430 325238 6 vccd1
+port 675 nsew default input
+rlabel metal5 s -1468 324938 240 325238 4 vccd1
+port 676 nsew default input
+rlabel metal5 s 291760 306938 293430 307238 6 vccd1
+port 677 nsew default input
+rlabel metal5 s -1468 306938 240 307238 4 vccd1
+port 678 nsew default input
+rlabel metal5 s 291760 288938 293430 289238 6 vccd1
+port 679 nsew default input
+rlabel metal5 s -1468 288938 240 289238 4 vccd1
+port 680 nsew default input
+rlabel metal5 s 291760 270938 293430 271238 6 vccd1
+port 681 nsew default input
+rlabel metal5 s -1468 270938 240 271238 4 vccd1
+port 682 nsew default input
+rlabel metal5 s 291760 252938 293430 253238 6 vccd1
+port 683 nsew default input
+rlabel metal5 s -1468 252938 240 253238 4 vccd1
+port 684 nsew default input
+rlabel metal5 s 291760 234938 293430 235238 6 vccd1
+port 685 nsew default input
+rlabel metal5 s -1468 234938 240 235238 4 vccd1
+port 686 nsew default input
+rlabel metal5 s 291760 216938 293430 217238 6 vccd1
+port 687 nsew default input
+rlabel metal5 s -1468 216938 240 217238 4 vccd1
+port 688 nsew default input
+rlabel metal5 s 291760 198938 293430 199238 6 vccd1
+port 689 nsew default input
+rlabel metal5 s -1468 198938 240 199238 4 vccd1
+port 690 nsew default input
+rlabel metal5 s 291760 180938 293430 181238 6 vccd1
+port 691 nsew default input
+rlabel metal5 s -1468 180938 240 181238 4 vccd1
+port 692 nsew default input
+rlabel metal5 s 291760 162938 293430 163238 6 vccd1
+port 693 nsew default input
+rlabel metal5 s -1468 162938 240 163238 4 vccd1
+port 694 nsew default input
+rlabel metal5 s 291760 144938 293430 145238 6 vccd1
+port 695 nsew default input
+rlabel metal5 s -1468 144938 240 145238 4 vccd1
+port 696 nsew default input
+rlabel metal5 s 291760 126938 293430 127238 6 vccd1
+port 697 nsew default input
+rlabel metal5 s -1468 126938 240 127238 4 vccd1
+port 698 nsew default input
+rlabel metal5 s 291760 108938 293430 109238 6 vccd1
+port 699 nsew default input
+rlabel metal5 s -1468 108938 240 109238 4 vccd1
+port 700 nsew default input
+rlabel metal5 s 291760 90938 293430 91238 6 vccd1
+port 701 nsew default input
+rlabel metal5 s -1468 90938 240 91238 4 vccd1
+port 702 nsew default input
+rlabel metal5 s 291760 72938 293430 73238 6 vccd1
+port 703 nsew default input
+rlabel metal5 s -1468 72938 240 73238 4 vccd1
+port 704 nsew default input
+rlabel metal5 s 291760 54938 293430 55238 6 vccd1
+port 705 nsew default input
+rlabel metal5 s -1468 54938 240 55238 4 vccd1
+port 706 nsew default input
+rlabel metal5 s 291760 36938 293430 37238 6 vccd1
+port 707 nsew default input
+rlabel metal5 s -1468 36938 240 37238 4 vccd1
+port 708 nsew default input
+rlabel metal5 s 291760 18938 293430 19238 6 vccd1
+port 709 nsew default input
+rlabel metal5 s -1468 18938 240 19238 4 vccd1
+port 710 nsew default input
+rlabel metal5 s 291760 938 293430 1238 6 vccd1
+port 711 nsew default input
+rlabel metal5 s -1468 938 240 1238 4 vccd1
+port 712 nsew default input
+rlabel metal5 s -998 -462 292960 -162 8 vccd1
+port 713 nsew default input
+rlabel metal4 s 293130 -932 293430 352900 6 vssd1
+port 714 nsew default input
+rlabel metal4 s 279402 351760 279702 352900 6 vssd1
+port 715 nsew default input
+rlabel metal4 s 261402 351760 261702 352900 6 vssd1
+port 716 nsew default input
+rlabel metal4 s 243402 351760 243702 352900 6 vssd1
+port 717 nsew default input
+rlabel metal4 s 225402 351760 225702 352900 6 vssd1
+port 718 nsew default input
+rlabel metal4 s 207402 351760 207702 352900 6 vssd1
+port 719 nsew default input
+rlabel metal4 s 189402 351760 189702 352900 6 vssd1
+port 720 nsew default input
+rlabel metal4 s 171402 351760 171702 352900 6 vssd1
+port 721 nsew default input
+rlabel metal4 s 153402 351760 153702 352900 6 vssd1
+port 722 nsew default input
+rlabel metal4 s 135402 351760 135702 352900 6 vssd1
+port 723 nsew default input
+rlabel metal4 s 117402 351760 117702 352900 6 vssd1
+port 724 nsew default input
+rlabel metal4 s 99402 351760 99702 352900 6 vssd1
+port 725 nsew default input
+rlabel metal4 s 81402 351760 81702 352900 6 vssd1
+port 726 nsew default input
+rlabel metal4 s 63402 351760 63702 352900 6 vssd1
+port 727 nsew default input
+rlabel metal4 s 45402 351760 45702 352900 6 vssd1
+port 728 nsew default input
+rlabel metal4 s 27402 351760 27702 352900 6 vssd1
+port 729 nsew default input
+rlabel metal4 s 9402 351760 9702 352900 6 vssd1
+port 730 nsew default input
+rlabel metal4 s -1468 -932 -1168 352900 4 vssd1
+port 731 nsew default input
+rlabel metal4 s 279402 -932 279702 240 8 vssd1
+port 732 nsew default input
+rlabel metal4 s 261402 -932 261702 240 8 vssd1
+port 733 nsew default input
+rlabel metal4 s 243402 -932 243702 240 8 vssd1
+port 734 nsew default input
+rlabel metal4 s 225402 -932 225702 240 8 vssd1
+port 735 nsew default input
+rlabel metal4 s 207402 -932 207702 240 8 vssd1
+port 736 nsew default input
+rlabel metal4 s 189402 -932 189702 240 8 vssd1
+port 737 nsew default input
+rlabel metal4 s 171402 -932 171702 240 8 vssd1
+port 738 nsew default input
+rlabel metal4 s 153402 -932 153702 240 8 vssd1
+port 739 nsew default input
+rlabel metal4 s 135402 -932 135702 240 8 vssd1
+port 740 nsew default input
+rlabel metal4 s 117402 -932 117702 240 8 vssd1
+port 741 nsew default input
+rlabel metal4 s 99402 -932 99702 240 8 vssd1
+port 742 nsew default input
+rlabel metal4 s 81402 -932 81702 240 8 vssd1
+port 743 nsew default input
+rlabel metal4 s 63402 -932 63702 240 8 vssd1
+port 744 nsew default input
+rlabel metal4 s 45402 -932 45702 240 8 vssd1
+port 745 nsew default input
+rlabel metal4 s 27402 -932 27702 240 8 vssd1
+port 746 nsew default input
+rlabel metal4 s 9402 -932 9702 240 8 vssd1
+port 747 nsew default input
+rlabel metal5 s -1468 352600 293430 352900 6 vssd1
+port 748 nsew default input
+rlabel metal5 s 291760 333938 293430 334238 6 vssd1
+port 749 nsew default input
+rlabel metal5 s -1468 333938 240 334238 4 vssd1
+port 750 nsew default input
+rlabel metal5 s 291760 315938 293430 316238 6 vssd1
+port 751 nsew default input
+rlabel metal5 s -1468 315938 240 316238 4 vssd1
+port 752 nsew default input
+rlabel metal5 s 291760 297938 293430 298238 6 vssd1
+port 753 nsew default input
+rlabel metal5 s -1468 297938 240 298238 4 vssd1
+port 754 nsew default input
+rlabel metal5 s 291760 279938 293430 280238 6 vssd1
+port 755 nsew default input
+rlabel metal5 s -1468 279938 240 280238 4 vssd1
+port 756 nsew default input
+rlabel metal5 s 291760 261938 293430 262238 6 vssd1
+port 757 nsew default input
+rlabel metal5 s -1468 261938 240 262238 4 vssd1
+port 758 nsew default input
+rlabel metal5 s 291760 243938 293430 244238 6 vssd1
+port 759 nsew default input
+rlabel metal5 s -1468 243938 240 244238 4 vssd1
+port 760 nsew default input
+rlabel metal5 s 291760 225938 293430 226238 6 vssd1
+port 761 nsew default input
+rlabel metal5 s -1468 225938 240 226238 4 vssd1
+port 762 nsew default input
+rlabel metal5 s 291760 207938 293430 208238 6 vssd1
+port 763 nsew default input
+rlabel metal5 s -1468 207938 240 208238 4 vssd1
+port 764 nsew default input
+rlabel metal5 s 291760 189938 293430 190238 6 vssd1
+port 765 nsew default input
+rlabel metal5 s -1468 189938 240 190238 4 vssd1
+port 766 nsew default input
+rlabel metal5 s 291760 171938 293430 172238 6 vssd1
+port 767 nsew default input
+rlabel metal5 s -1468 171938 240 172238 4 vssd1
+port 768 nsew default input
+rlabel metal5 s 291760 153938 293430 154238 6 vssd1
+port 769 nsew default input
+rlabel metal5 s -1468 153938 240 154238 4 vssd1
+port 770 nsew default input
+rlabel metal5 s 291760 135938 293430 136238 6 vssd1
+port 771 nsew default input
+rlabel metal5 s -1468 135938 240 136238 4 vssd1
+port 772 nsew default input
+rlabel metal5 s 291760 117938 293430 118238 6 vssd1
+port 773 nsew default input
+rlabel metal5 s -1468 117938 240 118238 4 vssd1
+port 774 nsew default input
+rlabel metal5 s 291760 99938 293430 100238 6 vssd1
+port 775 nsew default input
+rlabel metal5 s -1468 99938 240 100238 4 vssd1
+port 776 nsew default input
+rlabel metal5 s 291760 81938 293430 82238 6 vssd1
+port 777 nsew default input
+rlabel metal5 s -1468 81938 240 82238 4 vssd1
+port 778 nsew default input
+rlabel metal5 s 291760 63938 293430 64238 6 vssd1
+port 779 nsew default input
+rlabel metal5 s -1468 63938 240 64238 4 vssd1
+port 780 nsew default input
+rlabel metal5 s 291760 45938 293430 46238 6 vssd1
+port 781 nsew default input
+rlabel metal5 s -1468 45938 240 46238 4 vssd1
+port 782 nsew default input
+rlabel metal5 s 291760 27938 293430 28238 6 vssd1
+port 783 nsew default input
+rlabel metal5 s -1468 27938 240 28238 4 vssd1
+port 784 nsew default input
+rlabel metal5 s 291760 9938 293430 10238 6 vssd1
+port 785 nsew default input
+rlabel metal5 s -1468 9938 240 10238 4 vssd1
+port 786 nsew default input
+rlabel metal5 s -1468 -932 293430 -632 8 vssd1
+port 787 nsew default input
+rlabel metal4 s 290202 351760 290502 353840 6 vccd2
+port 788 nsew default input
+rlabel metal4 s 272202 351760 272502 353840 6 vccd2
+port 789 nsew default input
+rlabel metal4 s 254202 351760 254502 353840 6 vccd2
+port 790 nsew default input
+rlabel metal4 s 236202 351760 236502 353840 6 vccd2
+port 791 nsew default input
+rlabel metal4 s 218202 351760 218502 353840 6 vccd2
+port 792 nsew default input
+rlabel metal4 s 200202 351760 200502 353840 6 vccd2
+port 793 nsew default input
+rlabel metal4 s 182202 351760 182502 353840 6 vccd2
+port 794 nsew default input
+rlabel metal4 s 164202 351760 164502 353840 6 vccd2
+port 795 nsew default input
+rlabel metal4 s 146202 351760 146502 353840 6 vccd2
+port 796 nsew default input
+rlabel metal4 s 128202 351760 128502 353840 6 vccd2
+port 797 nsew default input
+rlabel metal4 s 110202 351760 110502 353840 6 vccd2
+port 798 nsew default input
+rlabel metal4 s 92202 351760 92502 353840 6 vccd2
+port 799 nsew default input
+rlabel metal4 s 74202 351760 74502 353840 6 vccd2
+port 800 nsew default input
+rlabel metal4 s 56202 351760 56502 353840 6 vccd2
+port 801 nsew default input
+rlabel metal4 s 38202 351760 38502 353840 6 vccd2
+port 802 nsew default input
+rlabel metal4 s 20202 351760 20502 353840 6 vccd2
+port 803 nsew default input
+rlabel metal4 s 2202 351760 2502 353840 6 vccd2
+port 804 nsew default input
+rlabel metal4 s 293600 -1402 293900 353370 6 vccd2
+port 805 nsew default input
+rlabel metal4 s -1938 -1402 -1638 353370 4 vccd2
+port 806 nsew default input
+rlabel metal4 s 290202 -1872 290502 240 8 vccd2
+port 807 nsew default input
+rlabel metal4 s 272202 -1872 272502 240 8 vccd2
+port 808 nsew default input
+rlabel metal4 s 254202 -1872 254502 240 8 vccd2
+port 809 nsew default input
+rlabel metal4 s 236202 -1872 236502 240 8 vccd2
+port 810 nsew default input
+rlabel metal4 s 218202 -1872 218502 240 8 vccd2
+port 811 nsew default input
+rlabel metal4 s 200202 -1872 200502 240 8 vccd2
+port 812 nsew default input
+rlabel metal4 s 182202 -1872 182502 240 8 vccd2
+port 813 nsew default input
+rlabel metal4 s 164202 -1872 164502 240 8 vccd2
+port 814 nsew default input
+rlabel metal4 s 146202 -1872 146502 240 8 vccd2
+port 815 nsew default input
+rlabel metal4 s 128202 -1872 128502 240 8 vccd2
+port 816 nsew default input
+rlabel metal4 s 110202 -1872 110502 240 8 vccd2
+port 817 nsew default input
+rlabel metal4 s 92202 -1872 92502 240 8 vccd2
+port 818 nsew default input
+rlabel metal4 s 74202 -1872 74502 240 8 vccd2
+port 819 nsew default input
+rlabel metal4 s 56202 -1872 56502 240 8 vccd2
+port 820 nsew default input
+rlabel metal4 s 38202 -1872 38502 240 8 vccd2
+port 821 nsew default input
+rlabel metal4 s 20202 -1872 20502 240 8 vccd2
+port 822 nsew default input
+rlabel metal4 s 2202 -1872 2502 240 8 vccd2
+port 823 nsew default input
+rlabel metal5 s -1938 353070 293900 353370 6 vccd2
+port 824 nsew default input
+rlabel metal5 s 291760 344738 294370 345038 6 vccd2
+port 825 nsew default input
+rlabel metal5 s -2408 344738 240 345038 4 vccd2
+port 826 nsew default input
+rlabel metal5 s 291760 326738 294370 327038 6 vccd2
+port 827 nsew default input
+rlabel metal5 s -2408 326738 240 327038 4 vccd2
+port 828 nsew default input
+rlabel metal5 s 291760 308738 294370 309038 6 vccd2
+port 829 nsew default input
+rlabel metal5 s -2408 308738 240 309038 4 vccd2
+port 830 nsew default input
+rlabel metal5 s 291760 290738 294370 291038 6 vccd2
+port 831 nsew default input
+rlabel metal5 s -2408 290738 240 291038 4 vccd2
+port 832 nsew default input
+rlabel metal5 s 291760 272738 294370 273038 6 vccd2
+port 833 nsew default input
+rlabel metal5 s -2408 272738 240 273038 4 vccd2
+port 834 nsew default input
+rlabel metal5 s 291760 254738 294370 255038 6 vccd2
+port 835 nsew default input
+rlabel metal5 s -2408 254738 240 255038 4 vccd2
+port 836 nsew default input
+rlabel metal5 s 291760 236738 294370 237038 6 vccd2
+port 837 nsew default input
+rlabel metal5 s -2408 236738 240 237038 4 vccd2
+port 838 nsew default input
+rlabel metal5 s 291760 218738 294370 219038 6 vccd2
+port 839 nsew default input
+rlabel metal5 s -2408 218738 240 219038 4 vccd2
+port 840 nsew default input
+rlabel metal5 s 291760 200738 294370 201038 6 vccd2
+port 841 nsew default input
+rlabel metal5 s -2408 200738 240 201038 4 vccd2
+port 842 nsew default input
+rlabel metal5 s 291760 182738 294370 183038 6 vccd2
+port 843 nsew default input
+rlabel metal5 s -2408 182738 240 183038 4 vccd2
+port 844 nsew default input
+rlabel metal5 s 291760 164738 294370 165038 6 vccd2
+port 845 nsew default input
+rlabel metal5 s -2408 164738 240 165038 4 vccd2
+port 846 nsew default input
+rlabel metal5 s 291760 146738 294370 147038 6 vccd2
+port 847 nsew default input
+rlabel metal5 s -2408 146738 240 147038 4 vccd2
+port 848 nsew default input
+rlabel metal5 s 291760 128738 294370 129038 6 vccd2
+port 849 nsew default input
+rlabel metal5 s -2408 128738 240 129038 4 vccd2
+port 850 nsew default input
+rlabel metal5 s 291760 110738 294370 111038 6 vccd2
+port 851 nsew default input
+rlabel metal5 s -2408 110738 240 111038 4 vccd2
+port 852 nsew default input
+rlabel metal5 s 291760 92738 294370 93038 6 vccd2
+port 853 nsew default input
+rlabel metal5 s -2408 92738 240 93038 4 vccd2
+port 854 nsew default input
+rlabel metal5 s 291760 74738 294370 75038 6 vccd2
+port 855 nsew default input
+rlabel metal5 s -2408 74738 240 75038 4 vccd2
+port 856 nsew default input
+rlabel metal5 s 291760 56738 294370 57038 6 vccd2
+port 857 nsew default input
+rlabel metal5 s -2408 56738 240 57038 4 vccd2
+port 858 nsew default input
+rlabel metal5 s 291760 38738 294370 39038 6 vccd2
+port 859 nsew default input
+rlabel metal5 s -2408 38738 240 39038 4 vccd2
+port 860 nsew default input
+rlabel metal5 s 291760 20738 294370 21038 6 vccd2
+port 861 nsew default input
+rlabel metal5 s -2408 20738 240 21038 4 vccd2
+port 862 nsew default input
+rlabel metal5 s 291760 2738 294370 3038 6 vccd2
+port 863 nsew default input
+rlabel metal5 s -2408 2738 240 3038 4 vccd2
+port 864 nsew default input
+rlabel metal5 s -1938 -1402 293900 -1102 8 vccd2
+port 865 nsew default input
+rlabel metal4 s 294070 -1872 294370 353840 6 vssd2
+port 866 nsew default input
+rlabel metal4 s 281202 351760 281502 353840 6 vssd2
+port 867 nsew default input
+rlabel metal4 s 263202 351760 263502 353840 6 vssd2
+port 868 nsew default input
+rlabel metal4 s 245202 351760 245502 353840 6 vssd2
+port 869 nsew default input
+rlabel metal4 s 227202 351760 227502 353840 6 vssd2
+port 870 nsew default input
+rlabel metal4 s 209202 351760 209502 353840 6 vssd2
+port 871 nsew default input
+rlabel metal4 s 191202 351760 191502 353840 6 vssd2
+port 872 nsew default input
+rlabel metal4 s 173202 351760 173502 353840 6 vssd2
+port 873 nsew default input
+rlabel metal4 s 155202 351760 155502 353840 6 vssd2
+port 874 nsew default input
+rlabel metal4 s 137202 351760 137502 353840 6 vssd2
+port 875 nsew default input
+rlabel metal4 s 119202 351760 119502 353840 6 vssd2
+port 876 nsew default input
+rlabel metal4 s 101202 351760 101502 353840 6 vssd2
+port 877 nsew default input
+rlabel metal4 s 83202 351760 83502 353840 6 vssd2
+port 878 nsew default input
+rlabel metal4 s 65202 351760 65502 353840 6 vssd2
+port 879 nsew default input
+rlabel metal4 s 47202 351760 47502 353840 6 vssd2
+port 880 nsew default input
+rlabel metal4 s 29202 351760 29502 353840 6 vssd2
+port 881 nsew default input
+rlabel metal4 s 11202 351760 11502 353840 6 vssd2
+port 882 nsew default input
+rlabel metal4 s -2408 -1872 -2108 353840 4 vssd2
+port 883 nsew default input
+rlabel metal4 s 281202 -1872 281502 240 8 vssd2
+port 884 nsew default input
+rlabel metal4 s 263202 -1872 263502 240 8 vssd2
+port 885 nsew default input
+rlabel metal4 s 245202 -1872 245502 240 8 vssd2
+port 886 nsew default input
+rlabel metal4 s 227202 -1872 227502 240 8 vssd2
+port 887 nsew default input
+rlabel metal4 s 209202 -1872 209502 240 8 vssd2
+port 888 nsew default input
+rlabel metal4 s 191202 -1872 191502 240 8 vssd2
+port 889 nsew default input
+rlabel metal4 s 173202 -1872 173502 240 8 vssd2
+port 890 nsew default input
+rlabel metal4 s 155202 -1872 155502 240 8 vssd2
+port 891 nsew default input
+rlabel metal4 s 137202 -1872 137502 240 8 vssd2
+port 892 nsew default input
+rlabel metal4 s 119202 -1872 119502 240 8 vssd2
+port 893 nsew default input
+rlabel metal4 s 101202 -1872 101502 240 8 vssd2
+port 894 nsew default input
+rlabel metal4 s 83202 -1872 83502 240 8 vssd2
+port 895 nsew default input
+rlabel metal4 s 65202 -1872 65502 240 8 vssd2
+port 896 nsew default input
+rlabel metal4 s 47202 -1872 47502 240 8 vssd2
+port 897 nsew default input
+rlabel metal4 s 29202 -1872 29502 240 8 vssd2
+port 898 nsew default input
+rlabel metal4 s 11202 -1872 11502 240 8 vssd2
+port 899 nsew default input
+rlabel metal5 s -2408 353540 294370 353840 6 vssd2
+port 900 nsew default input
+rlabel metal5 s 291760 335738 294370 336038 6 vssd2
+port 901 nsew default input
+rlabel metal5 s -2408 335738 240 336038 4 vssd2
+port 902 nsew default input
+rlabel metal5 s 291760 317738 294370 318038 6 vssd2
+port 903 nsew default input
+rlabel metal5 s -2408 317738 240 318038 4 vssd2
+port 904 nsew default input
+rlabel metal5 s 291760 299738 294370 300038 6 vssd2
+port 905 nsew default input
+rlabel metal5 s -2408 299738 240 300038 4 vssd2
+port 906 nsew default input
+rlabel metal5 s 291760 281738 294370 282038 6 vssd2
+port 907 nsew default input
+rlabel metal5 s -2408 281738 240 282038 4 vssd2
+port 908 nsew default input
+rlabel metal5 s 291760 263738 294370 264038 6 vssd2
+port 909 nsew default input
+rlabel metal5 s -2408 263738 240 264038 4 vssd2
+port 910 nsew default input
+rlabel metal5 s 291760 245738 294370 246038 6 vssd2
+port 911 nsew default input
+rlabel metal5 s -2408 245738 240 246038 4 vssd2
+port 912 nsew default input
+rlabel metal5 s 291760 227738 294370 228038 6 vssd2
+port 913 nsew default input
+rlabel metal5 s -2408 227738 240 228038 4 vssd2
+port 914 nsew default input
+rlabel metal5 s 291760 209738 294370 210038 6 vssd2
+port 915 nsew default input
+rlabel metal5 s -2408 209738 240 210038 4 vssd2
+port 916 nsew default input
+rlabel metal5 s 291760 191738 294370 192038 6 vssd2
+port 917 nsew default input
+rlabel metal5 s -2408 191738 240 192038 4 vssd2
+port 918 nsew default input
+rlabel metal5 s 291760 173738 294370 174038 6 vssd2
+port 919 nsew default input
+rlabel metal5 s -2408 173738 240 174038 4 vssd2
+port 920 nsew default input
+rlabel metal5 s 291760 155738 294370 156038 6 vssd2
+port 921 nsew default input
+rlabel metal5 s -2408 155738 240 156038 4 vssd2
+port 922 nsew default input
+rlabel metal5 s 291760 137738 294370 138038 6 vssd2
+port 923 nsew default input
+rlabel metal5 s -2408 137738 240 138038 4 vssd2
+port 924 nsew default input
+rlabel metal5 s 291760 119738 294370 120038 6 vssd2
+port 925 nsew default input
+rlabel metal5 s -2408 119738 240 120038 4 vssd2
+port 926 nsew default input
+rlabel metal5 s 291760 101738 294370 102038 6 vssd2
+port 927 nsew default input
+rlabel metal5 s -2408 101738 240 102038 4 vssd2
+port 928 nsew default input
+rlabel metal5 s 291760 83738 294370 84038 6 vssd2
+port 929 nsew default input
+rlabel metal5 s -2408 83738 240 84038 4 vssd2
+port 930 nsew default input
+rlabel metal5 s 291760 65738 294370 66038 6 vssd2
+port 931 nsew default input
+rlabel metal5 s -2408 65738 240 66038 4 vssd2
+port 932 nsew default input
+rlabel metal5 s 291760 47738 294370 48038 6 vssd2
+port 933 nsew default input
+rlabel metal5 s -2408 47738 240 48038 4 vssd2
+port 934 nsew default input
+rlabel metal5 s 291760 29738 294370 30038 6 vssd2
+port 935 nsew default input
+rlabel metal5 s -2408 29738 240 30038 4 vssd2
+port 936 nsew default input
+rlabel metal5 s 291760 11738 294370 12038 6 vssd2
+port 937 nsew default input
+rlabel metal5 s -2408 11738 240 12038 4 vssd2
+port 938 nsew default input
+rlabel metal5 s -2408 -1872 294370 -1572 8 vssd2
+port 939 nsew default input
+rlabel metal4 s 274002 351760 274302 354780 6 vdda1
+port 940 nsew default input
+rlabel metal4 s 256002 351760 256302 354780 6 vdda1
+port 941 nsew default input
+rlabel metal4 s 238002 351760 238302 354780 6 vdda1
+port 942 nsew default input
+rlabel metal4 s 220002 351760 220302 354780 6 vdda1
+port 943 nsew default input
+rlabel metal4 s 202002 351760 202302 354780 6 vdda1
+port 944 nsew default input
+rlabel metal4 s 184002 351760 184302 354780 6 vdda1
+port 945 nsew default input
+rlabel metal4 s 166002 351760 166302 354780 6 vdda1
+port 946 nsew default input
+rlabel metal4 s 148002 351760 148302 354780 6 vdda1
+port 947 nsew default input
+rlabel metal4 s 130002 351760 130302 354780 6 vdda1
+port 948 nsew default input
+rlabel metal4 s 112002 351760 112302 354780 6 vdda1
+port 949 nsew default input
+rlabel metal4 s 94002 351760 94302 354780 6 vdda1
+port 950 nsew default input
+rlabel metal4 s 76002 351760 76302 354780 6 vdda1
+port 951 nsew default input
+rlabel metal4 s 58002 351760 58302 354780 6 vdda1
+port 952 nsew default input
+rlabel metal4 s 40002 351760 40302 354780 6 vdda1
+port 953 nsew default input
+rlabel metal4 s 22002 351760 22302 354780 6 vdda1
+port 954 nsew default input
+rlabel metal4 s 4002 351760 4302 354780 6 vdda1
+port 955 nsew default input
+rlabel metal4 s 294540 -2342 294840 354310 6 vdda1
+port 956 nsew default input
+rlabel metal4 s -2878 -2342 -2578 354310 4 vdda1
+port 957 nsew default input
+rlabel metal4 s 274002 -2812 274302 240 8 vdda1
+port 958 nsew default input
+rlabel metal4 s 256002 -2812 256302 240 8 vdda1
+port 959 nsew default input
+rlabel metal4 s 238002 -2812 238302 240 8 vdda1
+port 960 nsew default input
+rlabel metal4 s 220002 -2812 220302 240 8 vdda1
+port 961 nsew default input
+rlabel metal4 s 202002 -2812 202302 240 8 vdda1
+port 962 nsew default input
+rlabel metal4 s 184002 -2812 184302 240 8 vdda1
+port 963 nsew default input
+rlabel metal4 s 166002 -2812 166302 240 8 vdda1
+port 964 nsew default input
+rlabel metal4 s 148002 -2812 148302 240 8 vdda1
+port 965 nsew default input
+rlabel metal4 s 130002 -2812 130302 240 8 vdda1
+port 966 nsew default input
+rlabel metal4 s 112002 -2812 112302 240 8 vdda1
+port 967 nsew default input
+rlabel metal4 s 94002 -2812 94302 240 8 vdda1
+port 968 nsew default input
+rlabel metal4 s 76002 -2812 76302 240 8 vdda1
+port 969 nsew default input
+rlabel metal4 s 58002 -2812 58302 240 8 vdda1
+port 970 nsew default input
+rlabel metal4 s 40002 -2812 40302 240 8 vdda1
+port 971 nsew default input
+rlabel metal4 s 22002 -2812 22302 240 8 vdda1
+port 972 nsew default input
+rlabel metal4 s 4002 -2812 4302 240 8 vdda1
+port 973 nsew default input
+rlabel metal5 s -2878 354010 294840 354310 6 vdda1
+port 974 nsew default input
+rlabel metal5 s 291760 346538 295310 346838 6 vdda1
+port 975 nsew default input
+rlabel metal5 s -3348 346538 240 346838 4 vdda1
+port 976 nsew default input
+rlabel metal5 s 291760 328538 295310 328838 6 vdda1
+port 977 nsew default input
+rlabel metal5 s -3348 328538 240 328838 4 vdda1
+port 978 nsew default input
+rlabel metal5 s 291760 310538 295310 310838 6 vdda1
+port 979 nsew default input
+rlabel metal5 s -3348 310538 240 310838 4 vdda1
+port 980 nsew default input
+rlabel metal5 s 291760 292538 295310 292838 6 vdda1
+port 981 nsew default input
+rlabel metal5 s -3348 292538 240 292838 4 vdda1
+port 982 nsew default input
+rlabel metal5 s 291760 274538 295310 274838 6 vdda1
+port 983 nsew default input
+rlabel metal5 s -3348 274538 240 274838 4 vdda1
+port 984 nsew default input
+rlabel metal5 s 291760 256538 295310 256838 6 vdda1
+port 985 nsew default input
+rlabel metal5 s -3348 256538 240 256838 4 vdda1
+port 986 nsew default input
+rlabel metal5 s 291760 238538 295310 238838 6 vdda1
+port 987 nsew default input
+rlabel metal5 s -3348 238538 240 238838 4 vdda1
+port 988 nsew default input
+rlabel metal5 s 291760 220538 295310 220838 6 vdda1
+port 989 nsew default input
+rlabel metal5 s -3348 220538 240 220838 4 vdda1
+port 990 nsew default input
+rlabel metal5 s 291760 202538 295310 202838 6 vdda1
+port 991 nsew default input
+rlabel metal5 s -3348 202538 240 202838 4 vdda1
+port 992 nsew default input
+rlabel metal5 s 291760 184538 295310 184838 6 vdda1
+port 993 nsew default input
+rlabel metal5 s -3348 184538 240 184838 4 vdda1
+port 994 nsew default input
+rlabel metal5 s 291760 166538 295310 166838 6 vdda1
+port 995 nsew default input
+rlabel metal5 s -3348 166538 240 166838 4 vdda1
+port 996 nsew default input
+rlabel metal5 s 291760 148538 295310 148838 6 vdda1
+port 997 nsew default input
+rlabel metal5 s -3348 148538 240 148838 4 vdda1
+port 998 nsew default input
+rlabel metal5 s 291760 130538 295310 130838 6 vdda1
+port 999 nsew default input
+rlabel metal5 s -3348 130538 240 130838 4 vdda1
+port 1000 nsew default input
+rlabel metal5 s 291760 112538 295310 112838 6 vdda1
+port 1001 nsew default input
+rlabel metal5 s -3348 112538 240 112838 4 vdda1
+port 1002 nsew default input
+rlabel metal5 s 291760 94538 295310 94838 6 vdda1
+port 1003 nsew default input
+rlabel metal5 s -3348 94538 240 94838 4 vdda1
+port 1004 nsew default input
+rlabel metal5 s 291760 76538 295310 76838 6 vdda1
+port 1005 nsew default input
+rlabel metal5 s -3348 76538 240 76838 4 vdda1
+port 1006 nsew default input
+rlabel metal5 s 291760 58538 295310 58838 6 vdda1
+port 1007 nsew default input
+rlabel metal5 s -3348 58538 240 58838 4 vdda1
+port 1008 nsew default input
+rlabel metal5 s 291760 40538 295310 40838 6 vdda1
+port 1009 nsew default input
+rlabel metal5 s -3348 40538 240 40838 4 vdda1
+port 1010 nsew default input
+rlabel metal5 s 291760 22538 295310 22838 6 vdda1
+port 1011 nsew default input
+rlabel metal5 s -3348 22538 240 22838 4 vdda1
+port 1012 nsew default input
+rlabel metal5 s 291760 4538 295310 4838 6 vdda1
+port 1013 nsew default input
+rlabel metal5 s -3348 4538 240 4838 4 vdda1
+port 1014 nsew default input
+rlabel metal5 s -2878 -2342 294840 -2042 8 vdda1
+port 1015 nsew default input
+rlabel metal4 s 295010 -2812 295310 354780 6 vssa1
+port 1016 nsew default input
+rlabel metal4 s 283002 351760 283302 354780 6 vssa1
+port 1017 nsew default input
+rlabel metal4 s 265002 351760 265302 354780 6 vssa1
+port 1018 nsew default input
+rlabel metal4 s 247002 351760 247302 354780 6 vssa1
+port 1019 nsew default input
+rlabel metal4 s 229002 351760 229302 354780 6 vssa1
+port 1020 nsew default input
+rlabel metal4 s 211002 351760 211302 354780 6 vssa1
+port 1021 nsew default input
+rlabel metal4 s 193002 351760 193302 354780 6 vssa1
+port 1022 nsew default input
+rlabel metal4 s 175002 351760 175302 354780 6 vssa1
+port 1023 nsew default input
+rlabel metal4 s 157002 351760 157302 354780 6 vssa1
+port 1024 nsew default input
+rlabel metal4 s 139002 351760 139302 354780 6 vssa1
+port 1025 nsew default input
+rlabel metal4 s 121002 351760 121302 354780 6 vssa1
+port 1026 nsew default input
+rlabel metal4 s 103002 351760 103302 354780 6 vssa1
+port 1027 nsew default input
+rlabel metal4 s 85002 351760 85302 354780 6 vssa1
+port 1028 nsew default input
+rlabel metal4 s 67002 351760 67302 354780 6 vssa1
+port 1029 nsew default input
+rlabel metal4 s 49002 351760 49302 354780 6 vssa1
+port 1030 nsew default input
+rlabel metal4 s 31002 351760 31302 354780 6 vssa1
+port 1031 nsew default input
+rlabel metal4 s 13002 351760 13302 354780 6 vssa1
+port 1032 nsew default input
+rlabel metal4 s -3348 -2812 -3048 354780 4 vssa1
+port 1033 nsew default input
+rlabel metal4 s 283002 -2812 283302 240 8 vssa1
+port 1034 nsew default input
+rlabel metal4 s 265002 -2812 265302 240 8 vssa1
+port 1035 nsew default input
+rlabel metal4 s 247002 -2812 247302 240 8 vssa1
+port 1036 nsew default input
+rlabel metal4 s 229002 -2812 229302 240 8 vssa1
+port 1037 nsew default input
+rlabel metal4 s 211002 -2812 211302 240 8 vssa1
+port 1038 nsew default input
+rlabel metal4 s 193002 -2812 193302 240 8 vssa1
+port 1039 nsew default input
+rlabel metal4 s 175002 -2812 175302 240 8 vssa1
+port 1040 nsew default input
+rlabel metal4 s 157002 -2812 157302 240 8 vssa1
+port 1041 nsew default input
+rlabel metal4 s 139002 -2812 139302 240 8 vssa1
+port 1042 nsew default input
+rlabel metal4 s 121002 -2812 121302 240 8 vssa1
+port 1043 nsew default input
+rlabel metal4 s 103002 -2812 103302 240 8 vssa1
+port 1044 nsew default input
+rlabel metal4 s 85002 -2812 85302 240 8 vssa1
+port 1045 nsew default input
+rlabel metal4 s 67002 -2812 67302 240 8 vssa1
+port 1046 nsew default input
+rlabel metal4 s 49002 -2812 49302 240 8 vssa1
+port 1047 nsew default input
+rlabel metal4 s 31002 -2812 31302 240 8 vssa1
+port 1048 nsew default input
+rlabel metal4 s 13002 -2812 13302 240 8 vssa1
+port 1049 nsew default input
+rlabel metal5 s -3348 354480 295310 354780 6 vssa1
+port 1050 nsew default input
+rlabel metal5 s 291760 337538 295310 337838 6 vssa1
+port 1051 nsew default input
+rlabel metal5 s -3348 337538 240 337838 4 vssa1
+port 1052 nsew default input
+rlabel metal5 s 291760 319538 295310 319838 6 vssa1
+port 1053 nsew default input
+rlabel metal5 s -3348 319538 240 319838 4 vssa1
+port 1054 nsew default input
+rlabel metal5 s 291760 301538 295310 301838 6 vssa1
+port 1055 nsew default input
+rlabel metal5 s -3348 301538 240 301838 4 vssa1
+port 1056 nsew default input
+rlabel metal5 s 291760 283538 295310 283838 6 vssa1
+port 1057 nsew default input
+rlabel metal5 s -3348 283538 240 283838 4 vssa1
+port 1058 nsew default input
+rlabel metal5 s 291760 265538 295310 265838 6 vssa1
+port 1059 nsew default input
+rlabel metal5 s -3348 265538 240 265838 4 vssa1
+port 1060 nsew default input
+rlabel metal5 s 291760 247538 295310 247838 6 vssa1
+port 1061 nsew default input
+rlabel metal5 s -3348 247538 240 247838 4 vssa1
+port 1062 nsew default input
+rlabel metal5 s 291760 229538 295310 229838 6 vssa1
+port 1063 nsew default input
+rlabel metal5 s -3348 229538 240 229838 4 vssa1
+port 1064 nsew default input
+rlabel metal5 s 291760 211538 295310 211838 6 vssa1
+port 1065 nsew default input
+rlabel metal5 s -3348 211538 240 211838 4 vssa1
+port 1066 nsew default input
+rlabel metal5 s 291760 193538 295310 193838 6 vssa1
+port 1067 nsew default input
+rlabel metal5 s -3348 193538 240 193838 4 vssa1
+port 1068 nsew default input
+rlabel metal5 s 291760 175538 295310 175838 6 vssa1
+port 1069 nsew default input
+rlabel metal5 s -3348 175538 240 175838 4 vssa1
+port 1070 nsew default input
+rlabel metal5 s 291760 157538 295310 157838 6 vssa1
+port 1071 nsew default input
+rlabel metal5 s -3348 157538 240 157838 4 vssa1
+port 1072 nsew default input
+rlabel metal5 s 291760 139538 295310 139838 6 vssa1
+port 1073 nsew default input
+rlabel metal5 s -3348 139538 240 139838 4 vssa1
+port 1074 nsew default input
+rlabel metal5 s 291760 121538 295310 121838 6 vssa1
+port 1075 nsew default input
+rlabel metal5 s -3348 121538 240 121838 4 vssa1
+port 1076 nsew default input
+rlabel metal5 s 291760 103538 295310 103838 6 vssa1
+port 1077 nsew default input
+rlabel metal5 s -3348 103538 240 103838 4 vssa1
+port 1078 nsew default input
+rlabel metal5 s 291760 85538 295310 85838 6 vssa1
+port 1079 nsew default input
+rlabel metal5 s -3348 85538 240 85838 4 vssa1
+port 1080 nsew default input
+rlabel metal5 s 291760 67538 295310 67838 6 vssa1
+port 1081 nsew default input
+rlabel metal5 s -3348 67538 240 67838 4 vssa1
+port 1082 nsew default input
+rlabel metal5 s 291760 49538 295310 49838 6 vssa1
+port 1083 nsew default input
+rlabel metal5 s -3348 49538 240 49838 4 vssa1
+port 1084 nsew default input
+rlabel metal5 s 291760 31538 295310 31838 6 vssa1
+port 1085 nsew default input
+rlabel metal5 s -3348 31538 240 31838 4 vssa1
+port 1086 nsew default input
+rlabel metal5 s 291760 13538 295310 13838 6 vssa1
+port 1087 nsew default input
+rlabel metal5 s -3348 13538 240 13838 4 vssa1
+port 1088 nsew default input
+rlabel metal5 s -3348 -2812 295310 -2512 8 vssa1
+port 1089 nsew default input
+rlabel metal4 s 275802 351760 276102 355720 6 vdda2
+port 1090 nsew default input
+rlabel metal4 s 257802 351760 258102 355720 6 vdda2
+port 1091 nsew default input
+rlabel metal4 s 239802 351760 240102 355720 6 vdda2
+port 1092 nsew default input
+rlabel metal4 s 221802 351760 222102 355720 6 vdda2
+port 1093 nsew default input
+rlabel metal4 s 203802 351760 204102 355720 6 vdda2
+port 1094 nsew default input
+rlabel metal4 s 185802 351760 186102 355720 6 vdda2
+port 1095 nsew default input
+rlabel metal4 s 167802 351760 168102 355720 6 vdda2
+port 1096 nsew default input
+rlabel metal4 s 149802 351760 150102 355720 6 vdda2
+port 1097 nsew default input
+rlabel metal4 s 131802 351760 132102 355720 6 vdda2
+port 1098 nsew default input
+rlabel metal4 s 113802 351760 114102 355720 6 vdda2
+port 1099 nsew default input
+rlabel metal4 s 95802 351760 96102 355720 6 vdda2
+port 1100 nsew default input
+rlabel metal4 s 77802 351760 78102 355720 6 vdda2
+port 1101 nsew default input
+rlabel metal4 s 59802 351760 60102 355720 6 vdda2
+port 1102 nsew default input
+rlabel metal4 s 41802 351760 42102 355720 6 vdda2
+port 1103 nsew default input
+rlabel metal4 s 23802 351760 24102 355720 6 vdda2
+port 1104 nsew default input
+rlabel metal4 s 5802 351760 6102 355720 6 vdda2
+port 1105 nsew default input
+rlabel metal4 s 295480 -3282 295780 355250 6 vdda2
+port 1106 nsew default input
+rlabel metal4 s -3818 -3282 -3518 355250 4 vdda2
+port 1107 nsew default input
+rlabel metal4 s 275802 -3752 276102 240 8 vdda2
+port 1108 nsew default input
+rlabel metal4 s 257802 -3752 258102 240 8 vdda2
+port 1109 nsew default input
+rlabel metal4 s 239802 -3752 240102 240 8 vdda2
+port 1110 nsew default input
+rlabel metal4 s 221802 -3752 222102 240 8 vdda2
+port 1111 nsew default input
+rlabel metal4 s 203802 -3752 204102 240 8 vdda2
+port 1112 nsew default input
+rlabel metal4 s 185802 -3752 186102 240 8 vdda2
+port 1113 nsew default input
+rlabel metal4 s 167802 -3752 168102 240 8 vdda2
+port 1114 nsew default input
+rlabel metal4 s 149802 -3752 150102 240 8 vdda2
+port 1115 nsew default input
+rlabel metal4 s 131802 -3752 132102 240 8 vdda2
+port 1116 nsew default input
+rlabel metal4 s 113802 -3752 114102 240 8 vdda2
+port 1117 nsew default input
+rlabel metal4 s 95802 -3752 96102 240 8 vdda2
+port 1118 nsew default input
+rlabel metal4 s 77802 -3752 78102 240 8 vdda2
+port 1119 nsew default input
+rlabel metal4 s 59802 -3752 60102 240 8 vdda2
+port 1120 nsew default input
+rlabel metal4 s 41802 -3752 42102 240 8 vdda2
+port 1121 nsew default input
+rlabel metal4 s 23802 -3752 24102 240 8 vdda2
+port 1122 nsew default input
+rlabel metal4 s 5802 -3752 6102 240 8 vdda2
+port 1123 nsew default input
+rlabel metal5 s -3818 354950 295780 355250 6 vdda2
+port 1124 nsew default input
+rlabel metal5 s 291760 348338 296250 348638 6 vdda2
+port 1125 nsew default input
+rlabel metal5 s -4288 348338 240 348638 4 vdda2
+port 1126 nsew default input
+rlabel metal5 s 291760 330338 296250 330638 6 vdda2
+port 1127 nsew default input
+rlabel metal5 s -4288 330338 240 330638 4 vdda2
+port 1128 nsew default input
+rlabel metal5 s 291760 312338 296250 312638 6 vdda2
+port 1129 nsew default input
+rlabel metal5 s -4288 312338 240 312638 4 vdda2
+port 1130 nsew default input
+rlabel metal5 s 291760 294338 296250 294638 6 vdda2
+port 1131 nsew default input
+rlabel metal5 s -4288 294338 240 294638 4 vdda2
+port 1132 nsew default input
+rlabel metal5 s 291760 276338 296250 276638 6 vdda2
+port 1133 nsew default input
+rlabel metal5 s -4288 276338 240 276638 4 vdda2
+port 1134 nsew default input
+rlabel metal5 s 291760 258338 296250 258638 6 vdda2
+port 1135 nsew default input
+rlabel metal5 s -4288 258338 240 258638 4 vdda2
+port 1136 nsew default input
+rlabel metal5 s 291760 240338 296250 240638 6 vdda2
+port 1137 nsew default input
+rlabel metal5 s -4288 240338 240 240638 4 vdda2
+port 1138 nsew default input
+rlabel metal5 s 291760 222338 296250 222638 6 vdda2
+port 1139 nsew default input
+rlabel metal5 s -4288 222338 240 222638 4 vdda2
+port 1140 nsew default input
+rlabel metal5 s 291760 204338 296250 204638 6 vdda2
+port 1141 nsew default input
+rlabel metal5 s -4288 204338 240 204638 4 vdda2
+port 1142 nsew default input
+rlabel metal5 s 291760 186338 296250 186638 6 vdda2
+port 1143 nsew default input
+rlabel metal5 s -4288 186338 240 186638 4 vdda2
+port 1144 nsew default input
+rlabel metal5 s 291760 168338 296250 168638 6 vdda2
+port 1145 nsew default input
+rlabel metal5 s -4288 168338 240 168638 4 vdda2
+port 1146 nsew default input
+rlabel metal5 s 291760 150338 296250 150638 6 vdda2
+port 1147 nsew default input
+rlabel metal5 s -4288 150338 240 150638 4 vdda2
+port 1148 nsew default input
+rlabel metal5 s 291760 132338 296250 132638 6 vdda2
+port 1149 nsew default input
+rlabel metal5 s -4288 132338 240 132638 4 vdda2
+port 1150 nsew default input
+rlabel metal5 s 291760 114338 296250 114638 6 vdda2
+port 1151 nsew default input
+rlabel metal5 s -4288 114338 240 114638 4 vdda2
+port 1152 nsew default input
+rlabel metal5 s 291760 96338 296250 96638 6 vdda2
+port 1153 nsew default input
+rlabel metal5 s -4288 96338 240 96638 4 vdda2
+port 1154 nsew default input
+rlabel metal5 s 291760 78338 296250 78638 6 vdda2
+port 1155 nsew default input
+rlabel metal5 s -4288 78338 240 78638 4 vdda2
+port 1156 nsew default input
+rlabel metal5 s 291760 60338 296250 60638 6 vdda2
+port 1157 nsew default input
+rlabel metal5 s -4288 60338 240 60638 4 vdda2
+port 1158 nsew default input
+rlabel metal5 s 291760 42338 296250 42638 6 vdda2
+port 1159 nsew default input
+rlabel metal5 s -4288 42338 240 42638 4 vdda2
+port 1160 nsew default input
+rlabel metal5 s 291760 24338 296250 24638 6 vdda2
+port 1161 nsew default input
+rlabel metal5 s -4288 24338 240 24638 4 vdda2
+port 1162 nsew default input
+rlabel metal5 s 291760 6338 296250 6638 6 vdda2
+port 1163 nsew default input
+rlabel metal5 s -4288 6338 240 6638 4 vdda2
+port 1164 nsew default input
+rlabel metal5 s -3818 -3282 295780 -2982 8 vdda2
+port 1165 nsew default input
+rlabel metal4 s 295950 -3752 296250 355720 6 vssa2
+port 1166 nsew default input
+rlabel metal4 s 284802 351760 285102 355720 6 vssa2
+port 1167 nsew default input
+rlabel metal4 s 266802 351760 267102 355720 6 vssa2
+port 1168 nsew default input
+rlabel metal4 s 248802 351760 249102 355720 6 vssa2
+port 1169 nsew default input
+rlabel metal4 s 230802 351760 231102 355720 6 vssa2
+port 1170 nsew default input
+rlabel metal4 s 212802 351760 213102 355720 6 vssa2
+port 1171 nsew default input
+rlabel metal4 s 194802 351760 195102 355720 6 vssa2
+port 1172 nsew default input
+rlabel metal4 s 176802 351760 177102 355720 6 vssa2
+port 1173 nsew default input
+rlabel metal4 s 158802 351760 159102 355720 6 vssa2
+port 1174 nsew default input
+rlabel metal4 s 140802 351760 141102 355720 6 vssa2
+port 1175 nsew default input
+rlabel metal4 s 122802 351760 123102 355720 6 vssa2
+port 1176 nsew default input
+rlabel metal4 s 104802 351760 105102 355720 6 vssa2
+port 1177 nsew default input
+rlabel metal4 s 86802 351760 87102 355720 6 vssa2
+port 1178 nsew default input
+rlabel metal4 s 68802 351760 69102 355720 6 vssa2
+port 1179 nsew default input
+rlabel metal4 s 50802 351760 51102 355720 6 vssa2
+port 1180 nsew default input
+rlabel metal4 s 32802 351760 33102 355720 6 vssa2
+port 1181 nsew default input
+rlabel metal4 s 14802 351760 15102 355720 6 vssa2
+port 1182 nsew default input
+rlabel metal4 s -4288 -3752 -3988 355720 4 vssa2
+port 1183 nsew default input
+rlabel metal4 s 284802 -3752 285102 240 8 vssa2
+port 1184 nsew default input
+rlabel metal4 s 266802 -3752 267102 240 8 vssa2
+port 1185 nsew default input
+rlabel metal4 s 248802 -3752 249102 240 8 vssa2
+port 1186 nsew default input
+rlabel metal4 s 230802 -3752 231102 240 8 vssa2
+port 1187 nsew default input
+rlabel metal4 s 212802 -3752 213102 240 8 vssa2
+port 1188 nsew default input
+rlabel metal4 s 194802 -3752 195102 240 8 vssa2
+port 1189 nsew default input
+rlabel metal4 s 176802 -3752 177102 240 8 vssa2
+port 1190 nsew default input
+rlabel metal4 s 158802 -3752 159102 240 8 vssa2
+port 1191 nsew default input
+rlabel metal4 s 140802 -3752 141102 240 8 vssa2
+port 1192 nsew default input
+rlabel metal4 s 122802 -3752 123102 240 8 vssa2
+port 1193 nsew default input
+rlabel metal4 s 104802 -3752 105102 240 8 vssa2
+port 1194 nsew default input
+rlabel metal4 s 86802 -3752 87102 240 8 vssa2
+port 1195 nsew default input
+rlabel metal4 s 68802 -3752 69102 240 8 vssa2
+port 1196 nsew default input
+rlabel metal4 s 50802 -3752 51102 240 8 vssa2
+port 1197 nsew default input
+rlabel metal4 s 32802 -3752 33102 240 8 vssa2
+port 1198 nsew default input
+rlabel metal4 s 14802 -3752 15102 240 8 vssa2
+port 1199 nsew default input
+rlabel metal5 s -4288 355420 296250 355720 6 vssa2
+port 1200 nsew default input
+rlabel metal5 s 291760 339338 296250 339638 6 vssa2
+port 1201 nsew default input
+rlabel metal5 s -4288 339338 240 339638 4 vssa2
+port 1202 nsew default input
+rlabel metal5 s 291760 321338 296250 321638 6 vssa2
+port 1203 nsew default input
+rlabel metal5 s -4288 321338 240 321638 4 vssa2
+port 1204 nsew default input
+rlabel metal5 s 291760 303338 296250 303638 6 vssa2
+port 1205 nsew default input
+rlabel metal5 s -4288 303338 240 303638 4 vssa2
+port 1206 nsew default input
+rlabel metal5 s 291760 285338 296250 285638 6 vssa2
+port 1207 nsew default input
+rlabel metal5 s -4288 285338 240 285638 4 vssa2
+port 1208 nsew default input
+rlabel metal5 s 291760 267338 296250 267638 6 vssa2
+port 1209 nsew default input
+rlabel metal5 s -4288 267338 240 267638 4 vssa2
+port 1210 nsew default input
+rlabel metal5 s 291760 249338 296250 249638 6 vssa2
+port 1211 nsew default input
+rlabel metal5 s -4288 249338 240 249638 4 vssa2
+port 1212 nsew default input
+rlabel metal5 s 291760 231338 296250 231638 6 vssa2
+port 1213 nsew default input
+rlabel metal5 s -4288 231338 240 231638 4 vssa2
+port 1214 nsew default input
+rlabel metal5 s 291760 213338 296250 213638 6 vssa2
+port 1215 nsew default input
+rlabel metal5 s -4288 213338 240 213638 4 vssa2
+port 1216 nsew default input
+rlabel metal5 s 291760 195338 296250 195638 6 vssa2
+port 1217 nsew default input
+rlabel metal5 s -4288 195338 240 195638 4 vssa2
+port 1218 nsew default input
+rlabel metal5 s 291760 177338 296250 177638 6 vssa2
+port 1219 nsew default input
+rlabel metal5 s -4288 177338 240 177638 4 vssa2
+port 1220 nsew default input
+rlabel metal5 s 291760 159338 296250 159638 6 vssa2
+port 1221 nsew default input
+rlabel metal5 s -4288 159338 240 159638 4 vssa2
+port 1222 nsew default input
+rlabel metal5 s 291760 141338 296250 141638 6 vssa2
+port 1223 nsew default input
+rlabel metal5 s -4288 141338 240 141638 4 vssa2
+port 1224 nsew default input
+rlabel metal5 s 291760 123338 296250 123638 6 vssa2
+port 1225 nsew default input
+rlabel metal5 s -4288 123338 240 123638 4 vssa2
+port 1226 nsew default input
+rlabel metal5 s 291760 105338 296250 105638 6 vssa2
+port 1227 nsew default input
+rlabel metal5 s -4288 105338 240 105638 4 vssa2
+port 1228 nsew default input
+rlabel metal5 s 291760 87338 296250 87638 6 vssa2
+port 1229 nsew default input
+rlabel metal5 s -4288 87338 240 87638 4 vssa2
+port 1230 nsew default input
+rlabel metal5 s 291760 69338 296250 69638 6 vssa2
+port 1231 nsew default input
+rlabel metal5 s -4288 69338 240 69638 4 vssa2
+port 1232 nsew default input
+rlabel metal5 s 291760 51338 296250 51638 6 vssa2
+port 1233 nsew default input
+rlabel metal5 s -4288 51338 240 51638 4 vssa2
+port 1234 nsew default input
+rlabel metal5 s 291760 33338 296250 33638 6 vssa2
+port 1235 nsew default input
+rlabel metal5 s -4288 33338 240 33638 4 vssa2
+port 1236 nsew default input
+rlabel metal5 s 291760 15338 296250 15638 6 vssa2
+port 1237 nsew default input
+rlabel metal5 s -4288 15338 240 15638 4 vssa2
+port 1238 nsew default input
+rlabel metal5 s -4288 -3752 296250 -3452 8 vssa2
+port 1239 nsew default input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+string GDS_FILE ../gds/user_project_wrapper_empty.gds
+string GDS_END 370014
+string GDS_START 130
+<< end >>
diff --git a/manifest b/manifest
new file mode 100644
index 0000000..8ecbd49
--- /dev/null
+++ b/manifest
@@ -0,0 +1,56 @@
+d328f88dd48e015bbaa95e0d7c88954343cc5632 verilog/rtl/DFFRAM.v
+dab57f3c5464ce3354219840dae589a3fcd27135 verilog/rtl/DFFRAMBB.v
+46a8e0cab91f460de543c77ad6ef987af87b11bd verilog/rtl/caravel.v
+b2feeb2a098894d5d731a5b011858a471e855d73 verilog/rtl/caravel_clocking.v
+2f81d7936062037160cfdad06997cc0b84439511 verilog/rtl/chip_io.v
+d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c verilog/rtl/clock_div.v
+f937b52e53d45bdbe41bcbd07c65b41104c21756 verilog/rtl/convert_gpio_sigs.v
+a16f89c8efa638eab43641ab7047bb8eeedd6fa6 verilog/rtl/counter_timer_high.v
+d8eab2f4cef158e3c7800778ffc2367ab4abe130 verilog/rtl/counter_timer_low.v
+fff2d08e49701312c2ebd6714b7425baf83f3d35 verilog/rtl/digital_pll.v
+ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
+73b3cad3a826fabdd8406e1cc54425651de3b711 verilog/rtl/gpio_control_block.v
+57554b3586f306944b31718a8c52526fa9a8a574 verilog/rtl/gpio_wb.v
+baf3aba29655ca7021398ddc3f68be81eff0fa0c verilog/rtl/housekeeping_spi.v
+0544035d9f2bfc52ebcb3220a21f29e98a3784b4 verilog/rtl/la_wb.v
+ff3e65a783f3807340e25efac9207787d39fb6cd verilog/rtl/mem_wb.v
+65feb79043201d3609307a3dd5af4e75cc26e81b verilog/rtl/mgmt_core.v
+4d42909e102c472504739bc37559c6a34fd85ae1 verilog/rtl/mgmt_protect.v
+3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
+990e80add8b881f67d70eb52663dd885fddb8f7a verilog/rtl/mgmt_soc.v
+9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
+93eb7aa0f8489715145ff0870737fecf8be1fa8c verilog/rtl/mprj_ctrl.v
+2586a4c06bb540a5ca3803223f972243a2bbc1cc verilog/rtl/mprj_io.v
+d4dba320b923398939fcc45ed9db8ed61d71dcdf verilog/rtl/mprj_logic_high.v
+eac1e6d413cdfbc2f802e229ae5058828e01be1e verilog/rtl/pads.v
+b5aff2fda5078cfda377b98337fcc91040815fc2 verilog/rtl/picorv32.v
+669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
+6864cc10dacfd3edb4c66825b7a301ab097cea0d verilog/rtl/simple_por.v
+917aa6e1bb869f973c79fb2c7894eab882ead74c verilog/rtl/simple_spi_master.v
+293532d95583330278f9608fa1833cdae33a052d verilog/rtl/simpleuart.v
+46bca62460c4dbfac30233318b24c3d526a40058 verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+4501cd26dbf73787602b4c29324d0ba0c5caf46e verilog/rtl/spimemio.v
+3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+8dea2030f1f59fc58ce50d943c395b8041ff1fb3 verilog/rtl/storage.v
+7e8d789570ed224df49cf61f69593cc738790a5d verilog/rtl/storage_bridge_wb.v
+5e314e94a13d7291117123395ae088e1d17cf487 verilog/rtl/sysctrl.v
+e6246df6bbf0860a331b3547d64f7d235b0eca9a verilog/rtl/wb_intercon.v
+fa0922de31c054943abb75fb8bccd72e19f29f81 maglef/chip_io.mag
+0596a994ebb59aa6f8892dde6060cb1bddb65a82 maglef/digital_pll.mag
+ef61be6386ff6a7918c14b00980850c6d94024e3 maglef/gpio_control_block.mag
+a54426257f9f5a10515ed5db3ff40aab56e0298f maglef/mgmt_core.mag
+01cb0a625572c60a49dc25736329164800993739 maglef/mgmt_protect.mag
+6bd83ca8fd6da8735f713e3c782302417272da05 maglef/mgmt_protect_hv.mag
+280a4bc938d8fd3b6208d2b324835c19bd194de0 maglef/mprj2_logic_high.mag
+d0ad23504023314d6cc5fc2e71c881ca468f3c69 maglef/mprj_logic_high.mag
+ccd1692a5c7a5aa90744666697657f48af92a79b maglef/simple_por.mag
+d8e1539cc77e46867d5898bb153da9c5fc4af4e5 maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
+aee17d1399cb66772dfaab0b7a844daa47f1ec0b maglef/sram_1rw1r_32_256_8_sky130.mag
+7d161db43cff1e38961881b94ab1d261e74893ec maglef/storage.mag
+901cc6df77916c7716aa8721226270dd36749118 maglef/user_id_programming.mag
+10f6352ee314480f3d6a1e92cb9145dfa975951a mag/caravel.mag
+08dd27da4e7fa8b9757c8ce8c87dc3397f1f0027 mag/.magicrc
+9d06bd68e8ec6918cd3ef5467cb8cee44e7e3a26 scripts/set_user_id.py
+fb656ab5c417c535e31574f3a738389cd4decd2c scripts/generate_fill.py
+e273cce208fe0508e06b316691ffef1d74161e6c scripts/compositor.py
+4e3d3b2b41e3af3c3bbea4873bd2ce8c537eb6c1 lef/user_project_wrapper_empty.lef
diff --git a/ngspice/digital_pll/digital_pll/digital_pll.spice b/ngspice/digital_pll/digital_pll/digital_pll.spice
new file mode 100644
index 0000000..cd88d48
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/digital_pll.spice
@@ -0,0 +1,43 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* All-digital Frequency-locked loop
+*---------------------------------------------------------------------------
+* To make this simulatable, the circuit is broken into the ring oscillator
+* and controller, separately, with the controller converted into an xspice
+* model.
+*
+* For simplicity, the DCO mode has been removed, so no external trim with
+* multiplexer. Also no multiplexer on the internal reset.
+*---------------------------------------------------------------------------
+
+.include "digital_pll_controller.xspice"
+.include "ring_osc2x13.spice"
+
+.subckt digital_pll vdd vss reset osc clockp1 clockp0 div4 div3 div2 div1 div0
+
+X0 vdd vss clockp0 div0 div1 div2 div3 div4 osc reset trim0 trim1 trim2 trim3
++ trim4 trim5 trim6 trim7 trim8 trim9 trim10 trim11 trim12 trim13 trim14
++ trim15 trim16 trim17 trim18 trim19 trim20 trim21 trim22 trim23 trim24
++ trim25 digital_pll_controller
+
+X1 vdd vss clockp0 clockp1 reset trim0 trim1 trim2 trim3 trim4 trim5 trim6 trim7
++ trim8 trim9 trim10 trim11 trim12 trim13 trim14 trim15 trim16 trim17 trim18
++ trim19 trim20 trim21 trim22 trim23 trim24 trim25 ring_osc2x13
+
+.ends
+
+
diff --git a/ngspice/digital_pll/digital_pll/digital_pll_controller.xspice b/ngspice/digital_pll/digital_pll/digital_pll_controller.xspice
new file mode 100644
index 0000000..cbb0343
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/digital_pll_controller.xspice
@@ -0,0 +1,497 @@
+* XSpice netlist created from SPICE and liberty sources by spi2xspice.py
+* SPICE netlist created from verilog structural netlist module digital_pll_controller by vlog2Spice (qflow)
+*
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+******* EOF
+** End of included library /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+.subckt digital_pll_controller a_VPB a_VGND a_clock a_div_0_ a_div_1_ a_div_2_ a_div_3_ a_div_4_ a_osc a_reset a_trim_0_ a_trim_1_ a_trim_2_ a_trim_3_ a_trim_4_ a_trim_5_ a_trim_6_ a_trim_7_ a_trim_8_ a_trim_9_ a_trim_10_ a_trim_11_ a_trim_12_ a_trim_13_ a_trim_14_ a_trim_15_ a_trim_16_ a_trim_17_ a_trim_18_ a_trim_19_ a_trim_20_ a_trim_21_ a_trim_22_ a_trim_23_ a_trim_24_ a_trim_25_
+Asky130_fd_sc_hd__buf_1_insert11 [_64_] _64__bF$buf0 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert10 [_64_] _64__bF$buf1 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert9 [_64_] _64__bF$buf2 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert8 [_64_] _64__bF$buf3 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert7 [_4_] _4__bF$buf0 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert6 [_4_] _4__bF$buf1 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert5 [_4_] _4__bF$buf2 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__buf_1_insert4 [_4_] _4__bF$buf3 d_lut_sky130_fd_sc_hd__buf_1
+Asky130_fd_sc_hd__clkbuf_1_insert3 [clock] clock_bF$buf0 d_lut_sky130_fd_sc_hd__clkbuf_1
+Asky130_fd_sc_hd__clkbuf_1_insert2 [clock] clock_bF$buf1 d_lut_sky130_fd_sc_hd__clkbuf_1
+Asky130_fd_sc_hd__clkbuf_1_insert1 [clock] clock_bF$buf2 d_lut_sky130_fd_sc_hd__clkbuf_1
+Asky130_fd_sc_hd__clkbuf_1_insert0 [clock] clock_bF$buf3 d_lut_sky130_fd_sc_hd__clkbuf_1
+A_218_ [tint_1_ tint_0_] _194_ d_lut_sky130_fd_sc_hd__nor2_1
+A_219_ [tint_3_ tint_2_] _195_ d_lut_sky130_fd_sc_hd__nor2_1
+A_220_ [_194_ _195_] _196_ d_lut_sky130_fd_sc_hd__nand2_1
+A_221_ [tint_4_ _196_] _197_ d_lut_sky130_fd_sc_hd__nor2_1
+A_222_ [_197_] _217__0_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_223_ [tval_0_] _198_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_224_ [oscbuf_1_ oscbuf_2_] _199_ d_lut_sky130_fd_sc_hd__nor2_1
+A_225_ [oscbuf_1_ oscbuf_2_] _200_ d_lut_sky130_fd_sc_hd__nand2_1
+A_226_ [_200_] _201_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_227_ [_199_ _201_] _202_ d_lut_sky130_fd_sc_hd__or2_2
+A_228_ [_202_] _203_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_229_ [_203_ prep_0_] _204_ d_lut_sky130_fd_sc_hd__nand2_1
+A_230_ [prep_1_ prep_2_] _205_ d_lut_sky130_fd_sc_hd__nand2_1
+A_231_ [_205_ _204_] _206_ d_lut_sky130_fd_sc_hd__nor2_1
+A_232_ [count1_4_] _207_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_233_ [count0_4_] _208_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_234_ [_207_ _208_] _209_ d_lut_sky130_fd_sc_hd__nor2_1
+A_235_ [count1_4_ count0_4_] _210_ d_lut_sky130_fd_sc_hd__nor2_1
+A_236_ [_210_ _209_] _211_ d_lut_sky130_fd_sc_hd__or2_2
+A_237_ [count1_3_ count0_3_] _212_ d_lut_sky130_fd_sc_hd__and2_2
+A_238_ [count1_3_ count0_3_] _213_ d_lut_sky130_fd_sc_hd__nor2_1
+A_239_ [_213_] _214_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_240_ [count1_2_ count0_2_] _215_ d_lut_sky130_fd_sc_hd__and2_2
+A_241_ [_214_ _215_ _212_] _216_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_242_ [count1_1_ count0_1_] _5_ d_lut_sky130_fd_sc_hd__nand2_1
+A_243_ [count1_0_ count0_0_] _6_ d_lut_sky130_fd_sc_hd__nand2_1
+A_244_ [count1_1_ count0_1_] _7_ d_lut_sky130_fd_sc_hd__nor2_1
+A_245_ [_6_ _7_ _5_] _8_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_246_ [count1_2_ count0_2_] _9_ d_lut_sky130_fd_sc_hd__nor2_1
+A_247_ [_9_ _215_] _10_ d_lut_sky130_fd_sc_hd__nor2_1
+A_248_ [_213_ _212_] _11_ d_lut_sky130_fd_sc_hd__nor2_1
+A_249_ [_10_ _11_ _8_] _12_ d_lut_sky130_fd_sc_hd__nand3_1
+A_250_ [_12_ _216_ _211_] _13_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_251_ [_209_ _210_ _216_ _12_] _14_ d_lut_sky130_fd_sc_hd__o211a_1
+A_252_ [_14_ _13_ div_4_] _15_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_253_ [div_4_] _16_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_254_ [_211_ _12_ _216_] _17_ d_lut_sky130_fd_sc_hd__nand3_1
+A_255_ [_17_ _16_ _209_] _18_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_256_ [_15_ _18_] _19_ d_lut_sky130_fd_sc_hd__nand2_1
+A_257_ [div_3_] _20_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_258_ [_215_] _21_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_259_ [_10_ _8_] _22_ d_lut_sky130_fd_sc_hd__nand2_1
+A_260_ [_212_ _213_ _21_ _22_] _23_ d_lut_sky130_fd_sc_hd__o211ai_1
+A_261_ [_6_ _7_ _5_] _24_ d_lut_sky130_fd_sc_hd__o21a_1
+A_262_ [_9_ _24_ _215_] _25_ d_lut_sky130_fd_sc_hd__o21bai_1
+A_263_ [_25_ _11_] _26_ d_lut_sky130_fd_sc_hd__nand2_1
+A_264_ [_26_ _20_ _23_] _27_ d_lut_sky130_fd_sc_hd__nand3_1
+A_265_ [div_2_ _8_ _10_] _28_ d_lut_sky130_fd_sc_hd__xnor3_4
+A_266_ [_22_ _21_ _11_] _29_ d_lut_sky130_fd_sc_hd__nand3_1
+A_267_ [_21_ _22_ _212_ _213_] _30_ d_lut_sky130_fd_sc_hd__o2bb2ai_1
+A_268_ [_30_ div_3_ _29_] _31_ d_lut_sky130_fd_sc_hd__nand3_1
+A_269_ [div_0_] _32_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_270_ [count1_0_ count0_0_] _33_ d_lut_sky130_fd_sc_hd__xor2_1
+A_271_ [_33_ _32_] _34_ d_lut_sky130_fd_sc_hd__and2_2
+A_272_ [div_1_] _35_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_273_ [count1_1_ count0_1_] _36_ d_lut_sky130_fd_sc_hd__or2_2
+A_274_ [_36_ _5_] _37_ d_lut_sky130_fd_sc_hd__nand2_1
+A_275_ [_35_ _6_ _37_] _38_ d_lut_sky130_fd_sc_hd__xnor3_4
+A_276_ [_32_ _33_] _39_ d_lut_sky130_fd_sc_hd__nor2_1
+A_277_ [_34_ _39_ _38_] _40_ d_lut_sky130_fd_sc_hd__nor3_1
+A_278_ [_40_ _27_ _28_ _31_] _41_ d_lut_sky130_fd_sc_hd__nand4_1
+A_279_ [_41_ _19_] _42_ d_lut_sky130_fd_sc_hd__or2_2
+A_280_ [_36_ count1_0_ count0_0_ _5_] _43_ d_lut_sky130_fd_sc_hd__nand4_1
+A_281_ [count1_1_ count0_1_] _44_ d_lut_sky130_fd_sc_hd__and2_2
+A_282_ [_7_ _44_ _6_] _45_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_283_ [_45_ _43_ _35_] _46_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_284_ [_45_ _43_ _35_] _47_ d_lut_sky130_fd_sc_hd__nand3_1
+A_285_ [_33_ _32_] _48_ d_lut_sky130_fd_sc_hd__nand2_1
+A_286_ [_47_ _48_ _46_] _49_ d_lut_sky130_fd_sc_hd__a21o_2
+A_287_ [_27_ _31_ _28_ _49_] _50_ d_lut_sky130_fd_sc_hd__nand4_1
+A_288_ [_215_ _9_ _24_] _51_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_289_ [_51_ _22_ div_2_] _52_ d_lut_sky130_fd_sc_hd__a21boi_0
+A_290_ [_27_ _52_] _53_ d_lut_sky130_fd_sc_hd__nand2_1
+A_291_ [_50_ _31_ _53_ _19_] _54_ d_lut_sky130_fd_sc_hd__a31oi_1
+A_292_ [_12_ div_4_ _210_ _216_] _55_ d_lut_sky130_fd_sc_hd__nand4_1
+A_293_ [_55_] _56_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_294_ [tval_0_ tval_1_] _57_ d_lut_sky130_fd_sc_hd__nor2_1
+A_295_ [_197_ _57_] _58_ d_lut_sky130_fd_sc_hd__nand2_1
+A_296_ [_58_] _59_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_297_ [tval_0_ _59_ _56_ _54_ _42_] _60_ d_lut_sky130_fd_sc_hd__o221ai_1
+A_298_ [_15_ _18_] _61_ d_lut_sky130_fd_sc_hd__and2_2
+A_299_ [_50_ _31_ _53_] _62_ d_lut_sky130_fd_sc_hd__nand3_1
+A_300_ [_62_ _61_] _63_ d_lut_sky130_fd_sc_hd__nand2_1
+A_301_ [tint_4_] _64_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_302_ [tval_0_ tval_1_] _65_ d_lut_sky130_fd_sc_hd__nand2_1
+A_303_ [tint_1_ tint_0_] _66_ d_lut_sky130_fd_sc_hd__nand2_1
+A_304_ [_65_ _66_] _67_ d_lut_sky130_fd_sc_hd__nor2_1
+A_305_ [_67_ tint_3_ tint_2_] _68_ d_lut_sky130_fd_sc_hd__nand3_1
+A_306_ [_64__bF$buf3 _68_] _69_ d_lut_sky130_fd_sc_hd__nor2_1
+A_307_ [_69_] _70_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_308_ [_63_ tval_0_ _55_ _70_] _71_ d_lut_sky130_fd_sc_hd__nand4_1
+A_309_ [tval_0_ _42_ _206_ _71_ _60_] _72_ d_lut_sky130_fd_sc_hd__o2111ai_1
+A_310_ [_198_ _206_ _72_] _3__0_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_311_ [tval_1_] _73_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_312_ [_65_] _74_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_313_ [_57_ _74_] _75_ d_lut_sky130_fd_sc_hd__nor2_1
+A_314_ [_59_ _75_ _56_ _54_ _42_] _76_ d_lut_sky130_fd_sc_hd__o221ai_1
+A_315_ [_75_ _69_] _77_ d_lut_sky130_fd_sc_hd__nor2_1
+A_316_ [_63_ _55_ _77_] _78_ d_lut_sky130_fd_sc_hd__nand3_1
+A_317_ [tval_1_ _42_ _206_ _78_ _76_] _79_ d_lut_sky130_fd_sc_hd__o2111ai_1
+A_318_ [_73_ _206_ _79_] _3__1_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_319_ [tint_0_] _80_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_320_ [_206_] _81_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_321_ [_62_ _61_ _56_] _82_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_322_ [_80_ _65_] _83_ d_lut_sky130_fd_sc_hd__nor2_1
+A_323_ [tint_0_ _74_] _84_ d_lut_sky130_fd_sc_hd__nor2_1
+A_324_ [_83_ _84_ _70_] _85_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_325_ [_82_ _85_ _81_] _86_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_326_ [_63_ _55_] _87_ d_lut_sky130_fd_sc_hd__nand2_1
+A_327_ [_41_ _19_] _88_ d_lut_sky130_fd_sc_hd__nor2_1
+A_328_ [_57_ _80_] _89_ d_lut_sky130_fd_sc_hd__nand2_1
+A_329_ [_57_] _90_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_330_ [_90_ tint_0_] _91_ d_lut_sky130_fd_sc_hd__nand2_1
+A_331_ [_91_ _89_ _197_] _92_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_332_ [_88_ _80_] _93_ d_lut_sky130_fd_sc_hd__nand2_1
+A_333_ [_88_ _92_ _93_ _87_] _94_ d_lut_sky130_fd_sc_hd__o211ai_1
+A_334_ [_80_ _81_ _86_ _94_] _3__2_ d_lut_sky130_fd_sc_hd__a22oi_1
+A_335_ [tint_1_] _95_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_336_ [tint_1_ _83_] _96_ d_lut_sky130_fd_sc_hd__nor2_1
+A_337_ [_67_ _96_ _70_] _97_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_338_ [_82_ _97_ _81_] _98_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_339_ [_194_ _57_] _99_ d_lut_sky130_fd_sc_hd__nand2_1
+A_340_ [_89_ tint_1_] _100_ d_lut_sky130_fd_sc_hd__nand2_1
+A_341_ [_99_ _100_ _59_] _101_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_342_ [_88_ _95_] _102_ d_lut_sky130_fd_sc_hd__nand2_1
+A_343_ [_88_ _101_ _102_ _87_] _103_ d_lut_sky130_fd_sc_hd__o211ai_1
+A_344_ [_95_ _81_ _98_ _103_] _3__3_ d_lut_sky130_fd_sc_hd__a22oi_1
+A_345_ [tint_2_] _104_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_346_ [_194_ _57_ _104_] _105_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_347_ [tint_2_ _99_] _106_ d_lut_sky130_fd_sc_hd__nor2_1
+A_348_ [_106_ _105_ _58_] _107_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_349_ [_88_ tint_2_] _108_ d_lut_sky130_fd_sc_hd__nand2_1
+A_350_ [_107_ _88_ _56_ _54_ _108_] _109_ d_lut_sky130_fd_sc_hd__o221ai_1
+A_351_ [_67_ tint_2_] _110_ d_lut_sky130_fd_sc_hd__nand2_1
+A_352_ [_65_ _66_ _104_] _111_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_353_ [_111_ _110_ _69_] _112_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_354_ [_63_ _55_ _112_] _113_ d_lut_sky130_fd_sc_hd__nand3_1
+A_355_ [_109_ _206_ _113_] _114_ d_lut_sky130_fd_sc_hd__nand3_1
+A_356_ [_104_ _206_ _114_] _3__4_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_357_ [tint_3_] _115_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_358_ [tint_4_ _68_] _116_ d_lut_sky130_fd_sc_hd__nor2_1
+A_359_ [_115_ _110_ _116_] _117_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_360_ [_82_ _117_ _81_] _118_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_361_ [_90_ _196_] _119_ d_lut_sky130_fd_sc_hd__nor2_1
+A_362_ [_115_ _106_] _120_ d_lut_sky130_fd_sc_hd__nor2_1
+A_363_ [_119_ _120_] _121_ d_lut_sky130_fd_sc_hd__nor2_1
+A_364_ [_59_ _121_] _122_ d_lut_sky130_fd_sc_hd__nor2_1
+A_365_ [_88_ _115_] _123_ d_lut_sky130_fd_sc_hd__nand2_1
+A_366_ [_88_ _122_ _123_ _87_] _124_ d_lut_sky130_fd_sc_hd__o211ai_1
+A_367_ [_115_ _81_ _118_ _124_] _3__5_ d_lut_sky130_fd_sc_hd__a22oi_1
+A_368_ [_56_ _54_ _206_ _119_ _42_] _125_ d_lut_sky130_fd_sc_hd__o2111a_1
+A_369_ [_68_ _64__bF$buf2] _126_ d_lut_sky130_fd_sc_hd__nand2_1
+A_370_ [_206_ _126_] _127_ d_lut_sky130_fd_sc_hd__nand2_1
+A_371_ [_87_ _127_ _64__bF$buf1 _125_] _3__6_ d_lut_sky130_fd_sc_hd__o22ai_1
+A_372_ [prep_0_ _203_] _2__0_ d_lut_sky130_fd_sc_hd__or2_2
+A_373_ [prep_1_] _128_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_374_ [_128_ _203_ _204_] _2__1_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_375_ [_202_ prep_2_] _129_ d_lut_sky130_fd_sc_hd__nand2_1
+A_376_ [_128_ _202_ _129_] _2__2_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_377_ [count0_0_] _130_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_378_ [_202_ count1_0_] _131_ d_lut_sky130_fd_sc_hd__nand2_1
+A_379_ [_130_ _202_ _131_] _1__0_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_380_ [count0_1_] _132_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_381_ [_202_ count1_1_] _133_ d_lut_sky130_fd_sc_hd__nand2_1
+A_382_ [_132_ _202_ _133_] _1__1_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_383_ [count0_2_] _134_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_384_ [_202_ count1_2_] _135_ d_lut_sky130_fd_sc_hd__nand2_1
+A_385_ [_134_ _202_ _135_] _1__2_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_386_ [_203_ count0_3_] _136_ d_lut_sky130_fd_sc_hd__nand2_1
+A_387_ [_202_ count1_3_] _137_ d_lut_sky130_fd_sc_hd__nand2_1
+A_388_ [_136_ _137_] _1__3_ d_lut_sky130_fd_sc_hd__nand2_1
+A_389_ [_202_ count1_4_] _138_ d_lut_sky130_fd_sc_hd__nand2_1
+A_390_ [_208_ _202_ _138_] _1__4_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_391_ [_132_ _130_] _139_ d_lut_sky130_fd_sc_hd__nor2_1
+A_392_ [_139_] _140_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_393_ [_134_ _140_] _141_ d_lut_sky130_fd_sc_hd__nor2_1
+A_394_ [_141_ count0_3_] _142_ d_lut_sky130_fd_sc_hd__nand2_1
+A_395_ [_142_] _143_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_396_ [_143_ count0_4_] _144_ d_lut_sky130_fd_sc_hd__nand2_1
+A_397_ [_144_ count0_0_ _202_] _0__0_ d_lut_sky130_fd_sc_hd__nand3_1
+A_398_ [_132_ _130_] _145_ d_lut_sky130_fd_sc_hd__nand2_1
+A_399_ [_140_ _145_] _146_ d_lut_sky130_fd_sc_hd__nand2_1
+A_400_ [_144_ _146_ _203_] _0__1_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_401_ [_134_ _139_] _147_ d_lut_sky130_fd_sc_hd__xor2_1
+A_402_ [_144_ _147_ _203_] _0__2_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_403_ [count0_3_ _141_ _202_] _148_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_404_ [_143_ _208_ _148_] _0__3_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_405_ [_142_ _208_ _203_] _0__4_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_406_ [tint_3_ tint_2_] _149_ d_lut_sky130_fd_sc_hd__nand2_1
+A_407_ [_149_ _64__bF$buf0] _217__1_ d_lut_sky130_fd_sc_hd__nand2_1
+A_408_ [tint_3_ _104_] _150_ d_lut_sky130_fd_sc_hd__nor2_1
+A_409_ [_150_] _151_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_410_ [_66_ _151_] _152_ d_lut_sky130_fd_sc_hd__nor2_1
+A_411_ [_195_ tint_1_ _80_ _64__bF$buf3] _153_ d_lut_sky130_fd_sc_hd__nand4_1
+A_412_ [_195_] _154_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_413_ [tint_4_ _154_] _155_ d_lut_sky130_fd_sc_hd__nor2_1
+A_414_ [_155_ _95_] _217__6_ d_lut_sky130_fd_sc_hd__nand2_1
+A_415_ [_217__6_ _153_] _156_ d_lut_sky130_fd_sc_hd__nand2_1
+A_416_ [_80_ _64__bF$buf2 tint_1_] _157_ d_lut_sky130_fd_sc_hd__nand3_1
+A_417_ [_157_ _151_] _158_ d_lut_sky130_fd_sc_hd__nor2_1
+A_418_ [_158_] _159_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_419_ [_66_ _154_] _160_ d_lut_sky130_fd_sc_hd__nor2_1
+A_420_ [_95_ _150_ _160_] _161_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_421_ [tint_4_ _161_ _159_] _162_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_422_ [_156_ _162_] _217__5_ d_lut_sky130_fd_sc_hd__nor2_1
+A_423_ [_217__5_] _163_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_424_ [_64__bF$buf1 _152_ _163_] _217__2_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_425_ [_155_] _217__3_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_426_ [_95_ tint_0_] _164_ d_lut_sky130_fd_sc_hd__nand2_1
+A_427_ [_104_ tint_3_] _165_ d_lut_sky130_fd_sc_hd__nand2_1
+A_428_ [_164_ _165_] _166_ d_lut_sky130_fd_sc_hd__nor2_1
+A_429_ [_166_ _64__bF$buf0] _167_ d_lut_sky130_fd_sc_hd__nand2_1
+A_430_ [_152_ _64__bF$buf3] _168_ d_lut_sky130_fd_sc_hd__nand2_1
+A_431_ [_194_] _169_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_432_ [_165_ _169_] _170_ d_lut_sky130_fd_sc_hd__nor2_1
+A_433_ [_170_ _64__bF$buf2] _171_ d_lut_sky130_fd_sc_hd__nand2_1
+A_434_ [_168_ _171_] _172_ d_lut_sky130_fd_sc_hd__nand2_1
+A_435_ [_172_ _163_] _217__9_ d_lut_sky130_fd_sc_hd__nor2_1
+A_436_ [_217__9_ _167_] _173_ d_lut_sky130_fd_sc_hd__nand2_1
+A_437_ [_173_] _217__4_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_438_ [tint_4_ _149_ _169_] _174_ d_lut_sky130_fd_sc_hd__nor3_1
+A_439_ [tint_4_ _66_ _165_] _175_ d_lut_sky130_fd_sc_hd__nor3_1
+A_440_ [_165_ _157_] _176_ d_lut_sky130_fd_sc_hd__nor2_1
+A_441_ [_174_ _175_ _176_ _173_] _217__7_ d_lut_sky130_fd_sc_hd__nor4_1
+A_442_ [_104_ _194_ _115_ _64__bF$buf1] _217__8_ d_lut_sky130_fd_sc_hd__o211ai_1
+A_443_ [_156_] _217__10_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_444_ [_176_ _173_] _217__11_ d_lut_sky130_fd_sc_hd__nor2_1
+A_445_ [tint_4_ _161_] _177_ d_lut_sky130_fd_sc_hd__nor2_1
+A_446_ [_156_ _177_] _217__12_ d_lut_sky130_fd_sc_hd__nor2_1
+A_447_ [_217__9_] _178_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_448_ [_175_ _174_] _179_ d_lut_sky130_fd_sc_hd__nor2_1
+A_449_ [_179_ _167_] _180_ d_lut_sky130_fd_sc_hd__nand2_1
+A_450_ [tint_4_ _149_ _164_ _157_ _165_] _181_ d_lut_sky130_fd_sc_hd__o32ai_1
+A_451_ [_180_ _181_ _178_] _217__13_ d_lut_sky130_fd_sc_hd__nor3_1
+A_452_ [_95_ _80_ _104_ _115_ _64__bF$buf0] _217__14_ d_lut_sky130_fd_sc_hd__a311oi_1
+A_453_ [_154_ _66_ _169_ _151_] _182_ d_lut_sky130_fd_sc_hd__o22ai_1
+A_454_ [tint_4_ _95_ _149_] _183_ d_lut_sky130_fd_sc_hd__nor3_1
+A_455_ [tint_4_ _195_ _66_ _183_] _184_ d_lut_sky130_fd_sc_hd__a31oi_1
+A_456_ [_184_] _185_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_457_ [_181_ _185_] _186_ d_lut_sky130_fd_sc_hd__nor2_1
+A_458_ [_217__9_ _167_ _179_ _186_] _187_ d_lut_sky130_fd_sc_hd__nand4_1
+A_459_ [tint_4_ _182_ _187_] _217__15_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_460_ [_194_ _195_ _64__bF$buf3] _217__16_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_461_ [_64__bF$buf2 _161_] _188_ d_lut_sky130_fd_sc_hd__nor2_1
+A_462_ [_95_ tint_0_ _64__bF$buf1 _151_] _189_ d_lut_sky130_fd_sc_hd__nor4_1
+A_463_ [_188_ _189_ _187_] _217__17_ d_lut_sky130_fd_sc_hd__nor3_1
+A_464_ [_64__bF$buf0 _195_] _217__18_ d_lut_sky130_fd_sc_hd__nor2_1
+A_465_ [_149_ _66_ _64__bF$buf3] _217__19_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_466_ [_150_ _160_ tint_4_] _190_ d_lut_sky130_fd_sc_hd__o21ai_0
+A_467_ [_186_ _179_ _190_] _191_ d_lut_sky130_fd_sc_hd__nand3_1
+A_468_ [_170_ tint_4_ _166_] _192_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_469_ [_192_ _153_ _217__6_] _193_ d_lut_sky130_fd_sc_hd__nand3_1
+A_470_ [_172_ _193_ _162_ _191_] _217__20_ d_lut_sky130_fd_sc_hd__nor4_1
+A_471_ [_195_ _95_ _64__bF$buf2] _217__21_ d_lut_sky130_fd_sc_hd__a21oi_1
+A_472_ [_188_ _187_] _217__22_ d_lut_sky130_fd_sc_hd__nor2_1
+A_473_ [_191_ _173_] _217__24_ d_lut_sky130_fd_sc_hd__nor2_1
+A_474_ [_187_] _217__25_ d_lut_sky130_fd_sc_hd__clkinv_1
+A_475_ [reset] _4_ d_lut_sky130_fd_sc_hd__clkinv_2
+A_476_ [tint_4_] trim_23_ d_lut_sky130_fd_sc_hd__buf_2
+A_477_ [_217__0_] trim_0_ d_lut_sky130_fd_sc_hd__buf_2
+A_478_ [_217__1_] trim_1_ d_lut_sky130_fd_sc_hd__buf_2
+A_479_ [_217__2_] trim_2_ d_lut_sky130_fd_sc_hd__buf_2
+A_480_ [_217__3_] trim_3_ d_lut_sky130_fd_sc_hd__buf_2
+A_481_ [_217__4_] trim_4_ d_lut_sky130_fd_sc_hd__buf_2
+A_482_ [_217__5_] trim_5_ d_lut_sky130_fd_sc_hd__buf_2
+A_483_ [_217__6_] trim_6_ d_lut_sky130_fd_sc_hd__buf_2
+A_484_ [_217__7_] trim_7_ d_lut_sky130_fd_sc_hd__buf_2
+A_485_ [_217__8_] trim_8_ d_lut_sky130_fd_sc_hd__buf_2
+A_486_ [_217__9_] trim_9_ d_lut_sky130_fd_sc_hd__buf_2
+A_487_ [_217__10_] trim_10_ d_lut_sky130_fd_sc_hd__buf_2
+A_488_ [_217__11_] trim_11_ d_lut_sky130_fd_sc_hd__buf_2
+A_489_ [_217__12_] trim_12_ d_lut_sky130_fd_sc_hd__buf_2
+A_490_ [_217__13_] trim_13_ d_lut_sky130_fd_sc_hd__buf_2
+A_491_ [_217__14_] trim_14_ d_lut_sky130_fd_sc_hd__buf_2
+A_492_ [_217__15_] trim_15_ d_lut_sky130_fd_sc_hd__buf_2
+A_493_ [_217__16_] trim_16_ d_lut_sky130_fd_sc_hd__buf_2
+A_494_ [_217__17_] trim_17_ d_lut_sky130_fd_sc_hd__buf_2
+A_495_ [_217__18_] trim_18_ d_lut_sky130_fd_sc_hd__buf_2
+A_496_ [_217__19_] trim_19_ d_lut_sky130_fd_sc_hd__buf_2
+A_497_ [_217__20_] trim_20_ d_lut_sky130_fd_sc_hd__buf_2
+A_498_ [_217__21_] trim_21_ d_lut_sky130_fd_sc_hd__buf_2
+A_499_ [_217__22_] trim_22_ d_lut_sky130_fd_sc_hd__buf_2
+A_500_ [_217__24_] trim_24_ d_lut_sky130_fd_sc_hd__buf_2
+A_501_ [_217__25_] trim_25_ d_lut_sky130_fd_sc_hd__buf_2
+A_502_ _0__0_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_503_ _0__1_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_504_ _0__2_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+A_505_ _0__3_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop
+A_506_ _0__4_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_507_ _1__0_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_508_ _1__1_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+A_509_ _1__2_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop
+A_510_ _1__3_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_511_ _1__4_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_512_ osc clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+A_513_ oscbuf_0_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop
+A_514_ oscbuf_1_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_515_ _2__0_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_516_ _2__1_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+A_517_ _2__2_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop
+A_518_ _3__0_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_519_ _3__1_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_520_ _3__2_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+A_521_ _3__3_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop
+A_522_ _3__4_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop
+A_523_ _3__5_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop
+A_524_ _3__6_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop
+
+.model todig_1v95 adc_bridge(in_high=1.3 in_low=0.65 rise_delay=500p fall_delay=500p)
+.model toana_1v95 dac_bridge(out_high=1.95 out_low=0)
+
+.model ddflop d_dff(ic=0 rise_delay=50p fall_delay=50p)
+.model dzero d_pulldown(load=250f)
+.model done d_pullup(load=250f)
+
+AA2D1 [a_VPB] [VPB] todig_1v95
+AA2D2 [a_VGND] [VGND] todig_1v95
+AA2D3 [a_clock] [clock] todig_1v95
+AA2D4 [a_div_0_] [div_0_] todig_1v95
+AA2D5 [a_div_1_] [div_1_] todig_1v95
+AA2D6 [a_div_2_] [div_2_] todig_1v95
+AA2D7 [a_div_3_] [div_3_] todig_1v95
+AA2D8 [a_div_4_] [div_4_] todig_1v95
+AA2D9 [a_osc] [osc] todig_1v95
+AA2D10 [a_reset] [reset] todig_1v95
+AD2A1 [trim_0_] [a_trim_0_] toana_1v95
+AD2A2 [trim_1_] [a_trim_1_] toana_1v95
+AD2A3 [trim_2_] [a_trim_2_] toana_1v95
+AD2A4 [trim_3_] [a_trim_3_] toana_1v95
+AD2A5 [trim_4_] [a_trim_4_] toana_1v95
+AD2A6 [trim_5_] [a_trim_5_] toana_1v95
+AD2A7 [trim_6_] [a_trim_6_] toana_1v95
+AD2A8 [trim_7_] [a_trim_7_] toana_1v95
+AD2A9 [trim_8_] [a_trim_8_] toana_1v95
+AD2A10 [trim_9_] [a_trim_9_] toana_1v95
+AD2A11 [trim_10_] [a_trim_10_] toana_1v95
+AD2A12 [trim_11_] [a_trim_11_] toana_1v95
+AD2A13 [trim_12_] [a_trim_12_] toana_1v95
+AD2A14 [trim_13_] [a_trim_13_] toana_1v95
+AD2A15 [trim_14_] [a_trim_14_] toana_1v95
+AD2A16 [trim_15_] [a_trim_15_] toana_1v95
+AD2A17 [trim_16_] [a_trim_16_] toana_1v95
+AD2A18 [trim_17_] [a_trim_17_] toana_1v95
+AD2A19 [trim_18_] [a_trim_18_] toana_1v95
+AD2A20 [trim_19_] [a_trim_19_] toana_1v95
+AD2A21 [trim_20_] [a_trim_20_] toana_1v95
+AD2A22 [trim_21_] [a_trim_21_] toana_1v95
+AD2A23 [trim_22_] [a_trim_22_] toana_1v95
+AD2A24 [trim_23_] [a_trim_23_] toana_1v95
+AD2A25 [trim_24_] [a_trim_24_] toana_1v95
+AD2A26 [trim_25_] [a_trim_25_] toana_1v95
+
+.ends
+
+* sky130_fd_sc_hd__nand2_2 (!A) | (!B)
+.model d_lut_sky130_fd_sc_hd__nand2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1110")
+* sky130_fd_sc_hd__inv_2 (!A)
+.model d_lut_sky130_fd_sc_hd__inv_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10")
+* sky130_fd_sc_hd__nor2_2 (!A&!B)
+.model d_lut_sky130_fd_sc_hd__nor2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1000")
+* sky130_fd_sc_hd__conb_1 1
+* sky130_fd_sc_hd__buf_1 (A)
+.model d_lut_sky130_fd_sc_hd__buf_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "01")
+* sky130_fd_sc_hd__clkbuf_1 (A)
+.model d_lut_sky130_fd_sc_hd__clkbuf_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "01")
+* sky130_fd_sc_hd__nor2_1 (!A&!B)
+.model d_lut_sky130_fd_sc_hd__nor2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1000")
+* sky130_fd_sc_hd__nand2_1 (!A) | (!B)
+.model d_lut_sky130_fd_sc_hd__nand2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1110")
+* sky130_fd_sc_hd__clkinv_1 (!A)
+.model d_lut_sky130_fd_sc_hd__clkinv_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10")
+* sky130_fd_sc_hd__or2_2 (A) | (B)
+.model d_lut_sky130_fd_sc_hd__or2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "0111")
+* sky130_fd_sc_hd__and2_2 (A&B)
+.model d_lut_sky130_fd_sc_hd__and2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "0001")
+* sky130_fd_sc_hd__a21oi_1 (!A1&!B1) | (!A2&!B1)
+.model d_lut_sky130_fd_sc_hd__a21oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11100000")
+* sky130_fd_sc_hd__o21ai_0 (!A1&!A2) | (!B1)
+.model d_lut_sky130_fd_sc_hd__o21ai_0 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111000")
+* sky130_fd_sc_hd__nand3_1 (!A) | (!B) | (!C)
+.model d_lut_sky130_fd_sc_hd__nand3_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111110")
+* sky130_fd_sc_hd__o211a_1 (A1&B1&C1) | (A2&B1&C1)
+.model d_lut_sky130_fd_sc_hd__o211a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "0000000000000111")
+* sky130_fd_sc_hd__o211ai_1 (!A1&!A2) | (!B1) | (!C1)
+.model d_lut_sky130_fd_sc_hd__o211ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1111111111111000")
+* sky130_fd_sc_hd__o21a_1 (A1&B1) | (A2&B1)
+.model d_lut_sky130_fd_sc_hd__o21a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "00000111")
+* sky130_fd_sc_hd__o21bai_1 (!A1&!A2) | (B1_N)
+.model d_lut_sky130_fd_sc_hd__o21bai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10001111")
+* sky130_fd_sc_hd__xnor3_4 (!A&!B&!C) | (A&B&!C) | (A&!B&C) | (!A&B&C)
+.model d_lut_sky130_fd_sc_hd__xnor3_4 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10010110")
+* sky130_fd_sc_hd__o2bb2ai_1 (!B1&!B2) | (A1_N&A2_N)
+.model d_lut_sky130_fd_sc_hd__o2bb2ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1111000100010001")
+* sky130_fd_sc_hd__xor2_1 (A&!B) | (!A&B)
+.model d_lut_sky130_fd_sc_hd__xor2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "0110")
+* sky130_fd_sc_hd__nor3_1 (!A&!B&!C)
+.model d_lut_sky130_fd_sc_hd__nor3_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10000000")
+* sky130_fd_sc_hd__nand4_1 (!A) | (!B) | (!C) | (!D)
+.model d_lut_sky130_fd_sc_hd__nand4_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1111111111111110")
+* sky130_fd_sc_hd__a21o_2 (A1&A2) | (B1)
+.model d_lut_sky130_fd_sc_hd__a21o_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "00011111")
+* sky130_fd_sc_hd__a21boi_0 (!A1&B1_N) | (!A2&B1_N)
+.model d_lut_sky130_fd_sc_hd__a21boi_0 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "00001110")
+* sky130_fd_sc_hd__a31oi_1 (!A1&!B1) | (!A2&!B1) | (!A3&!B1)
+.model d_lut_sky130_fd_sc_hd__a31oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1111111000000000")
+* sky130_fd_sc_hd__o221ai_1 (!B1&!B2) | (!A1&!A2) | (!C1)
+.model d_lut_sky130_fd_sc_hd__o221ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111111111111111111100010001000")
+* sky130_fd_sc_hd__o2111ai_1 (!A1&!A2) | (!B1) | (!C1) | (!D1)
+.model d_lut_sky130_fd_sc_hd__o2111ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111111111111111111111111111000")
+* sky130_fd_sc_hd__a22oi_1 (!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A2&!B2)
+.model d_lut_sky130_fd_sc_hd__a22oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1110111011100000")
+* sky130_fd_sc_hd__o2111a_1 (A1&B1&C1&D1) | (A2&B1&C1&D1)
+.model d_lut_sky130_fd_sc_hd__o2111a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "00000000000000000000000000000111")
+* sky130_fd_sc_hd__o22ai_1 (!B1&!B2) | (!A1&!A2)
+.model d_lut_sky130_fd_sc_hd__o22ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1111100010001000")
+* sky130_fd_sc_hd__nor4_1 (!A&!B&!C&!D)
+.model d_lut_sky130_fd_sc_hd__nor4_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "1000000000000000")
+* sky130_fd_sc_hd__o32ai_1 (!A1&!A2&!A3) | (!B1&!B2)
+.model d_lut_sky130_fd_sc_hd__o32ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111111100000001000000010000000")
+* sky130_fd_sc_hd__a311oi_1 (!A1&!B1&!C1) | (!A2&!B1&!C1) | (!A3&!B1&!C1)
+.model d_lut_sky130_fd_sc_hd__a311oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "11111110000000000000000000000000")
+* sky130_fd_sc_hd__clkinv_2 (!A)
+.model d_lut_sky130_fd_sc_hd__clkinv_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "10")
+* sky130_fd_sc_hd__buf_2 (A)
+.model d_lut_sky130_fd_sc_hd__buf_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f
++ table_values "01")
+* sky130_fd_sc_hd__dfrtp_2 IQ
+* sky130_fd_sc_hd__dfrtp_1 IQ
+* sky130_fd_sc_hd__dfrtp_4 IQ
+* sky130_fd_sc_hd__diode_2 (no function)
+.end
diff --git a/ngspice/digital_pll/digital_pll/digital_pll_tb.spice b/ngspice/digital_pll/digital_pll/digital_pll_tb.spice
new file mode 100644
index 0000000..c3d89ce
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/digital_pll_tb.spice
@@ -0,0 +1,64 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Complete Digital PLL testbench
+*--------------------------------
+
+.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
+
+.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+
+.include "digital_pll.spice"
+
+.option TEMP=27
+* .option RELTOL=1.0E-2
+
+* Instantiate the digital PLL
+
+X0 vdd vss reset osc clkp1 clkp0 div4 div3 div2 div1 div0 digital_pll
+
+* Power supply (note that all logic is 1.8V here)
+
+V0 vdd vss PWL(0.0 0.0 25n 1.8)
+V1 vss 0 0.0
+
+* Fixed divider value (connect resistors to power or ground)
+* divider value = 16 (10MHz * 16 = 160MHz clock)
+
+R0 div4 vdd 1
+R1 div3 gnd 1
+R2 div2 gnd 1
+R3 div1 gnd 1
+R4 div0 gnd 1
+
+* Run oscillator at 10MHz
+* Because DFFs don't handle reclocking well, keep the edges sharp.
+
+V2 osc vss PULSE(0.0 1.8 5n 10p 10p 50n 100n)
+
+* Reset pulse
+V3 reset vss PWL(0.0 1.8 0.1u 1.8 0.101u 0.0)
+
+* Transient analysis. Note that trim updates every four cycles, or about
+* three updates per microsecond. To update all 17 trim bits requires
+* 6us.
+
+.control
+tran 1n 8u
+plot V(osc)
+plot V(clkp0) V(clkp1)
+.endc
+.end
diff --git a/ngspice/digital_pll/digital_pll/inverter_tb.spi b/ngspice/digital_pll/digital_pll/inverter_tb.spi
new file mode 100644
index 0000000..36d5c18
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/inverter_tb.spi
@@ -0,0 +1,37 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Simple testbench mainly to check SPICE model conversion from CDL
+* Plots the transient response of the smallest inverter in the HD standard cell library
+
+.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
+.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+
+* .option TEMP=27
+
+X0 in vss vss vdd vdd out sky130_fd_sc_hd__inv_1
+
+V0 vdd vss PWL(0n 0.0 30n 1.8)
+V1 vss 0 0.0
+
+Vin in vss PWL(0n 0.0 100n 0.0 500n 1.8)
+
+* Transient analysis
+.control
+tran 1n 1u
+plot V(in) V(out)
+.endc
+.end
diff --git a/ngspice/digital_pll/digital_pll/ring_osc2x13.spice b/ngspice/digital_pll/digital_pll/ring_osc2x13.spice
new file mode 100644
index 0000000..5553f2c
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/ring_osc2x13.spice
@@ -0,0 +1,264 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* SPICE netlist created from verilog structural netlist module ring_osc2x13 by vlog2Spice (qflow)
+* Warning: This file contains <> array delimiters in net names_
+* Note: Library sky130_fd_sc_hd_spice has been removed; reference library as an
+* include file from the testbench instead_
+
+.subckt ring_osc2x13 VPB VGND clockp<0> clockp<1> reset trim<0> trim<1>
++ trim<2> trim<3> trim<4> trim<5> trim<6> trim<7> trim<8> trim<9>
++ trim<10> trim<11> trim<12> trim<13> trim<14> trim<15> trim<16> trim<17>
++ trim<18> trim<19> trim<20> trim<21> trim<22> trim<23> trim<24> trim<25>
++
+
+X_1_ _0_<0> VGND VGND VPB VPB clockp<0> sky130_fd_sc_hd__buf_2
+X_2_ _0_<1> VGND VGND VPB VPB clockp<1> sky130_fd_sc_hd__buf_2
+Xdstage<0>_id_delaybuf0 dstage<0>_id_in VGND VGND VPB VPB dstage<0>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<0>_id_delaybuf1 dstage<0>_id_ts VGND VGND VPB VPB dstage<0>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<0>_id_delayen0 dstage<0>_id_d2 trim<0> VGND VGND VPB VPB
++ dstage<0>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<0>_id_delayen1 dstage<0>_id_d0 trim<13> VGND VGND VPB VPB
++ dstage<0>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<0>_id_delayenb0 dstage<0>_id_ts trim<0> VGND VGND VPB VPB
++ dstage<0>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<0>_id_delayenb1 dstage<0>_id_ts trim<13> VGND VGND VPB VPB
++ dstage<0>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<0>_id_delayint0 dstage<0>_id_d1 VGND VGND VPB VPB dstage<0>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<10>_id_delaybuf0 dstage<10>_id_in VGND VGND VPB VPB dstage<10>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<10>_id_delaybuf1 dstage<10>_id_ts VGND VGND VPB VPB dstage<10>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<10>_id_delayen0 dstage<10>_id_d2 trim<10> VGND VGND VPB VPB
++ dstage<10>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<10>_id_delayen1 dstage<10>_id_d0 trim<23> VGND VGND VPB VPB
++ dstage<10>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<10>_id_delayenb0 dstage<10>_id_ts trim<10> VGND VGND VPB VPB
++ dstage<10>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<10>_id_delayenb1 dstage<10>_id_ts trim<23> VGND VGND VPB VPB
++ dstage<10>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<10>_id_delayint0 dstage<10>_id_d1 VGND VGND VPB VPB dstage<10>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<11>_id_delaybuf0 dstage<10>_id_out VGND VGND VPB VPB dstage<11>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<11>_id_delaybuf1 dstage<11>_id_ts VGND VGND VPB VPB dstage<11>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<11>_id_delayen0 dstage<11>_id_d2 trim<11> VGND VGND VPB VPB
++ dstage<11>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<11>_id_delayen1 dstage<11>_id_d0 trim<24> VGND VGND VPB VPB
++ dstage<11>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<11>_id_delayenb0 dstage<11>_id_ts trim<11> VGND VGND VPB VPB
++ dstage<11>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<11>_id_delayenb1 dstage<11>_id_ts trim<24> VGND VGND VPB VPB
++ dstage<11>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<11>_id_delayint0 dstage<11>_id_d1 VGND VGND VPB VPB dstage<11>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<1>_id_delaybuf0 dstage<0>_id_out VGND VGND VPB VPB dstage<1>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<1>_id_delaybuf1 dstage<1>_id_ts VGND VGND VPB VPB dstage<1>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<1>_id_delayen0 dstage<1>_id_d2 trim<1> VGND VGND VPB VPB
++ dstage<1>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<1>_id_delayen1 dstage<1>_id_d0 trim<14> VGND VGND VPB VPB
++ dstage<1>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<1>_id_delayenb0 dstage<1>_id_ts trim<1> VGND VGND VPB VPB
++ dstage<1>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<1>_id_delayenb1 dstage<1>_id_ts trim<14> VGND VGND VPB VPB
++ dstage<1>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<1>_id_delayint0 dstage<1>_id_d1 VGND VGND VPB VPB dstage<1>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<2>_id_delaybuf0 dstage<1>_id_out VGND VGND VPB VPB dstage<2>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<2>_id_delaybuf1 dstage<2>_id_ts VGND VGND VPB VPB dstage<2>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<2>_id_delayen0 dstage<2>_id_d2 trim<2> VGND VGND VPB VPB
++ dstage<2>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<2>_id_delayen1 dstage<2>_id_d0 trim<15> VGND VGND VPB VPB
++ dstage<2>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<2>_id_delayenb0 dstage<2>_id_ts trim<2> VGND VGND VPB VPB
++ dstage<2>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<2>_id_delayenb1 dstage<2>_id_ts trim<15> VGND VGND VPB VPB
++ dstage<2>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<2>_id_delayint0 dstage<2>_id_d1 VGND VGND VPB VPB dstage<2>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<3>_id_delaybuf0 dstage<2>_id_out VGND VGND VPB VPB dstage<3>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<3>_id_delaybuf1 dstage<3>_id_ts VGND VGND VPB VPB dstage<3>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<3>_id_delayen0 dstage<3>_id_d2 trim<3> VGND VGND VPB VPB
++ dstage<3>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<3>_id_delayen1 dstage<3>_id_d0 trim<16> VGND VGND VPB VPB
++ dstage<3>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<3>_id_delayenb0 dstage<3>_id_ts trim<3> VGND VGND VPB VPB
++ dstage<3>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<3>_id_delayenb1 dstage<3>_id_ts trim<16> VGND VGND VPB VPB
++ dstage<3>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<3>_id_delayint0 dstage<3>_id_d1 VGND VGND VPB VPB dstage<3>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<4>_id_delaybuf0 dstage<3>_id_out VGND VGND VPB VPB dstage<4>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<4>_id_delaybuf1 dstage<4>_id_ts VGND VGND VPB VPB dstage<4>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<4>_id_delayen0 dstage<4>_id_d2 trim<4> VGND VGND VPB VPB
++ dstage<4>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<4>_id_delayen1 dstage<4>_id_d0 trim<17> VGND VGND VPB VPB
++ dstage<4>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<4>_id_delayenb0 dstage<4>_id_ts trim<4> VGND VGND VPB VPB
++ dstage<4>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<4>_id_delayenb1 dstage<4>_id_ts trim<17> VGND VGND VPB VPB
++ dstage<4>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<4>_id_delayint0 dstage<4>_id_d1 VGND VGND VPB VPB dstage<4>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<5>_id_delaybuf0 dstage<4>_id_out VGND VGND VPB VPB dstage<5>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<5>_id_delaybuf1 dstage<5>_id_ts VGND VGND VPB VPB dstage<5>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<5>_id_delayen0 dstage<5>_id_d2 trim<5> VGND VGND VPB VPB
++ dstage<5>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<5>_id_delayen1 dstage<5>_id_d0 trim<18> VGND VGND VPB VPB
++ dstage<5>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<5>_id_delayenb0 dstage<5>_id_ts trim<5> VGND VGND VPB VPB
++ dstage<5>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<5>_id_delayenb1 dstage<5>_id_ts trim<18> VGND VGND VPB VPB
++ dstage<5>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<5>_id_delayint0 dstage<5>_id_d1 VGND VGND VPB VPB dstage<5>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<6>_id_delaybuf0 dstage<5>_id_out VGND VGND VPB VPB dstage<6>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<6>_id_delaybuf1 dstage<6>_id_ts VGND VGND VPB VPB dstage<6>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<6>_id_delayen0 dstage<6>_id_d2 trim<6> VGND VGND VPB VPB
++ dstage<6>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<6>_id_delayen1 dstage<6>_id_d0 trim<19> VGND VGND VPB VPB
++ dstage<6>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<6>_id_delayenb0 dstage<6>_id_ts trim<6> VGND VGND VPB VPB
++ dstage<6>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<6>_id_delayenb1 dstage<6>_id_ts trim<19> VGND VGND VPB VPB
++ dstage<6>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<6>_id_delayint0 dstage<6>_id_d1 VGND VGND VPB VPB dstage<6>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<7>_id_delaybuf0 dstage<6>_id_out VGND VGND VPB VPB dstage<7>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<7>_id_delaybuf1 dstage<7>_id_ts VGND VGND VPB VPB dstage<7>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<7>_id_delayen0 dstage<7>_id_d2 trim<7> VGND VGND VPB VPB
++ dstage<7>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<7>_id_delayen1 dstage<7>_id_d0 trim<20> VGND VGND VPB VPB
++ dstage<7>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<7>_id_delayenb0 dstage<7>_id_ts trim<7> VGND VGND VPB VPB
++ dstage<7>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<7>_id_delayenb1 dstage<7>_id_ts trim<20> VGND VGND VPB VPB
++ dstage<7>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<7>_id_delayint0 dstage<7>_id_d1 VGND VGND VPB VPB dstage<7>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<8>_id_delaybuf0 dstage<7>_id_out VGND VGND VPB VPB dstage<8>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<8>_id_delaybuf1 dstage<8>_id_ts VGND VGND VPB VPB dstage<8>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<8>_id_delayen0 dstage<8>_id_d2 trim<8> VGND VGND VPB VPB
++ dstage<8>_id_out
++ sky130_fd_sc_hd__einvp_2
+Xdstage<8>_id_delayen1 dstage<8>_id_d0 trim<21> VGND VGND VPB VPB
++ dstage<8>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<8>_id_delayenb0 dstage<8>_id_ts trim<8> VGND VGND VPB VPB
++ dstage<8>_id_out
++ sky130_fd_sc_hd__einvn_8
+Xdstage<8>_id_delayenb1 dstage<8>_id_ts trim<21> VGND VGND VPB VPB
++ dstage<8>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<8>_id_delayint0 dstage<8>_id_d1 VGND VGND VPB VPB dstage<8>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xdstage<9>_id_delaybuf0 dstage<8>_id_out VGND VGND VPB VPB dstage<9>_id_ts sky130_fd_sc_hd__clkbuf_2
+Xdstage<9>_id_delaybuf1 dstage<9>_id_ts VGND VGND VPB VPB dstage<9>_id_d0 sky130_fd_sc_hd__clkbuf_1
+Xdstage<9>_id_delayen0 dstage<9>_id_d2 trim<9> VGND VGND VPB VPB
++ dstage<10>_id_in
++ sky130_fd_sc_hd__einvp_2
+Xdstage<9>_id_delayen1 dstage<9>_id_d0 trim<22> VGND VGND VPB VPB
++ dstage<9>_id_d1
++ sky130_fd_sc_hd__einvp_2
+Xdstage<9>_id_delayenb0 dstage<9>_id_ts trim<9> VGND VGND VPB VPB
++ dstage<10>_id_in
++ sky130_fd_sc_hd__einvn_8
+Xdstage<9>_id_delayenb1 dstage<9>_id_ts trim<22> VGND VGND VPB VPB
++ dstage<9>_id_d1
++ sky130_fd_sc_hd__einvn_4
+Xdstage<9>_id_delayint0 dstage<9>_id_d1 VGND VGND VPB VPB dstage<9>_id_d2 sky130_fd_sc_hd__clkinv_1
+Xibufp00 dstage<0>_id_in VGND VGND VPB VPB c<0> sky130_fd_sc_hd__clkinv_2
+Xibufp01 c<0> VGND VGND VPB VPB _0_<0> sky130_fd_sc_hd__clkinv_8
+Xibufp10 dstage<5>_id_out VGND VGND VPB VPB c<1> sky130_fd_sc_hd__clkinv_2
+Xibufp11 c<1> VGND VGND VPB VPB _0_<1> sky130_fd_sc_hd__clkinv_8
+Xiss_const1 VGND VGND VPB VPB iss_one _noconnect_1_ sky130_fd_sc_hd__conb_1
+Xiss_ctrlen0 reset trim<12> VGND VGND VPB VPB
++ iss_ctrl0
++ sky130_fd_sc_hd__or2_2
+Xiss_delaybuf0 dstage<11>_id_out VGND VGND VPB VPB iss_d0 sky130_fd_sc_hd__clkbuf_1
+Xiss_delayen0 iss_d2 trim<12> VGND VGND VPB VPB
++ dstage<0>_id_in
++ sky130_fd_sc_hd__einvp_2
+Xiss_delayen1 iss_d0 trim<25> VGND VGND VPB VPB
++ iss_d1
++ sky130_fd_sc_hd__einvp_2
+Xiss_delayenb0 dstage<11>_id_out iss_ctrl0 VGND VGND VPB VPB
++ dstage<0>_id_in
++ sky130_fd_sc_hd__einvn_8
+Xiss_delayenb1 dstage<11>_id_out trim<25> VGND VGND VPB VPB
++ iss_d1
++ sky130_fd_sc_hd__einvn_4
+Xiss_delayint0 iss_d1 VGND VGND VPB VPB iss_d2 sky130_fd_sc_hd__clkinv_1
+Xiss_reseten0 iss_one reset VGND VGND VPB VPB
++ dstage<0>_id_in
++ sky130_fd_sc_hd__einvp_1
+Xantenna_0 reset VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<25> trim<25> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<24> trim<24> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<23> trim<23> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<22> trim<22> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<21> trim<21> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<20> trim<20> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<19> trim<19> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<18> trim<18> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<17> trim<17> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<16> trim<16> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<15> trim<15> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<14> trim<14> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<13> trim<13> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<12> trim<12> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<11> trim<11> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<10> trim<10> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<9> trim<9> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<8> trim<8> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<7> trim<7> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<6> trim<6> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<5> trim<5> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<4> trim<4> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<3> trim<3> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<2> trim<2> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<1> trim<1> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1<0> trim<0> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+
+.ends
+.end
diff --git a/ngspice/digital_pll/digital_pll/ring_osc2x13.spice.bak b/ngspice/digital_pll/digital_pll/ring_osc2x13.spice.bak
new file mode 100644
index 0000000..c49b71c
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/ring_osc2x13.spice.bak
@@ -0,0 +1,264 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* SPICE netlist created from verilog structural netlist module ring_osc2x13 by vlog2Spice (qflow)
+* Warning: This file contains [] array delimiters in net names.
+* Note: Library sky130_fd_sc_hd.spice has been removed; reference library as an
+* include file from the testbench instead.
+
+.subckt ring_osc2x13 VPB VGND clockp[0] clockp[1] reset trim[0] trim[1]
++ trim[2] trim[3] trim[4] trim[5] trim[6] trim[7] trim[8] trim[9]
++ trim[10] trim[11] trim[12] trim[13] trim[14] trim[15] trim[16] trim[17]
++ trim[18] trim[19] trim[20] trim[21] trim[22] trim[23] trim[24] trim[25]
++
+
+X_1_ _0_[0] VGND VGND VPB VPB clockp[0] sky130_fd_sc_hd__buf_2
+X_2_ _0_[1] VGND VGND VPB VPB clockp[1] sky130_fd_sc_hd__buf_2
+X\dstage[0].id.delaybuf0 \dstage[0].id.in\ VGND VGND VPB VPB \dstage[0].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[0].id.delaybuf1 \dstage[0].id.ts\ VGND VGND VPB VPB \dstage[0].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[0].id.delayen0 \dstage[0].id.d2\ trim[0] VGND VGND VPB VPB
++ \dstage[0].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[0].id.delayen1 \dstage[0].id.d0\ trim[13] VGND VGND VPB VPB
++ \dstage[0].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[0].id.delayenb0 \dstage[0].id.ts\ trim[0] VGND VGND VPB VPB
++ \dstage[0].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[0].id.delayenb1 \dstage[0].id.ts\ trim[13] VGND VGND VPB VPB
++ \dstage[0].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[0].id.delayint0 \dstage[0].id.d1\ VGND VGND VPB VPB \dstage[0].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[10].id.delaybuf0 \dstage[10].id.in\ VGND VGND VPB VPB \dstage[10].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[10].id.delaybuf1 \dstage[10].id.ts\ VGND VGND VPB VPB \dstage[10].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[10].id.delayen0 \dstage[10].id.d2\ trim[10] VGND VGND VPB VPB
++ \dstage[10].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[10].id.delayen1 \dstage[10].id.d0\ trim[23] VGND VGND VPB VPB
++ \dstage[10].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[10].id.delayenb0 \dstage[10].id.ts\ trim[10] VGND VGND VPB VPB
++ \dstage[10].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[10].id.delayenb1 \dstage[10].id.ts\ trim[23] VGND VGND VPB VPB
++ \dstage[10].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[10].id.delayint0 \dstage[10].id.d1\ VGND VGND VPB VPB \dstage[10].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[11].id.delaybuf0 \dstage[10].id.out\ VGND VGND VPB VPB \dstage[11].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[11].id.delaybuf1 \dstage[11].id.ts\ VGND VGND VPB VPB \dstage[11].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[11].id.delayen0 \dstage[11].id.d2\ trim[11] VGND VGND VPB VPB
++ \dstage[11].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[11].id.delayen1 \dstage[11].id.d0\ trim[24] VGND VGND VPB VPB
++ \dstage[11].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[11].id.delayenb0 \dstage[11].id.ts\ trim[11] VGND VGND VPB VPB
++ \dstage[11].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[11].id.delayenb1 \dstage[11].id.ts\ trim[24] VGND VGND VPB VPB
++ \dstage[11].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[11].id.delayint0 \dstage[11].id.d1\ VGND VGND VPB VPB \dstage[11].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[1].id.delaybuf0 \dstage[0].id.out\ VGND VGND VPB VPB \dstage[1].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[1].id.delaybuf1 \dstage[1].id.ts\ VGND VGND VPB VPB \dstage[1].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[1].id.delayen0 \dstage[1].id.d2\ trim[1] VGND VGND VPB VPB
++ \dstage[1].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[1].id.delayen1 \dstage[1].id.d0\ trim[14] VGND VGND VPB VPB
++ \dstage[1].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[1].id.delayenb0 \dstage[1].id.ts\ trim[1] VGND VGND VPB VPB
++ \dstage[1].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[1].id.delayenb1 \dstage[1].id.ts\ trim[14] VGND VGND VPB VPB
++ \dstage[1].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[1].id.delayint0 \dstage[1].id.d1\ VGND VGND VPB VPB \dstage[1].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[2].id.delaybuf0 \dstage[1].id.out\ VGND VGND VPB VPB \dstage[2].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[2].id.delaybuf1 \dstage[2].id.ts\ VGND VGND VPB VPB \dstage[2].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[2].id.delayen0 \dstage[2].id.d2\ trim[2] VGND VGND VPB VPB
++ \dstage[2].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[2].id.delayen1 \dstage[2].id.d0\ trim[15] VGND VGND VPB VPB
++ \dstage[2].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[2].id.delayenb0 \dstage[2].id.ts\ trim[2] VGND VGND VPB VPB
++ \dstage[2].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[2].id.delayenb1 \dstage[2].id.ts\ trim[15] VGND VGND VPB VPB
++ \dstage[2].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[2].id.delayint0 \dstage[2].id.d1\ VGND VGND VPB VPB \dstage[2].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[3].id.delaybuf0 \dstage[2].id.out\ VGND VGND VPB VPB \dstage[3].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[3].id.delaybuf1 \dstage[3].id.ts\ VGND VGND VPB VPB \dstage[3].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[3].id.delayen0 \dstage[3].id.d2\ trim[3] VGND VGND VPB VPB
++ \dstage[3].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[3].id.delayen1 \dstage[3].id.d0\ trim[16] VGND VGND VPB VPB
++ \dstage[3].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[3].id.delayenb0 \dstage[3].id.ts\ trim[3] VGND VGND VPB VPB
++ \dstage[3].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[3].id.delayenb1 \dstage[3].id.ts\ trim[16] VGND VGND VPB VPB
++ \dstage[3].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[3].id.delayint0 \dstage[3].id.d1\ VGND VGND VPB VPB \dstage[3].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[4].id.delaybuf0 \dstage[3].id.out\ VGND VGND VPB VPB \dstage[4].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[4].id.delaybuf1 \dstage[4].id.ts\ VGND VGND VPB VPB \dstage[4].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[4].id.delayen0 \dstage[4].id.d2\ trim[4] VGND VGND VPB VPB
++ \dstage[4].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[4].id.delayen1 \dstage[4].id.d0\ trim[17] VGND VGND VPB VPB
++ \dstage[4].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[4].id.delayenb0 \dstage[4].id.ts\ trim[4] VGND VGND VPB VPB
++ \dstage[4].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[4].id.delayenb1 \dstage[4].id.ts\ trim[17] VGND VGND VPB VPB
++ \dstage[4].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[4].id.delayint0 \dstage[4].id.d1\ VGND VGND VPB VPB \dstage[4].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[5].id.delaybuf0 \dstage[4].id.out\ VGND VGND VPB VPB \dstage[5].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[5].id.delaybuf1 \dstage[5].id.ts\ VGND VGND VPB VPB \dstage[5].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[5].id.delayen0 \dstage[5].id.d2\ trim[5] VGND VGND VPB VPB
++ \dstage[5].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[5].id.delayen1 \dstage[5].id.d0\ trim[18] VGND VGND VPB VPB
++ \dstage[5].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[5].id.delayenb0 \dstage[5].id.ts\ trim[5] VGND VGND VPB VPB
++ \dstage[5].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[5].id.delayenb1 \dstage[5].id.ts\ trim[18] VGND VGND VPB VPB
++ \dstage[5].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[5].id.delayint0 \dstage[5].id.d1\ VGND VGND VPB VPB \dstage[5].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[6].id.delaybuf0 \dstage[5].id.out\ VGND VGND VPB VPB \dstage[6].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[6].id.delaybuf1 \dstage[6].id.ts\ VGND VGND VPB VPB \dstage[6].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[6].id.delayen0 \dstage[6].id.d2\ trim[6] VGND VGND VPB VPB
++ \dstage[6].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[6].id.delayen1 \dstage[6].id.d0\ trim[19] VGND VGND VPB VPB
++ \dstage[6].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[6].id.delayenb0 \dstage[6].id.ts\ trim[6] VGND VGND VPB VPB
++ \dstage[6].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[6].id.delayenb1 \dstage[6].id.ts\ trim[19] VGND VGND VPB VPB
++ \dstage[6].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[6].id.delayint0 \dstage[6].id.d1\ VGND VGND VPB VPB \dstage[6].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[7].id.delaybuf0 \dstage[6].id.out\ VGND VGND VPB VPB \dstage[7].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[7].id.delaybuf1 \dstage[7].id.ts\ VGND VGND VPB VPB \dstage[7].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[7].id.delayen0 \dstage[7].id.d2\ trim[7] VGND VGND VPB VPB
++ \dstage[7].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[7].id.delayen1 \dstage[7].id.d0\ trim[20] VGND VGND VPB VPB
++ \dstage[7].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[7].id.delayenb0 \dstage[7].id.ts\ trim[7] VGND VGND VPB VPB
++ \dstage[7].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[7].id.delayenb1 \dstage[7].id.ts\ trim[20] VGND VGND VPB VPB
++ \dstage[7].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[7].id.delayint0 \dstage[7].id.d1\ VGND VGND VPB VPB \dstage[7].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[8].id.delaybuf0 \dstage[7].id.out\ VGND VGND VPB VPB \dstage[8].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[8].id.delaybuf1 \dstage[8].id.ts\ VGND VGND VPB VPB \dstage[8].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[8].id.delayen0 \dstage[8].id.d2\ trim[8] VGND VGND VPB VPB
++ \dstage[8].id.out\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[8].id.delayen1 \dstage[8].id.d0\ trim[21] VGND VGND VPB VPB
++ \dstage[8].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[8].id.delayenb0 \dstage[8].id.ts\ trim[8] VGND VGND VPB VPB
++ \dstage[8].id.out\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[8].id.delayenb1 \dstage[8].id.ts\ trim[21] VGND VGND VPB VPB
++ \dstage[8].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[8].id.delayint0 \dstage[8].id.d1\ VGND VGND VPB VPB \dstage[8].id.d2\ sky130_fd_sc_hd__clkinv_1
+X\dstage[9].id.delaybuf0 \dstage[8].id.out\ VGND VGND VPB VPB \dstage[9].id.ts\ sky130_fd_sc_hd__clkbuf_2
+X\dstage[9].id.delaybuf1 \dstage[9].id.ts\ VGND VGND VPB VPB \dstage[9].id.d0\ sky130_fd_sc_hd__clkbuf_1
+X\dstage[9].id.delayen0 \dstage[9].id.d2\ trim[9] VGND VGND VPB VPB
++ \dstage[10].id.in\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[9].id.delayen1 \dstage[9].id.d0\ trim[22] VGND VGND VPB VPB
++ \dstage[9].id.d1\
++ sky130_fd_sc_hd__einvp_2
+X\dstage[9].id.delayenb0 \dstage[9].id.ts\ trim[9] VGND VGND VPB VPB
++ \dstage[10].id.in\
++ sky130_fd_sc_hd__einvn_8
+X\dstage[9].id.delayenb1 \dstage[9].id.ts\ trim[22] VGND VGND VPB VPB
++ \dstage[9].id.d1\
++ sky130_fd_sc_hd__einvn_4
+X\dstage[9].id.delayint0 \dstage[9].id.d1\ VGND VGND VPB VPB \dstage[9].id.d2\ sky130_fd_sc_hd__clkinv_1
+Xibufp00 \dstage[0].id.in\ VGND VGND VPB VPB c[0] sky130_fd_sc_hd__clkinv_2
+Xibufp01 c[0] VGND VGND VPB VPB _0_[0] sky130_fd_sc_hd__clkinv_8
+Xibufp10 \dstage[5].id.out\ VGND VGND VPB VPB c[1] sky130_fd_sc_hd__clkinv_2
+Xibufp11 c[1] VGND VGND VPB VPB _0_[1] sky130_fd_sc_hd__clkinv_8
+X\iss.const1 VGND VGND VPB VPB \iss.one\ _noconnect_1_ sky130_fd_sc_hd__conb_1
+X\iss.ctrlen0 reset trim[12] VGND VGND VPB VPB
++ \iss.ctrl0\
++ sky130_fd_sc_hd__or2_2
+X\iss.delaybuf0 \dstage[11].id.out\ VGND VGND VPB VPB \iss.d0\ sky130_fd_sc_hd__clkbuf_1
+X\iss.delayen0 \iss.d2\ trim[12] VGND VGND VPB VPB
++ \dstage[0].id.in\
++ sky130_fd_sc_hd__einvp_2
+X\iss.delayen1 \iss.d0\ trim[25] VGND VGND VPB VPB
++ \iss.d1\
++ sky130_fd_sc_hd__einvp_2
+X\iss.delayenb0 \dstage[11].id.out\ \iss.ctrl0\ VGND VGND VPB VPB
++ \dstage[0].id.in\
++ sky130_fd_sc_hd__einvn_8
+X\iss.delayenb1 \dstage[11].id.out\ trim[25] VGND VGND VPB VPB
++ \iss.d1\
++ sky130_fd_sc_hd__einvn_4
+X\iss.delayint0 \iss.d1\ VGND VGND VPB VPB \iss.d2\ sky130_fd_sc_hd__clkinv_1
+X\iss.reseten0 \iss.one\ reset VGND VGND VPB VPB
++ \dstage[0].id.in\
++ sky130_fd_sc_hd__einvp_1
+Xantenna_0 reset VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[25] trim[25] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[24] trim[24] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[23] trim[23] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[22] trim[22] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[21] trim[21] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[20] trim[20] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[19] trim[19] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[18] trim[18] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[17] trim[17] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[16] trim[16] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[15] trim[15] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[14] trim[14] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[13] trim[13] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[12] trim[12] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[11] trim[11] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[10] trim[10] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[9] trim[9] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[8] trim[8] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[7] trim[7] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[6] trim[6] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[5] trim[5] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[4] trim[4] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[3] trim[3] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[2] trim[2] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[1] trim[1] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+Xantenna_1[0] trim[0] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2
+
+.ends
+.end
diff --git a/ngspice/digital_pll/digital_pll/ring_osc2x13_tb.spice b/ngspice/digital_pll/digital_pll/ring_osc2x13_tb.spice
new file mode 100644
index 0000000..b2c3cae
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/ring_osc2x13_tb.spice
@@ -0,0 +1,58 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Ring oscillator testbench---simple check of ring oscillator
+* at several trim levels
+
+.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
+
+.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+
+.include "ring_osc2x13.spice"
+
+.option TEMP=27
+* .option RELTOL=1.0E-1
+* .option RSHUNT=1.0E20
+
+* Instantiate the ring oscillator
+* Tie trims together in four sets
+
+X0 vdd vss clockp0 clockp1 reset trim0 trim1 trim0 trim1 trim0 trim1 trim0
++ trim1 trim0 trim1 trim0 trim1 trim0 trim3 trim2 trim3 trim2 trim3 trim2
++ trim3 trim2 trim3 trim2 trim3 trim2 trim3 ring_osc2x13
+
+* Power supply (note that all logic is 1.8V here)
+
+V0 vdd vss PWL(0n 0.0 30n 1.8)
+V1 vss 0 0.0
+
+* Trim values (connect resistors to power or ground)
+* divider value = 12
+
+V2 trim0 gnd PULSE(0.0 1.8 200n 2n 2n 1u 2u)
+V3 trim1 gnd PULSE(0.0 1.8 400n 2n 2n 1u 2u)
+V4 trim2 gnd PULSE(0.0 1.8 600n 2n 2n 1u 2u)
+V5 trim3 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u)
+
+* Reset
+V6 reset gnd PWL(0n 1.8 48n 1.8 50n 0.0)
+
+* Transient analysis
+.control
+tran 100p 1u
+plot V(clockp0) V(clockp1)
+.endc
+.end
diff --git a/ngspice/digital_pll/digital_pll/ring_osc2x13_tb2.spice b/ngspice/digital_pll/digital_pll/ring_osc2x13_tb2.spice
new file mode 100644
index 0000000..93406af
--- /dev/null
+++ b/ngspice/digital_pll/digital_pll/ring_osc2x13_tb2.spice
@@ -0,0 +1,80 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Ring oscillator testbench---simple check of ring oscillator
+* at several trim levels
+
+.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
+
+.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+
+.include "ring_osc2x13.spice"
+
+.option TEMP=27
+* .option RELTOL=1.0E-1
+* .option RSHUNT=1.0E20
+
+* Instantiate the ring oscillator
+* Tie trims together in four sets
+
+X0 vdd vss clockp0 clockp1 reset trim00 trim01 trim02 trim03 trim04 trim05 trim06
++ trim07 trim08 trim09 trim10 trim11 trim12 trim13 trim14 trim15 trim16 trim17
++ trim18 trim19 trim20 trim21 trim22 trim23 trim24 trim25 ring_osc2x13
+
+* Power supply (note that all logic is 1.8V here)
+
+V00 vdd vss PWL(0n 0.0 30n 1.8)
+V01 vss 0 0.0
+
+* Trim values (connect resistors to power or ground)
+* divider value = 12
+
+V02 trim00 gnd PULSE(0.0 1.8 40n 2n 2n 1u 2u)
+V03 trim01 gnd PULSE(0.0 1.8 80n 2n 2n 1u 2u)
+V04 trim02 gnd PULSE(0.0 1.8 120n 2n 2n 1u 2u)
+V05 trim03 gnd PULSE(0.0 1.8 160n 2n 2n 1u 2u)
+V06 trim04 gnd PULSE(0.0 1.8 200n 2n 2n 1u 2u)
+V07 trim05 gnd PULSE(0.0 1.8 240n 2n 2n 1u 2u)
+V08 trim06 gnd PULSE(0.0 1.8 280n 2n 2n 1u 2u)
+V09 trim07 gnd PULSE(0.0 1.8 320n 2n 2n 1u 2u)
+V10 trim08 gnd PULSE(0.0 1.8 360n 2n 2n 1u 2u)
+V11 trim09 gnd PULSE(0.0 1.8 400n 2n 2n 1u 2u)
+V12 trim10 gnd PULSE(0.0 1.8 440n 2n 2n 1u 2u)
+V13 trim11 gnd PULSE(0.0 1.8 480n 2n 2n 1u 2u)
+V14 trim12 gnd PULSE(0.0 1.8 520n 2n 2n 1u 2u)
+V15 trim13 gnd PULSE(0.0 1.8 560n 2n 2n 1u 2u)
+V16 trim14 gnd PULSE(0.0 1.8 600n 2n 2n 1u 2u)
+V17 trim15 gnd PULSE(0.0 1.8 640n 2n 2n 1u 2u)
+V18 trim16 gnd PULSE(0.0 1.8 680n 2n 2n 1u 2u)
+V19 trim17 gnd PULSE(0.0 1.8 720n 2n 2n 1u 2u)
+V20 trim18 gnd PULSE(0.0 1.8 760n 2n 2n 1u 2u)
+V21 trim19 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u)
+V22 trim20 gnd PULSE(0.0 1.8 840n 2n 2n 1u 2u)
+V23 trim21 gnd PULSE(0.0 1.8 880n 2n 2n 1u 2u)
+V24 trim22 gnd PULSE(0.0 1.8 920n 2n 2n 1u 2u)
+V25 trim23 gnd PULSE(0.0 1.8 960n 2n 2n 1u 2u)
+V26 trim24 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u)
+V27 trim25 gnd PULSE(0.0 1.8 840n 2n 2n 1u 2u)
+
+* Reset
+V6 reset gnd PWL(0n 1.8 8n 1.8 10n 0.0)
+
+* Transient analysis
+.control
+tran 100p 1u
+plot V(clockp0) V(clockp1)
+.endc
+.end
diff --git a/ngspice/simple_por/simple_por/current_test.spice b/ngspice/simple_por/simple_por/current_test.spice
new file mode 100644
index 0000000..da74e24
--- /dev/null
+++ b/ngspice/simple_por/simple_por/current_test.spice
@@ -0,0 +1,85 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Simple POR circuit for Caravel current mirror test
+*-------------------------------------------------------------------
+
+.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+* Note: 20 resistors of length 25um connected in series
+Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
+Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149
+
+* voltage sources at 0V for measuring current in each branch
+
+Vm1 vssm1 vss DC=0
+Vm2 vdda vddm2 DC=0
+Vm3 vdda vddm3 DC=0
+Vm4 vssm4 vss DC=0
+Vm5 vssm5 vss DC=0
+Vm6 vdda vddm6 DC=0
+Vm7 vdda vddm7 DC=0
+
+* D G S B
+Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
+Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+
+* Check branch currents in each mirror branch.
+* 1st branch should be 240nA
+* 2nd branch should be 30nA
+* 3rd branch should be 4.3nA
+* 4th branch should be 612pA
+*
+* Result: vin sits at 0.7590 (close to 0.7575 target)
+* I(Vm1/2) = 202.80 nA
+* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77
+* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70
+* I(Vm7) = 0.67 pA (should be /7) actually /6.80
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.01
+Rload vcap vss 1MEG
+*----------------------------
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+op
+print V(vin)
+print I(Vm1)
+print I(Vm2)
+print I(Vm3)
+print I(Vm4)
+print I(Vm5)
+print I(Vm6)
+print I(Vm7)
+.endc
+
+.end
+
diff --git a/ngspice/simple_por/simple_por/simple_por.spice b/ngspice/simple_por/simple_por/simple_por.spice
new file mode 100644
index 0000000..2aa5265
--- /dev/null
+++ b/ngspice/simple_por/simple_por/simple_por.spice
@@ -0,0 +1,229 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* NGSPICE file created from simple_por.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW VSUBS m4_n3179_n3100# c2_n3079_n3000#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X
+X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200#
++ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200#
++ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297#
++ a_n683_n200#
+X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS VSUBS a_n80_n288# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288#
++ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200#
+X0 a_516_n200# a_356_n288# a_298_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X2 a_298_n200# a_138_n288# a_80_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X3 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X4 a_734_n200# a_574_n288# a_516_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+X6 a_n138_n200# a_n298_n288# a_n356_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 VSUBS a_n2578_n2932# a_5142_2500# a_n1034_n2932#
++ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500#
++ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932#
++ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500#
++ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500#
++ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500#
++ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932#
++ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500#
+X0 a_n3350_n2932# a_n3350_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n4508_n2932# a_n4508_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n2578_n2932# a_n2578_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_n1420_n2932# a_n1420_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_n4894_n2932# a_n4894_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n3736_n2932# a_n3736_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_3598_n2932# a_3598_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_124_n2932# a_124_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_4756_n2932# a_4756_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n2964_n2932# a_n2964_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_1668_n2932# a_1668_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n1806_n2932# a_n1806_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n648_n2932# a_n648_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_3984_n2932# a_3984_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_2826_n2932# a_2826_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_510_n2932# a_510_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_n4122_n2932# a_n4122_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_n2192_n2932# a_n2192_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_5142_n2932# a_5142_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_n1034_n2932# a_n1034_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_2054_n2932# a_2054_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_4370_n2932# a_4370_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_3212_n2932# a_3212_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_1282_n2932# a_1282_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n262_n2932# a_n262_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_n5280_n2932# a_n5280_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_2440_n2932# a_2440_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_896_n2932# a_896_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X
+X0 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X1 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u
+X2 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u
+X3 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u
+X4 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u
+X5 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X6 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X7 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X8 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u
+X9 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM VSUBS a_n80_n288# a_n138_n200# a_80_n200#
++ w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC VSUBS a_n80_n288# a_n138_n200# a_80_n200#
++ w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW VSUBS m3_n3136_n3100# c1_n3036_n3000#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297#
++ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200#
+X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u
+X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u
+.ends
+
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW
+Xsky130_fd_sc_hvl__buf_8_1 out vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_502_7653# vdd3v3 vdd3v3 vdd3v3
++ m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653#
++ m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 vss m1_721_6815# vss m1_721_6815# vss m1_721_6815#
++ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
++ vss m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 vss li_2935_165# vss li_4479_165# li_4866_5813#
++ li_7182_5813# li_5251_165# li_1778_5813# li_9111_165# li_3322_5813# li_9498_5813#
++ li_7567_165# li_7954_5813# li_9883_165# li_8726_5813# li_7182_5813# li_619_165#
++ li_5638_5813# li_1006_5813# li_2163_165# li_5638_5813# li_619_165# li_6795_165#
++ li_5251_165# li_3707_165# li_9498_5813# li_2163_165# li_4479_165# li_4866_5813#
++ vss li_4094_5813# li_2550_5813# li_2550_5813# li_4094_5813# li_8339_165# li_2935_165#
++ li_7954_5813# li_9883_165# vss li_6410_5813# li_8339_165# vss li_1778_5813# li_1006_5813#
++ vss li_6410_5813# li_6023_165# li_6795_165# li_3707_165# vdd3v3 li_1391_165# li_9111_165#
++ li_8726_5813# li_7567_165# li_6023_165# vss li_1391_165# li_3322_5813# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_2993_7658# vdd3v3 m1_721_6815# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3
++ vdd3v3 out sky130_fd_sc_hvl__schmittbuf_1
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_2756_6573# vdd3v3 m1_4283_8081# m1_2756_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_6249_7690# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A
++ m1_2756_6573# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_185_6573# vdd3v3 m1_502_7653# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_6249_7690# m1_4283_8081#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_721_6815# vss m1_2756_6573# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss li_2550_5813# vss m1_185_6573# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_WRT4AW
+Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081#
++ vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081#
++ m1_4283_8081# m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_2993_7658# m1_502_7653#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+Xsky130_fd_sc_hvl__inv_8_0 out vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+Xsky130_fd_sc_hvl__fill_4_0 vss vss vdd3v3 vdd3v3 sky130_fd_sc_hvl__fill_4
+Xsky130_fd_sc_hvl__buf_8_0 out vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+.ends
+
diff --git a/ngspice/simple_por/simple_por/simple_por_tb.spice b/ngspice/simple_por/simple_por/simple_por_tb.spice
new file mode 100644
index 0000000..18fc1dc
--- /dev/null
+++ b/ngspice/simple_por/simple_por/simple_por_tb.spice
@@ -0,0 +1,51 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Simple POR circuit for Caravel
+*-------------------------------------------------------------------
+*
+* Architecture: see simple_por.spice
+* Response of this circuit by ngspice simulation is a ~15ms delay.
+*-------------------------------------------------------------------
+
+.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+.include simple_por.spice
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Vpwr vdda vss DC=0 PWL(0.0 0 100u 0 5m 3.3)
+Vdig vccd vss DC=0 PWL(0.0 0 300u 0 5.3m 1.8)
+Rgnd vss 0 0.01
+Cload1 porb_h vss 1E-12
+Cload2 por_l vss 1E-12
+Cload3 porb_l vss 1E-12
+Xpor vdda vccd vss porb_h por_l porb_l simple_por
+*----------------------------
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+tran 10u 20m
+plot porb_h
+plot por_l
+plot porb_l
+.endc
+
+.end
+
diff --git a/ngspice/simple_por/simple_por/threshold_test_tb.spice b/ngspice/simple_por/simple_por/threshold_test_tb.spice
new file mode 100644
index 0000000..4d064d0
--- /dev/null
+++ b/ngspice/simple_por/simple_por/threshold_test_tb.spice
@@ -0,0 +1,47 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Threshold test for POR circuit
+* Determine gate voltage at which the HV NFET draws 240nA nominal
+*
+* Result: 0.7575V
+*-------------------------------------------------------------------
+
+.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Rtest vdda mir1 1MEG
+Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8
+
+Vgate vin vss DC=0
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.1
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+* DC sweep from 0.7 to 0.8V
+dc Vgate 0.7 0.8 0.001
+wrdata test.data Vpwr#branch vin
+
+.endc
+
+.end
+
diff --git a/scripts/check_density.py b/scripts/check_density.py
new file mode 100755
index 0000000..25f44ba
--- /dev/null
+++ b/scripts/check_density.py
@@ -0,0 +1,616 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# check_density.py ---
+#
+# Run density checks on the final (filled) GDS.
+#
+
+import sys
+import os
+import re
+import select
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("check_density.py [<path_to_project>] [-keep]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the check script.")
+ return 0
+
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to check_density.py.")
+ usage()
+ sys.exit(0)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ # Check for valid user path
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ if user_id_value:
+ project = 'caravel'
+ project_with_id = 'caravel_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ with open(magpath + '/check_density.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('crashbackups stop', file=ofile)
+ print('drc off', file=ofile)
+ print('snap internal', file=ofile)
+
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started reading GDS: $starttime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Read final project from .gds
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/' + project_with_id + '.gds', file=ofile)
+ print('', file=ofile)
+
+ print('set midtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Starting density checks: $midtime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Get step box dimensions (700um for size and 70um for FOM step)
+ # Use 350um for stepping on other layers.
+ print('box values 0 0 0 0', file=ofile)
+ # print('box size 700um 700um', file=ofile)
+ # print('set stepbox [box values]', file=ofile)
+ # print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ # print('set stepheight [lindex $stepbox 3]', file=ofile)
+
+ print('box size 70um 70um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepsizex [lindex $stepbox 2]', file=ofile)
+ print('set stepsizey [lindex $stepbox 3]', file=ofile)
+
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+
+ # Modify the box to be inside the seal ring area (shrink 5um)
+ print('box grow c -5um', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepsizex))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepsizey))}]', file=ofile)
+ print('box size $stepsizex $stepsizey', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ print('puts stdout "XTILES: $xtiles"', file=ofile)
+ print('puts stdout "YTILES: $ytiles"', file=ofile)
+ print('', file=ofile)
+
+ # Need to know what fraction of a full tile is the last row and column
+ print('set xfrac [expr {($xtiles * $stepsizex - $fullwidth + 0.0) / $stepsizex}]', file=ofile)
+ print('set yfrac [expr {($ytiles * $stepsizey - $fullheight + 0.0) / $stepsizey}]', file=ofile)
+ print('puts stdout "XFRAC: $xfrac"', file=ofile)
+ print('puts stdout "YFRAC: $yfrac"', file=ofile)
+
+ print('cif ostyle density', file=ofile)
+
+ # Process density at steps. For efficiency, this is done in 70x70 um
+ # areas, dumped to a file, and then aggregated into the 700x700 areas.
+
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepsizex]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepsizey]', file=ofile)
+ print(' set xhi [expr $xlo + $stepsizex]', file=ofile)
+ print(' set yhi [expr $ylo + $stepsizey]', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+
+ # Flatten this area
+ print(' flatten -dobbox -nolabels tile', file=ofile)
+ print(' load tile', file=ofile)
+ print(' select top cell', file=ofile)
+
+ # Run density check for each layer
+ print(' puts stdout "Density results for tile x=$x y=$y"', file=ofile)
+
+ print(' set fdens [cif list cover fom_all]', file=ofile)
+ print(' set pdens [cif list cover poly_all]', file=ofile)
+ print(' set ldens [cif list cover li_all]', file=ofile)
+ print(' set m1dens [cif list cover m1_all]', file=ofile)
+ print(' set m2dens [cif list cover m2_all]', file=ofile)
+ print(' set m3dens [cif list cover m3_all]', file=ofile)
+ print(' set m4dens [cif list cover m4_all]', file=ofile)
+ print(' set m5dens [cif list cover m5_all]', file=ofile)
+ print(' puts stdout "FOM: $fdens"', file=ofile)
+ print(' puts stdout "POLY: $pdens"', file=ofile)
+ print(' puts stdout "LI1: $ldens"', file=ofile)
+ print(' puts stdout "MET1: $m1dens"', file=ofile)
+ print(' puts stdout "MET2: $m2dens"', file=ofile)
+ print(' puts stdout "MET3: $m3dens"', file=ofile)
+ print(' puts stdout "MET4: $m4dens"', file=ofile)
+ print(' puts stdout "MET5: $m5dens"', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+
+ print(' load ' + project_with_id, file=ofile)
+ print(' cellname delete tile', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('', file=ofile)
+
+
+ myenv = os.environ.copy()
+ # Real views are necessary for the DRC checks
+ myenv['MAGTYPE'] = 'mag'
+
+ print('Running density checks on file ' + project_with_id + '.gds', flush=True)
+
+ mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/check_density.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+
+ # Use signal to poll the process and generate any output as it arrives
+
+ dlines = []
+
+ while mproc:
+ status = mproc.poll()
+ if status != None:
+ try:
+ output = mproc.communicate(timeout=1)
+ except ValueError:
+ print('Magic forced stop, status ' + str(status))
+ sys.exit(1)
+ else:
+ outlines = output[0]
+ errlines = output[1]
+ for line in outlines.splitlines():
+ dlines.append(line)
+ print(line)
+ for line in errlines.splitlines():
+ print(line)
+ print('Magic exited with status ' + str(status))
+ if int(status) != 0:
+ sys.exit(int(status))
+ else:
+ break
+ else:
+ n = 0
+ while True:
+ n += 1
+ if n > 100:
+ n = 0
+ status = mproc.poll()
+ if status != None:
+ break
+ sresult = select.select([mproc.stdout, mproc.stderr], [], [], 0.5)[0]
+ if mproc.stdout in sresult:
+ outstring = mproc.stdout.readline().strip()
+ dlines.append(outstring)
+ print(outstring)
+ elif mproc.stderr in sresult:
+ outstring = mproc.stderr.readline().strip()
+ print(outstring)
+ else:
+ break
+
+ fomfill = []
+ polyfill = []
+ lifill = []
+ met1fill = []
+ met2fill = []
+ met3fill = []
+ met4fill = []
+ met5fill = []
+ xtiles = 0
+ ytiles = 0
+ xfrac = 0.0
+ yfrac = 0.0
+
+ for line in dlines:
+ dpair = line.split(':')
+ if len(dpair) == 2:
+ layer = dpair[0]
+ try:
+ density = float(dpair[1].strip())
+ except:
+ continue
+ if layer == 'FOM':
+ fomfill.append(density)
+ elif layer == 'POLY':
+ polyfill.append(density)
+ elif layer == 'LI1':
+ lifill.append(density)
+ elif layer == 'MET1':
+ met1fill.append(density)
+ elif layer == 'MET2':
+ met2fill.append(density)
+ elif layer == 'MET3':
+ met3fill.append(density)
+ elif layer == 'MET4':
+ met4fill.append(density)
+ elif layer == 'MET5':
+ met5fill.append(density)
+ elif layer == 'XTILES':
+ xtiles = int(dpair[1].strip())
+ elif layer == 'YTILES':
+ ytiles = int(dpair[1].strip())
+ elif layer == 'XFRAC':
+ xfrac = float(dpair[1].strip())
+ elif layer == 'YFRAC':
+ yfrac = float(dpair[1].strip())
+
+ if ytiles == 0 or xtiles == 0:
+ print('Failed to read XTILES or YTILES from output.')
+ sys.exit(1)
+
+ total_tiles = (ytiles - 9) * (xtiles - 9)
+
+ print('')
+ print('Density results (total tiles = ' + str(total_tiles) + '):')
+
+ # For FOM, step at 70um intervals (same as 70um check area)
+ fomstep = 1
+
+ # For poly, step only at 700um intervals (10 * 70um check area)
+ polystep = 10
+
+ # For all metals, step only at 350um intervals (5 * 70um check area)
+ metalstep = 5
+
+ # Full areas are 10 x 10 tiles = 100. But the right and top sides are
+ # not full tiles, so the full area must be prorated.
+
+ sideadjust = 90.0 + (10.0 * xfrac)
+ topadjust = 90.0 + (10.0 * yfrac)
+ corneradjust = 81.0 + (9.0 * xfrac) + (9.0 * yfrac) + (xfrac * yfrac)
+
+ print('')
+ print('FOM Density:')
+ for y in range(0, ytiles - 9, fomstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, fomstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ fomaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ fomaccum += sum(fomfill[base : base + 10])
+
+ fomaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ print('')
+ print('POLY Density:')
+ for y in range(0, ytiles - 9, polystep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, polystep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ polyaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ polyaccum += sum(polyfill[base : base + 10])
+
+ polyaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(polyaccum))
+
+ print('')
+ print('LI Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ liaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ liaccum += sum(lifill[base : base + 10])
+
+ liaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ print('')
+ print('MET1 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met1accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met1accum += sum(met1fill[base : base + 10])
+
+ met1accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ print('')
+ print('MET2 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met2accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met2accum += sum(met2fill[base : base + 10])
+
+ met2accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ print('')
+ print('MET3 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met3accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met3accum += sum(met3fill[base : base + 10])
+
+ met3accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ print('')
+ print('MET4 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met4accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met4accum += sum(met4fill[base : base + 10])
+
+ met4accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ print('')
+ print('MET5 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met5accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met5accum += sum(met5fill[base : base + 10])
+
+ met5accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ print('')
+ print('Whole-chip density results:')
+
+ atotal = ((xtiles - 1.0) * (ytiles - 1.0)) + ((ytiles - 1.0) * xfrac) + ((xtiles - 1.0) * yfrac) + (xfrac * yfrac)
+
+ fomaccum = sum(fomfill) / atotal
+ print('')
+ print('FOM Density: ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ polyaccum = sum(polyfill) / atotal
+ print('')
+ print('POLY Density: ' + str(polyaccum))
+
+ liaccum = sum(lifill) / atotal
+ print('')
+ print('LI Density: ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ met1accum = sum(met1fill) / atotal
+ print('')
+ print('MET1 Density: ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ met2accum = sum(met2fill) / atotal
+ print('')
+ print('MET2 Density: ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ met3accum = sum(met3fill) / atotal
+ print('')
+ print('MET3 Density: ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ met4accum = sum(met4fill) / atotal
+ print('')
+ print('MET4 Density: ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ met5accum = sum(met5fill) / atotal
+ print('')
+ print('MET5 Density: ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ if not keepmode:
+ if os.path.isfile(magpath + '/check_density.tcl'):
+ os.remove(magpath + '/check_density.tcl')
+
+ print('')
+ print('Done!')
+ sys.exit(0)
diff --git a/scripts/count_lvs.py b/scripts/count_lvs.py
new file mode 100644
index 0000000..21b7771
--- /dev/null
+++ b/scripts/count_lvs.py
@@ -0,0 +1,132 @@
+#!/usr/bin/python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+#---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+#---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+#---------------------------------------------------------
+
+import os
+import re
+import sys
+import json
+import argparse
+
+def count_LVS_failures(filename):
+ with open(filename, 'r') as cfile:
+ lvsdata = json.load(cfile)
+
+ # Count errors in the JSON file
+ failures = 0
+ devfail = 0
+ netfail = 0
+ pinfail = 0
+ propfail = 0
+ netdiff = 0
+ devdiff = 0
+ ncells = len(lvsdata)
+ for c in range(0, ncells):
+ cellrec = lvsdata[c]
+
+ if c == ncells - 1:
+ topcell = True
+ else:
+ topcell = False
+
+ # Most errors must only be counted for the top cell, because individual
+ # failing cells are flattened and the matching attempted again on the
+ # flattened netlist.
+
+ if topcell:
+ if 'devices' in cellrec:
+ devices = cellrec['devices']
+ devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+ devpair = list(devlist[p:p + 2] for p in range(0, len(devlist), 2))
+ for dev in devpair:
+ c1dev = dev[0]
+ c2dev = dev[1]
+ diffdevs = abs(c1dev[1] - c2dev[1])
+ failures += diffdevs
+ devdiff += diffdevs
+
+ if 'nets' in cellrec:
+ nets = cellrec['nets']
+ diffnets = abs(nets[0] - nets[1])
+ failures += diffnets
+ netdiff += diffnets
+
+ if 'badnets' in cellrec:
+ badnets = cellrec['badnets']
+ failures += len(badnets)
+ netfail += len(badnets)
+
+ if 'badelements' in cellrec:
+ badelements = cellrec['badelements']
+ failures += len(badelements)
+ devfail += len(badelements)
+
+ if 'pins' in cellrec:
+ pins = cellrec['pins']
+ pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+ pinpair = list(pinlist[p:p + 2] for p in range(0, len(pinlist), 2))
+ for pin in pinpair:
+ # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+ # and ignore case when comparing pins.
+ pin0 = re.sub('!$', '', pin[0].lower())
+ pin1 = re.sub('!$', '', pin[1].lower())
+ if pin0 != pin1:
+ failures += 1
+ pinfail += 1
+
+ # Property errors must be counted for every cell
+ if 'properties' in cellrec:
+ properties = cellrec['properties']
+ failures += len(properties)
+ propfail += len(properties)
+
+ return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+if __name__ == '__main__':
+
+ parser = argparse.ArgumentParser(description='Parses netgen lvs')
+ parser.add_argument('--file', '-f', required=True)
+ args = parser.parse_args()
+ failures = count_LVS_failures(args.file)
+ total = failures[0]
+ if total > 0:
+ failed = True
+ print('LVS reports:')
+ print(' net count difference = ' + str(failures[5]))
+ print(' device count difference = ' + str(failures[6]))
+ print(' unmatched nets = ' + str(failures[1]))
+ print(' unmatched devices = ' + str(failures[2]))
+ print(' unmatched pins = ' + str(failures[3]))
+ print(' property failures = ' + str(failures[4]))
+ else:
+ print('LVS reports no net, device, pin, or property mismatches.')
+
+ print('')
+ print('Total errors = ' + str(total))
+
diff --git a/scripts/create-caravel-diagram.py b/scripts/create-caravel-diagram.py
new file mode 100644
index 0000000..18af64d
--- /dev/null
+++ b/scripts/create-caravel-diagram.py
@@ -0,0 +1,112 @@
+import sys
+import os
+import subprocess
+from pathlib import Path
+import argparse
+from tempfile import mkstemp
+import re
+
+
+def remove_inouts(jsonpath, replacewith='input'):
+ """Replaces inouts with either input or output statements.
+
+ Netlistsvg does not parse inout ports as for now, so they need to be
+ replaced with either input or output to produce a diagram.
+
+ Parameters
+ ----------
+ jsonpath : str
+ Path to JSON file to fix
+ replacewith : str
+ The string to replace 'inout', can be 'input' or 'output'
+ """
+ assert replacewith in ['input', 'output']
+ with open(jsonpath, 'r') as withinouts:
+ lines = withinouts.readlines()
+ with open(jsonpath, 'w') as withoutinouts:
+ for line in lines:
+ withoutinouts.write(re.sub('inout', replacewith, line))
+
+
+def main(argv):
+ parser = argparse.ArgumentParser(argv[0])
+ parser.add_argument(
+ 'verilog_rtl_dir',
+ help="Path to the project's verilog/rtl directory",
+ type=Path)
+ parser.add_argument(
+ 'output',
+ help="Path to the output SVG file",
+ type=Path)
+ parser.add_argument(
+ '--num-iopads',
+ help='Number of iopads to render',
+ type=int,
+ default=38)
+ parser.add_argument(
+ '--yosys-executable',
+ help='Path to yosys executable',
+ type=Path,
+ default='yosys')
+ parser.add_argument(
+ '--netlistsvg-executable',
+ help='Path to netlistsvg executable',
+ type=Path,
+ default='netlistsvg')
+ parser.add_argument(
+ '--inouts-as',
+ help='To what kind of IO should inout ports be replaced',
+ choices=['input', 'output'],
+ default='input'
+ )
+
+ args = parser.parse_args(argv[1:])
+
+ fd, jsonpath = mkstemp(suffix='-yosys.json')
+ os.close(fd)
+
+ yosyscommand = [
+ f'{str(args.yosys_executable)}',
+ '-p',
+ 'read_verilog pads.v defines.v; ' +
+ 'read_verilog -lib -overwrite *.v; ' +
+ f'verilog_defines -DMPRJ_IO_PADS={args.num_iopads}; ' +
+ 'read_verilog -overwrite caravel.v; ' +
+ 'hierarchy -top caravel; ' +
+ 'proc; ' +
+ 'opt; ' +
+ f'write_json {jsonpath}; '
+ ]
+
+ result = subprocess.run(
+ yosyscommand,
+ cwd=args.verilog_rtl_dir,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+
+ exitcode = 0
+ if result.returncode != 0:
+ print(f'Failed to run: {" ".join(yosyscommand)}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+ else:
+ # TODO once netlistsvg supports inout ports, this should be removed
+ remove_inouts(jsonpath, args.inouts_as)
+ command = f'{args.netlistsvg_executable} {jsonpath} -o {args.output}'
+ result = subprocess.run(
+ command.split(),
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+ if result.returncode != 0:
+ print(f'Failed to run: {command}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+
+ os.unlink(jsonpath)
+ sys.exit(exitcode)
+
+
+if __name__ == '__main__':
+ sys.exit(main(sys.argv))
diff --git a/scripts/generate_fill_orig.py b/scripts/generate_fill_orig.py
new file mode 100755
index 0000000..3a43a8c
--- /dev/null
+++ b/scripts/generate_fill_orig.py
@@ -0,0 +1,268 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# generate_fill_orig.py ---
+#
+# Run the fill generation on a layout top level.
+# This is the older version that does not have a "-dist" option for
+# distributed (multiprocessing) operation.
+#
+
+import sys
+import os
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("generate_fill_orig.py [<path_to_project>] [-keep] [-test]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ print(" If '-test' is specified, then create but do not run the generation script.")
+ return 0
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+ testmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to generate_fill_orig.py.")
+ usage()
+ sys.exit(1)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ project = 'caravel'
+ if user_id_value:
+ project_with_id = project + '_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+ if '-test' in optionlist:
+ testmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ if not os.path.isfile(rcfile):
+ rcfile = None
+
+ topdir = user_project_path
+ gdsdir = topdir + '/gds'
+ hasgdsdir = True if os.path.isdir(gdsdir) else False
+
+ with open(magpath + '/generate_fill.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box size 700um 700um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ print('set stepheight [lindex $stepbox 3]', file=ofile)
+ print('', file=ofile)
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started: $starttime"', file=ofile)
+ print('', file=ofile)
+ # Read the user project from GDS, as there is not necessarily a magic database file
+ # to go along with this.
+ # print('gds read ../gds/user_project_wrapper', file=ofile)
+ # Now read the full caravel project
+ # print('load ' + project + ' -dereference', file=ofile)
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/caravel', file=ofile)
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepwidth))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepheight))}]', file=ofile)
+ print('box size $stepwidth $stepheight', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ # Break layout into tiles and process each separately
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' if {$xhi > $fullwidth} {set xhi $fullwidth}', file=ofile)
+ print(' if {$yhi > $fullheight} {set yhi $fullheight}', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ # The flattened area must be larger than the fill tile by >1.5um
+ print(' box grow c 1.6um', file=ofile)
+
+ # Flatten into a cell with a new name
+ print(' puts stdout "Flattening layout of tile x=$x y=$y. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' flatten -dobox -nolabels ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ # Remove any GDS_FILE reference (there should not be any?)
+ print(' property GDS_FILE ""', file=ofile)
+ # Set boundary using comment layer, to the size of the step box
+ # This corresponds to the "topbox" rule in the wafflefill(tiled) style
+ print(' select top cell', file=ofile)
+ print(' erase comment', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' puts stdout "Writing GDS. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' gds write ' + project_with_id + '_fill_pattern_${x}_$y.gds', file=ofile)
+
+ # Reload project top
+ print(' load ' + project, file=ofile)
+
+ # Remove last generated cell to save memory
+ print(' cellname delete ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now create simple "fake" views of all the tiles.
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y -quiet', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' property FIXED_BBOX "$xlo $ylo $xhi $yhi"', file=ofile)
+ print(' property GDS_FILE ' + project_with_id + '_fill_pattern_${x}_${y}.gds', file=ofile)
+ print(' property GDS_START 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now tile everything back together
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' box values 0 0 0 0', file=ofile)
+ print(' getcell ' + project_with_id + '_fill_pattern_${x}_$y child 0 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # And write final GDS
+ print('puts stdout "Writing final GDS"', file=ofile)
+
+ print('cif *hier write disable', file=ofile)
+ print('cif *array write disable', file=ofile)
+ if hasgdsdir:
+ print('gds write ../gds/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ else:
+ print('gds write ' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ if not testmode:
+ # Diagnostic
+ # print('This script will generate file ' + project_with_id + '_fill_pattern.gds')
+ print('This script will generate files ' + project_with_id + '_fill_pattern_x_y.gds')
+ print('Now generating fill patterns. This may take. . . quite. . . a while.', flush=True)
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ # Remove fill generation script
+ os.remove(magpath + '/generate_fill.tcl')
+ # Remove all individual fill tiles, leaving only the composite GDS.
+ filelist = os.listdir(magpath)
+ for file in filelist:
+ if os.path.splitext(magpath + '/' + file)[1] == '.gds':
+ if file.startswith(project + '_fill_pattern_'):
+ os.remove(magpath + '/' + file)
+
+ print('Done!')
+ exit(0)
diff --git a/scripts/make_bump_bonds.tcl b/scripts/make_bump_bonds.tcl
new file mode 100644
index 0000000..4ce3aa9
--- /dev/null
+++ b/scripts/make_bump_bonds.tcl
@@ -0,0 +1,688 @@
+#----------------------------------------------------------------------
+# Assumes running magic -T micross using the micross technology file
+# from the open_pdks installation of sky130A
+#----------------------------------------------------------------------
+# bump bond pitch is 500um. Bump diameter is set by the technology
+
+namespace path {::tcl::mathop ::tcl::mathfunc}
+
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+source $PDKPATH/libs.tech/magic/current/bump_bond_generator/bump_bond.tcl
+
+# Caravel dimensions, in microns
+set chipwidth 3588
+set chipheight 5188
+
+set halfwidth [/ $chipwidth 2]
+set halfheight [/ $chipheight 2]
+
+set columns 6
+set rows 10
+
+set bump_pitch 500
+
+set llx [- $halfwidth [* [- [/ $columns 2] 0.5] $bump_pitch]]
+set lly [- $halfheight [* [- [/ $rows 2] 0.5] $bump_pitch]]
+
+# Create a new cell
+load caravel_bump_bond -quiet
+
+# Build the bump cells
+make_bump_bond 0
+make_bump_bond 45
+
+# View the whole chip during generation. This is not strictly
+# necessary, but looks nice!
+snap internal
+box values 0 0 ${chipwidth}um ${chipheight}um
+paint glass
+view
+erase glass
+box values 0 0 0 0
+grid 250um 250um 45um 95um
+
+# Starting from the bottom left-hand corner and scanning across and up,
+# these are the orientations of the bump bond pad tapers:
+set tapers {}
+lappend tapers 180 225 270 270 270 270
+lappend tapers 180 135 225 270 0 0
+lappend tapers 180 135 135 270 315 0
+lappend tapers 180 135 135 315 315 0
+lappend tapers 135 135 0 180 315 0
+lappend tapers 180 135 0 180 315 0
+lappend tapers 180 135 180 315 315 0
+lappend tapers 180 180 135 45 315 0
+lappend tapers 135 135 135 45 45 45
+lappend tapers 90 90 90 90 45 90
+
+box values 0 0 0 0
+set t 0
+for {set y 0} {$y < $rows} {incr y} {
+ for {set x 0} {$x < $columns} {incr x} {
+ set xpos [+ $llx [* $x $bump_pitch]]
+ set ypos [+ $lly [* $y $bump_pitch]]
+ draw_bump_bond $xpos $ypos [lindex $tapers $t]
+ incr t
+ }
+}
+
+# The pad at E6 has wires exiting two sides, so put another pad down
+# at the other orientation.
+set y 4
+set x 4
+set xpos [+ $llx [* $x $bump_pitch]]
+set ypos [+ $lly [* $y $bump_pitch]]
+draw_bump_bond $xpos $ypos 180
+
+select top cell
+expand
+
+# These are the pad Y positions on the left side from bottom to top
+
+set leftpads {}
+lappend leftpads 377.5 588.5 950.5 1166.5 1382.5 1598.5 1814.5
+lappend leftpads 2030.5 2241.5 2452.5 2668.5 2884.5 3100.5
+lappend leftpads 3316.5 3532.5 3748.5 3964.5 4175.5 4386.5 4597.5 4813.5
+
+# These are the pad X positions on the top side from left to right
+
+set toppads {}
+lappend toppads 423.5 680.5 937.5 1194.5 1452.5 1704.5 1961.5 2406.5
+lappend toppads 2663.5 2915.5 3172.5
+
+# These are the pad Y positions on the right side from bottom to top
+
+set rightpads {}
+lappend rightpads 537.5 763.5 988.5 1214.5 1439.5 1664.5 1890.5
+lappend rightpads 2115.5 2336.5 2556.5 2776.5 3002.5 3227.5 3453.5
+lappend rightpads 3678.5 3903.5 4129.5 4349.5 4575.5 4795.5
+
+# These are the pad X positions on the bottom side from left to right
+
+set bottompads {}
+lappend bottompads 431.5 700.5 969.5 1243.5 1512.5 1786.5 2060.5
+lappend bottompads 2334.5 2608.5 2882.5 3151.5
+
+set leftpadx 64.6
+set rightpadx 3523.78
+set bottompady 64.6
+set toppady 5123.78
+
+set xpos $leftpadx
+for {set y 0} {$y < [llength $leftpads]} {incr y} {
+ set ypos [lindex $leftpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $toppady
+for {set x 0} {$x < [llength $toppads]} {incr x} {
+ set xpos [lindex $toppads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+set xpos $rightpadx
+for {set y 0} {$y < [llength $rightpads]} {incr y} {
+ set ypos [lindex $rightpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $bottompady
+for {set x 0} {$x < [llength $bottompads]} {incr x} {
+ set xpos [lindex $bottompads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+# Now route between the wirebond pads and the bump bond pads
+# routes start centered on the wirebond pad and align to grid points
+# on a 1/2 ball pitch, although positions do not need to be on
+# integer values. The overlaid grid starts 1/2 pitch to the left
+# and below the center of the bottom left bump bond. Grid columns
+# are numbered 0 to 12, and grid rows are numbered 0 to 20. To
+# convert to a micron unit coordinate, use the to_grid procedure
+# defined below.
+
+set gridllx [- $llx 250.0]
+set gridlly [- $lly 250.0]
+set gridpitchx 250.0
+set gridpitchy 250.0
+
+proc to_grid {x y} {
+ global gridllx gridlly
+ set coords []
+ catch {lappend coords [+ $gridllx [* 250.0 $x]]}
+ catch {lappend coords [+ $gridlly [* 250.0 $y]]}
+ return $coords
+}
+
+# Detailed routing, scanning left to right and from bottom to top.
+# (This really needs to be automated. . .)
+
+set wire_width 40.0
+
+# A10 vccd
+set coords [list $leftpadx [lindex $leftpads 0]]
+lappend coords {*}[to_grid -0.8 1]
+lappend coords {*}[to_grid 1 1]
+draw_pad_route $coords $wire_width
+
+# B10 resetb
+set coords [list [lindex $bottompads 1] $bottompady]
+lappend coords {*}[to_grid 1.9 0.2]
+lappend coords {*}[to_grid 2.2 0.2]
+lappend coords {*}[to_grid 3 1]
+draw_pad_route $coords $wire_width
+
+# C10 flash csb
+set coords [list [lindex $bottompads 4] $bottompady]
+lappend coords {*}[to_grid 5 0]
+lappend coords {*}[to_grid 5 1]
+draw_pad_route $coords $wire_width
+
+# D10 flash io0
+set coords [list [lindex $bottompads 6] $bottompady]
+lappend coords {*}[to_grid 7 0]
+lappend coords {*}[to_grid 7 1]
+draw_pad_route $coords $wire_width
+
+# E10 gpio
+set coords [list [lindex $bottompads 8] $bottompady]
+lappend coords {*}[to_grid 9 0.2]
+lappend coords {*}[to_grid 9 1]
+draw_pad_route $coords $wire_width
+
+# F10 vdda
+set coords [list [lindex $bottompads 10] $bottompady]
+lappend coords {*}[to_grid 11 0.3]
+lappend coords {*}[to_grid 11 1]
+draw_pad_route $coords $wire_width
+
+# A9 mprj_io[37]
+set coords [list $leftpadx [lindex $leftpads 2]]
+lappend coords {*}[to_grid -0.5 3]
+lappend coords {*}[to_grid 1 3]
+draw_pad_route $coords $wire_width
+
+# B9 mprj_io[36]
+set coords [list $leftpadx [lindex $leftpads 3]]
+lappend coords {*}[to_grid -0.6 4]
+lappend coords {*}[to_grid 2 4]
+lappend coords {*}[to_grid 3 3]
+draw_pad_route $coords $wire_width
+
+# C9 clock
+set coords [list [lindex $bottompads 2] $bottompady]
+lappend coords {*}[to_grid 3 0.2]
+lappend coords {*}[to_grid 3.4 0.2]
+lappend coords {*}[to_grid 3.8 0.6]
+lappend coords {*}[to_grid 3.8 1.6]
+lappend coords {*}[to_grid 4.5 2.3]
+lappend coords {*}[to_grid 4.5 2.5]
+lappend coords {*}[to_grid 5 3]
+draw_pad_route $coords $wire_width
+
+# D9 flash io1
+set coords [list [lindex $bottompads 7] $bottompady]
+lappend coords {*}[to_grid 8 0.1]
+lappend coords {*}[to_grid 8 1.3]
+lappend coords {*}[to_grid 7 2.3]
+lappend coords {*}[to_grid 7 3]
+draw_pad_route $coords $wire_width
+
+# E9 mprj_io[1]/SDO
+set coords [list $rightpadx [lindex $rightpads 1]]
+lappend coords {*}[to_grid 12.4 2.2]
+lappend coords {*}[to_grid 10.5 2.2]
+lappend coords {*}[to_grid 9.7 3]
+lappend coords {*}[to_grid 9 3]
+draw_pad_route $coords $wire_width
+
+# F9 mprj_io[2]/SDI
+set coords [list $rightpadx [lindex $rightpads 2]]
+lappend coords {*}[to_grid 12.3 3]
+lappend coords {*}[to_grid 11 3]
+draw_pad_route $coords $wire_width
+
+# A8 mprj_io[35]
+set coords [list $leftpadx [lindex $leftpads 4]]
+lappend coords {*}[to_grid -0.7 5]
+lappend coords {*}[to_grid 1 5]
+draw_pad_route $coords $wire_width
+
+# B8 mprj_io[34]
+set coords [list $leftpadx [lindex $leftpads 5]]
+lappend coords {*}[to_grid -0.7 5.8]
+lappend coords {*}[to_grid 2.2 5.8]
+lappend coords {*}[to_grid 3 5]
+draw_pad_route $coords $wire_width
+
+# C8 mprj_io[33]
+set coords [list $leftpadx [lindex $leftpads 6]]
+lappend coords {*}[to_grid -0.3 6.2]
+lappend coords {*}[to_grid 3.8 6.2]
+lappend coords {*}[to_grid 5 5]
+draw_pad_route $coords $wire_width
+
+# D8 flash clk
+set coords [list [lindex $bottompads 5] $bottompady]
+lappend coords {*}[to_grid 6 0]
+lappend coords {*}[to_grid 6 1]
+lappend coords {*}[to_grid 6.2 1.2]
+lappend coords {*}[to_grid 6.2 3.5]
+lappend coords {*}[to_grid 7 4.3]
+lappend coords {*}[to_grid 7 5]
+draw_pad_route $coords $wire_width
+
+# E8 mprj_io[3]/CSB
+set coords [list $rightpadx [lindex $rightpads 3]]
+lappend coords {*}[to_grid 12.4 4]
+lappend coords {*}[to_grid 10 4]
+lappend coords {*}[to_grid 9 5]
+draw_pad_route $coords $wire_width
+
+# F8 mrpj_io[4]/SCK
+set coords [list $rightpadx [lindex $rightpads 4]]
+lappend coords {*}[to_grid 12.5 5]
+lappend coords {*}[to_grid 11 5]
+draw_pad_route $coords $wire_width
+
+# A7 mrpj_io[32]
+set coords [list $leftpadx [lindex $leftpads 7]]
+lappend coords {*}[to_grid -0.2 7]
+lappend coords {*}[to_grid 1 7]
+draw_pad_route $coords $wire_width
+
+# B7 vssd2
+set coords [list $leftpadx [lindex $leftpads 8]]
+lappend coords {*}[to_grid -0.1 7.8]
+lappend coords {*}[to_grid 2.2 7.8]
+lappend coords {*}[to_grid 3 7]
+draw_pad_route $coords $wire_width
+
+# C7 vdda2
+set coords [list $leftpadx [lindex $leftpads 9]]
+lappend coords {*}[to_grid 0.3 8.2]
+lappend coords {*}[to_grid 2.3 8.2]
+lappend coords {*}[to_grid 2.5 8]
+lappend coords {*}[to_grid 4 8]
+lappend coords {*}[to_grid 5 7]
+draw_pad_route $coords $wire_width
+
+# D7 mrpj_io[0]/JTAG
+set coords [list $rightpadx [lindex $rightpads 0]]
+lappend coords {*}[to_grid 12.8 1.8]
+lappend coords {*}[to_grid 10.2 1.8]
+lappend coords {*}[to_grid 9.8 2.2]
+lappend coords {*}[to_grid 8.6 2.2]
+lappend coords {*}[to_grid 8.2 2.6]
+lappend coords {*}[to_grid 8.2 5.8]
+lappend coords {*}[to_grid 7 7]
+draw_pad_route $coords $wire_width
+
+# E7 mrpj_io[5]/ser_rx
+set coords [list $rightpadx [lindex $rightpads 5]]
+lappend coords {*}[to_grid 12.6 6]
+lappend coords {*}[to_grid 10 6]
+lappend coords {*}[to_grid 9 7]
+draw_pad_route $coords $wire_width
+
+# F7 mprj_io[6]/ser_tx
+set coords [list $rightpadx [lindex $rightpads 6]]
+lappend coords {*}[to_grid 12.7 7]
+lappend coords {*}[to_grid 11 7]
+draw_pad_route $coords $wire_width
+
+# A6 mprj_io[31]
+set coords [list $leftpadx [lindex $leftpads 10]]
+lappend coords {*}[to_grid -0.3 10.3]
+lappend coords {*}[to_grid 1 9]
+draw_pad_route $coords $wire_width
+
+# B6 mprj_io[30]
+set coords [list $leftpadx [lindex $leftpads 11]]
+lappend coords {*}[to_grid -0.5 10.8]
+lappend coords {*}[to_grid -0.3 10.8]
+lappend coords {*}[to_grid 0.5 10]
+lappend coords {*}[to_grid 2 10]
+lappend coords {*}[to_grid 3 9]
+draw_pad_route $coords $wire_width
+
+# C6 vssio/vssa/vssd: Connects to D6, D5, C5
+set coords [to_grid 5 9]
+lappend coords {*}[to_grid 5.65 9]
+lappend coords {*}[to_grid 5.85 9.2]
+lappend coords {*}[to_grid 6 9.2]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd
+set coords [to_grid 7 9]
+lappend coords {*}[to_grid 6.35 9]
+lappend coords {*}[to_grid 6.15 8.8]
+lappend coords {*}[to_grid 6 8.8]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 0] $bottompady]
+lappend coords {*}[to_grid 0.9 0.2]
+lappend coords {*}[to_grid 1.3 0.2]
+lappend coords {*}[to_grid 2 0.9]
+lappend coords {*}[to_grid 2 1.5]
+lappend coords {*}[to_grid 2.3 1.8]
+lappend coords {*}[to_grid 3.5 1.8]
+lappend coords {*}[to_grid 4.2 2.5]
+lappend coords {*}[to_grid 4.2 3.5]
+lappend coords {*}[to_grid 4.5 3.8]
+lappend coords {*}[to_grid 5.3 3.8]
+lappend coords {*}[to_grid 5.8 3.3]
+lappend coords {*}[to_grid 5.8 2.5]
+lappend coords {*}[to_grid 5.3 2]
+lappend coords {*}[to_grid 4.8 2]
+lappend coords {*}[to_grid 4.2 1.4]
+lappend coords {*}[to_grid 4.2 0.3]
+lappend coords {*}[list [lindex $bottompads 3] $bottompady]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 9] $bottompady]
+lappend coords {*}[to_grid 10 0.3]
+lappend coords {*}[to_grid 10 1.4]
+lappend coords {*}[to_grid 9.6 1.8]
+lappend coords {*}[to_grid 8.5 1.8]
+lappend coords {*}[to_grid 7.8 2.5]
+lappend coords {*}[to_grid 7.8 5.5]
+lappend coords {*}[to_grid 7.3 6]
+lappend coords {*}[to_grid 6.2 6]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $toppads 5] $toppady]
+lappend coords {*}[to_grid 6 19.7]
+lappend coords {*}[to_grid 6 16]
+lappend coords {*}[to_grid 5.8 15.8]
+lappend coords {*}[to_grid 5.8 12.2]
+lappend coords {*}[to_grid 6 12]
+lappend coords {*}[to_grid 6 8]
+lappend coords {*}[to_grid 6.2 7.8]
+lappend coords {*}[to_grid 6.2 4.3]
+lappend coords {*}[to_grid 5.5 3.6]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1
+set coords [list $rightpadx [lindex $rightpads 7]]
+lappend coords {*}[to_grid 12.8 8]
+lappend coords {*}[to_grid 10 8]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1 also goes to
+set coords [list [lindex $toppads 9] $toppady]
+lappend coords {*}[to_grid 10 19.5]
+lappend coords {*}[to_grid 10 18.5]
+lappend coords {*}[to_grid 9.5 18]
+lappend coords {*}[to_grid 8.5 18]
+lappend coords {*}[to_grid 8 17.5]
+lappend coords {*}[to_grid 8 16.5]
+lappend coords {*}[to_grid 7.5 16]
+lappend coords {*}[to_grid 6.7 16]
+lappend coords {*}[to_grid 6.2 15.5]
+lappend coords {*}[to_grid 6.2 12.6]
+lappend coords {*}[to_grid 6.7 12]
+lappend coords {*}[to_grid 7.3 12]
+lappend coords {*}[to_grid 7.8 11.5]
+lappend coords {*}[to_grid 7.8 10.2]
+lappend coords {*}[to_grid 8 10]
+lappend coords {*}[to_grid 8 9.3]
+lappend coords {*}[to_grid 8.3 9]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# F6 vssd1
+set coords [list $rightpadx [lindex $rightpads 8]]
+lappend coords {*}[to_grid 12.9 9]
+lappend coords {*}[to_grid 11 9]
+draw_pad_route $coords $wire_width
+
+# A5 mprj_io[29]
+set coords [list $leftpadx [lindex $leftpads 12]]
+lappend coords {*}[to_grid 0.2 11]
+lappend coords {*}[to_grid 1 11]
+draw_pad_route $coords $wire_width
+
+# B5 mprj_io[28]
+set coords [list $leftpadx [lindex $leftpads 13]]
+lappend coords {*}[to_grid 0 12]
+lappend coords {*}[to_grid 2 12]
+lappend coords {*}[to_grid 3 11]
+draw_pad_route $coords $wire_width
+
+# C5 vssio/vssa/vssd : Connects to D6, C6, D5
+set coords [to_grid 5 11]
+lappend coords {*}[to_grid 5.65 11]
+lappend coords {*}[to_grid 5.85 11.2]
+lappend coords {*}[to_grid 6 11.2]
+draw_pad_route $coords $wire_width
+
+# D5 vssio/vssa/vssd : Connects to D6, C6, C5
+set coords [to_grid 7 11]
+lappend coords {*}[to_grid 6.35 11]
+lappend coords {*}[to_grid 6.15 10.8]
+lappend coords {*}[to_grid 6 10.8]
+draw_pad_route $coords $wire_width
+
+# E5 mprj_io[7]/irq
+set coords [list $rightpadx [lindex $rightpads 10]]
+lappend coords {*}[to_grid 12.4 10.2]
+lappend coords {*}[to_grid 9.8 10.2]
+lappend coords {*}[to_grid 9 11]
+draw_pad_route $coords $wire_width
+
+# F5 mprj_io[8]/flash2 csb
+set coords [list $rightpadx [lindex $rightpads 11]]
+lappend coords {*}[to_grid 12.3 11]
+lappend coords {*}[to_grid 11 11]
+draw_pad_route $coords $wire_width
+
+# A4 mprj_io[27]
+set coords [list $leftpadx [lindex $leftpads 14]]
+lappend coords {*}[to_grid -0.1 13]
+lappend coords {*}[to_grid 1 13]
+draw_pad_route $coords $wire_width
+
+# B4 mprj_io[26]
+set coords [list $leftpadx [lindex $leftpads 15]]
+lappend coords {*}[to_grid -0.2 14]
+lappend coords {*}[to_grid 2 14]
+lappend coords {*}[to_grid 3 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio
+set coords [list $leftpadx [lindex $leftpads 1]]
+lappend coords {*}[to_grid -0.8 2]
+lappend coords {*}[to_grid 1.8 2]
+lappend coords {*}[to_grid 2 2.2]
+lappend coords {*}[to_grid 3.3 2.2]
+lappend coords {*}[to_grid 3.8 2.7]
+lappend coords {*}[to_grid 3.8 3.7]
+lappend coords {*}[to_grid 4.3 4.2]
+lappend coords {*}[to_grid 5.3 4.2]
+lappend coords {*}[to_grid 5.8 4.7]
+lappend coords {*}[to_grid 5.8 7.4]
+lappend coords {*}[to_grid 5.2 8]
+lappend coords {*}[to_grid 4.7 8]
+lappend coords {*}[to_grid 4 8.7]
+lappend coords {*}[to_grid 4 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio is also:
+set coords [list $leftpadx [lindex $leftpads 18]]
+lappend coords {*}[to_grid 0.1 16.2]
+lappend coords {*}[to_grid 1.6 16.2]
+lappend coords {*}[to_grid 2 15.8]
+lappend coords {*}[to_grid 3.4 15.8]
+lappend coords {*}[to_grid 4 15.2]
+lappend coords {*}[to_grid 4 13]
+lappend coords {*}[to_grid 5 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1
+set coords [list $rightpadx [lindex $rightpads 9]]
+lappend coords {*}[to_grid 12.8 9.8]
+lappend coords {*}[to_grid 9.7 9.8]
+lappend coords {*}[to_grid 9.5 10]
+lappend coords {*}[to_grid 8.8 10]
+lappend coords {*}[to_grid 8.2 10.6]
+lappend coords {*}[to_grid 8.2 11.8]
+lappend coords {*}[to_grid 7 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1 is also:
+set coords [list $rightpadx [lindex $rightpads 16]]
+lappend coords {*}[to_grid 12.6 15.8]
+lappend coords {*}[to_grid 8.4 15.8]
+lappend coords {*}[to_grid 8 15.4]
+lappend coords {*}[to_grid 8 12.4]
+lappend coords {*}[to_grid 7.8 12.2]
+draw_pad_route $coords $wire_width
+
+# E4 mprj_io[9]/flash2 sck
+set coords [list $rightpadx [lindex $rightpads 12]]
+lappend coords {*}[to_grid 12.4 12]
+lappend coords {*}[to_grid 10 12]
+lappend coords {*}[to_grid 9 13]
+draw_pad_route $coords $wire_width
+
+# F4 mprj_io[10]/flash2 io0
+set coords [list $rightpadx [lindex $rightpads 13]]
+lappend coords {*}[to_grid 12.5 13]
+lappend coords {*}[to_grid 11 13]
+draw_pad_route $coords $wire_width
+
+# A3 mprj_io[25]
+set coords [list $leftpadx [lindex $leftpads 16]]
+lappend coords {*}[to_grid -0.4 15]
+lappend coords {*}[to_grid 1 15]
+draw_pad_route $coords $wire_width
+
+# B3 vssa2
+set coords [list $leftpadx [lindex $leftpads 17]]
+lappend coords {*}[to_grid -0.4 15.8]
+lappend coords {*}[to_grid 0 15.8]
+lappend coords {*}[to_grid 1.3 15.8]
+lappend coords {*}[to_grid 2.2 15]
+lappend coords {*}[to_grid 3 15]
+draw_pad_route $coords $wire_width
+
+# C3 mprj_io[24]
+set coords [list $leftpadx [lindex $leftpads 20]]
+lappend coords {*}[to_grid 0 18]
+lappend coords {*}[to_grid 1.5 18]
+lappend coords {*}[to_grid 2 17.5]
+lappend coords {*}[to_grid 2 16.5]
+lappend coords {*}[to_grid 2.3 16.2]
+lappend coords {*}[to_grid 3.8 16.2]
+lappend coords {*}[to_grid 5 15]
+draw_pad_route $coords $wire_width
+
+# D3 mprj_io[13]
+set coords [list $rightpadx [lindex $rightpads 17]]
+lappend coords {*}[to_grid 12 16.2]
+lappend coords {*}[to_grid 8.2 16.2]
+lappend coords {*}[to_grid 7 15]
+draw_pad_route $coords $wire_width
+
+# E3 mprj_io[11]/flash2 io1
+set coords [list $rightpadx [lindex $rightpads 14]]
+lappend coords {*}[to_grid 12.6 14]
+lappend coords {*}[to_grid 10 14]
+lappend coords {*}[to_grid 9 15]
+draw_pad_route $coords $wire_width
+
+# F3 mprj_io[12]
+set coords [list $rightpadx [lindex $rightpads 15]]
+lappend coords {*}[to_grid 12.7 15]
+lappend coords {*}[to_grid 11 15]
+draw_pad_route $coords $wire_width
+
+# A2 vccd2
+set coords [list $leftpadx [lindex $leftpads 19]]
+lappend coords {*}[to_grid -0.4 17.5]
+lappend coords {*}[to_grid 0.5 17.5]
+lappend coords {*}[to_grid 1 17]
+draw_pad_route $coords $wire_width
+
+# B2 mprj_io[22]
+set coords [list [lindex $toppads 1] $toppady]
+lappend coords {*}[to_grid 2 19.7]
+lappend coords {*}[to_grid 2 18]
+lappend coords {*}[to_grid 3 17]
+draw_pad_route $coords $wire_width
+
+# C2 mprj_io[20]
+set coords [list [lindex $toppads 3] $toppady]
+lappend coords {*}[to_grid 4 19.7]
+lappend coords {*}[to_grid 4 18]
+lappend coords {*}[to_grid 5 17]
+draw_pad_route $coords $wire_width
+
+# D2 mprj_io[17]
+set coords [list [lindex $toppads 7] $toppady]
+lappend coords {*}[to_grid 8 19.7]
+lappend coords {*}[to_grid 8 18]
+lappend coords {*}[to_grid 7 17]
+draw_pad_route $coords $wire_width
+
+# E2 mprj_io[14]
+set coords [list $rightpadx [lindex $rightpads 19]]
+lappend coords {*}[to_grid 12.6 18.5]
+lappend coords {*}[to_grid 12 18.5]
+lappend coords {*}[to_grid 11.5 18]
+lappend coords {*}[to_grid 10 18]
+lappend coords {*}[to_grid 9 17]
+draw_pad_route $coords $wire_width
+
+# F2 vccd1
+set coords [list $rightpadx [lindex $rightpads 18]]
+lappend coords {*}[to_grid 12.5 17.5]
+lappend coords {*}[to_grid 11.5 17.5]
+lappend coords {*}[to_grid 11 17]
+draw_pad_route $coords $wire_width
+
+# A1 mprj_io[23]
+set coords [list [lindex $toppads 0] $toppady]
+lappend coords {*}[to_grid 1 19.7]
+lappend coords {*}[to_grid 1 19]
+draw_pad_route $coords $wire_width
+
+# B1 mprj_io[21]
+set coords [list [lindex $toppads 2] $toppady]
+lappend coords {*}[to_grid 3 19.7]
+lappend coords {*}[to_grid 3 19]
+draw_pad_route $coords $wire_width
+
+# C1 mprj_io[19]
+set coords [list [lindex $toppads 4] $toppady]
+lappend coords {*}[to_grid 5 19.7]
+lappend coords {*}[to_grid 5 19]
+draw_pad_route $coords $wire_width
+
+# D1 mrpj_io[18]
+set coords [list [lindex $toppads 6] $toppady]
+lappend coords {*}[to_grid 7 19.7]
+lappend coords {*}[to_grid 7 19]
+draw_pad_route $coords $wire_width
+
+# E1 mprj_io[16]
+set coords [list [lindex $toppads 8] $toppady]
+lappend coords {*}[to_grid 9.5 20]
+lappend coords {*}[to_grid 9.5 19.5]
+lappend coords {*}[to_grid 9 19]
+draw_pad_route $coords $wire_width
+
+# F1 mprj_io[15]
+set coords [list [lindex $toppads 10] $toppady]
+lappend coords {*}[to_grid 11 19.7]
+lappend coords {*}[to_grid 11 19]
+draw_pad_route $coords $wire_width
+
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/calibreSummary.py b/signoff/calibreSummary.py
new file mode 100755
index 0000000..86fdee3
--- /dev/null
+++ b/signoff/calibreSummary.py
@@ -0,0 +1,132 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import re
+import os
+
+parser = argparse.ArgumentParser(
+ description="Summarizes a Calibre summary report into a csv file.")
+
+parser.add_argument("--targetPath", "-t", required=True,
+ help="Summaries Path. All .summary files inside that path and its subdirectories will be parsed")
+
+parser.add_argument("--waivableList", "-w", required=False,
+ help="A file that contains white space separated list of waivable violations")
+
+parser.add_argument("--outputDirectory", "-o", required=False,
+ help="Output Directory")
+
+args = parser.parse_args()
+summaryFolder = os.path.abspath(args.targetPath)
+outputDirectory = args.outputDirectory
+if outputDirectory is None:
+ outputDirectory = summaryFolder
+
+if not os.path.exists(outputDirectory):
+ os.makedirs(outputDirectory)
+
+waiveList=[]
+if args.waivableList is not None:
+ waivableListFileOpener = open(args.waivableList,"r")
+ waiveList = waivableListFileOpener.read().split()
+ waivableListFileOpener.close()
+
+header = "RULE,Waivable,rule_letter,category,COUNT 1, COUNT 2\n"
+
+
+mainOutputFile = outputDirectory+'/'+os.path.basename(summaryFolder)+'_merged.csv'
+
+mainOutputFileOpener = open(mainOutputFile, "w+")
+mainOutputFileOpener.write(header)
+mainOutputFileOpener.close()
+
+
+nonwaivableOutputFile = outputDirectory+'/'+os.path.basename(summaryFolder)+'_non_waivable.csv'
+
+nonwaivableFileOpener = open(nonwaivableOutputFile, "w+")
+nonwaivableFileOpener.write(header)
+nonwaivableFileOpener.close()
+
+
+def getListOfFiles(dirName):
+ # create a list of file and sub directories
+ # names in the given directory
+ listOfFile = os.listdir(dirName)
+ allFiles = list()
+ # Iterate over all the entries
+ for entry in listOfFile:
+ # Create full path
+ fullPath = os.path.join(dirName, entry)
+ # If entry is a directory then get the list of files in this directory
+ if os.path.isdir(fullPath):
+ allFiles = allFiles + getListOfFiles(fullPath)
+ else:
+ allFiles.append(fullPath)
+ return allFiles
+
+
+def extractSummary(summaryFile):
+ summaryFileOpener = open(summaryFile,"r")
+ summaryContent = summaryFileOpener.read().split("\n")
+ summaryFileOpener.close()
+ rule_category=os.path.basename(os.path.dirname(summaryFile))
+ outputFile = outputDirectory+'/'+rule_category+'.'+os.path.basename(summaryFile)+'.csv'
+
+ splitter = "----------------------------------------------------------------------------------"
+ ruleCheckString = "RULECHECK RESULTS STATISTICS"
+
+ beginFlag = False
+
+ outputFileOpener = open(outputFile, "w+")
+ outputFileOpener.write(header)
+ outputFileOpener.close()
+
+ for line in summaryContent:
+ if line.find(ruleCheckString) != -1:
+ beginFlag = True
+
+ if beginFlag:
+ if line == splitter:
+ break
+
+ rule = re.findall(r'RULECHECK (\S+)\s*.*\s*TOTAL Result Count = (\d+)\s*\((\d+)\)', line)
+
+ if len(rule) == 1:
+ ruleName = rule[0][0]
+ rk=ruleName[0]
+ waivable= 'no'
+ if ruleName in waiveList:
+ waivable='yes'
+ elif int(rule[0][1]) + int(rule[0][2]) != 0:
+ nonwaivableFileOpener = open(nonwaivableOutputFile, "a+")
+ nonwaivableFileOpener.write(str(",".join((ruleName, waivable,rk,rule_category,rule[0][1],rule[0][2])))+'\n')
+ nonwaivableFileOpener.close()
+
+ outputFileOpener = open(outputFile, "a+")
+ outputFileOpener.write(str(",".join((ruleName, waivable,rk,rule_category,rule[0][1],rule[0][2])))+'\n')
+ outputFileOpener.close()
+
+ mainOutputFileOpener = open(mainOutputFile, "a+")
+ mainOutputFileOpener.write(str(",".join((ruleName, waivable,rk,rule_category,rule[0][1],rule[0][2])))+'\n')
+ mainOutputFileOpener.close()
+
+files = getListOfFiles(summaryFolder)
+for f in files:
+ extension = os.path.splitext(f)[1]
+ if extension == '.summary':
+ extractSummary(f)
diff --git a/signoff/cdrc.log b/signoff/cdrc.log
new file mode 100644
index 0000000..f12e58e
--- /dev/null
+++ b/signoff/cdrc.log
@@ -0,0 +1,2 @@
+caldrc-put: caravel_0001001f.gds af3442e65ea6e1cb749914713f6092616f346721 2021-02-18.04:38:32.UTC md5=90d34aab150e384d431cd0ce82772917 /mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/gds/caravel_0001001f.gds.gz [no-git-push]
+caldrc-post: caravel_0001001f.gds put=af3442e 2021-02-18.05:35:58.UTC md5=(no-gds-file) output755_pdk79-ge1e7d3aa3_drc676-g764ba65_prj673-gaf3442e_caravel_0001001f
diff --git a/signoff/cdrcpost/caravel_0001001f_merged.csv b/signoff/cdrcpost/caravel_0001001f_merged.csv
new file mode 100644
index 0000000..9d8489b
--- /dev/null
+++ b/signoff/cdrcpost/caravel_0001001f_merged.csv
@@ -0,0 +1,172 @@
+RULE,Waivable,rule_letter,category,COUNT 1, COUNT 2
+MR_dnwell.2,no,M,drcmr,0,0
+MR_nwell.1,no,M,drcmr,0,0
+MR_nwell.2a,no,M,drcmr,0,0
+MR_hvtp.1,no,M,drcmr,0,0
+MR_hvtp.2,no,M,drcmr,0,0
+MR_hvtr.1,no,M,drcmr,0,0
+MR_hvtr.2,no,M,drcmr,0,0
+MR_hvtr.2_a,no,M,drcmr,0,0
+MR_lvtn.1a,no,M,drcmr,0,0
+MR_lvtn.2,no,M,drcmr,0,0
+MR_ncm.1,no,M,drcmr,0,0
+MR_ncm.2a,no,M,drcmr,0,0
+MR_difftap.1,no,M,drcmr,0,0
+MR_difftap.1_a,no,M,drcmr,0,0
+MR_difftap.1_b,no,M,drcmr,0,0
+MR_difftap.1_c,no,M,drcmr,0,0
+MR_difftap.3,no,M,drcmr,0,0
+MR_tunm.1,no,M,drcmr,0,0
+MR_tunm.2,no,M,drcmr,0,0
+MR_poly.1a,no,M,drcmr,0,0
+MR_poly.2,no,M,drcmr,0,0
+MR_rpm.1a,no,M,drcmr,0,0
+MR_rpm.2,no,M,drcmr,0,0
+MR_urpm.1a,no,M,drcmr,0,0
+MR_urpm.2,no,M,drcmr,0,0
+MR_npc.1,no,M,drcmr,0,0
+MR_npc.2,no,M,drcmr,0,0
+MR_licon.1,no,M,drcmr,0,0
+MR_licon.1_a,no,M,drcmr,0,0
+MR_licon.1_b,no,M,drcmr,0,0
+MR_licon.13,no,M,drcmr,0,0
+MR_licon.13_a,no,M,drcmr,0,0
+MR_licon.17,no,M,drcmr,0,0
+MR_li.1,no,M,drcmr,0,0
+MR_li.3,no,M,drcmr,0,0
+MR_li.5,no,M,drcmr,0,0
+MR_li.6,no,M,drcmr,0,0
+MR_ct.1,no,M,drcmr,0,0
+MR_ct.1_a,no,M,drcmr,0,0
+MR_ct.1_b,no,M,drcmr,0,0
+MR_ct.2,no,M,drcmr,0,0
+MR_ct.3,no,M,drcmr,0,0
+MR_ct.3_a,no,M,drcmr,0,0
+MR_ct.3_b,no,M,drcmr,0,0
+MR_ct.4,no,M,drcmr,0,0
+MR_capm.1,no,M,drcmr,0,0
+MR_capm.2a,no,M,drcmr,0,0
+MR_capm.2b,no,M,drcmr,0,0
+MR_capm.2b_a,no,M,drcmr,0,0
+MR_capm.3,no,M,drcmr,0,0
+MR_capm.4,no,M,drcmr,0,0
+MR_capm.5,no,M,drcmr,0,0
+MR_cap2m.1,no,M,drcmr,0,0
+MR_cap2m.2a,no,M,drcmr,0,0
+MR_cap2m.2b,no,M,drcmr,0,0
+MR_cap2m.2b_a,no,M,drcmr,0,0
+MR_cap2m.3,no,M,drcmr,0,0
+MR_cap2m.4,no,M,drcmr,0,0
+MR_cap2m.5,no,M,drcmr,0,0
+MR_m1.1,no,M,drcmr,0,0
+MR_m1.2,no,M,drcmr,0,0
+MR_m1.3b,no,M,drcmr,0,0
+MR_m1.3a,no,M,drcmr,0,0
+MR_791_m1.4,no,M,drcmr,0,0
+MR_m1.4,no,M,drcmr,0,0
+MR_m1.4a,no,M,drcmr,0,0
+MR_m1.4a_a,no,M,drcmr,0,0
+MR_m1.5,no,M,drcmr,0,0
+MR_m1.6,no,M,drcmr,0,0
+MR_m1.7,no,M,drcmr,0,0
+MR_m1.7_a,no,M,drcmr,0,0
+MR_via.1a,no,M,drcmr,0,0
+MR_via.1a_a,no,M,drcmr,0,0
+MR_via.1a_b,no,M,drcmr,0,0
+MR_via.2,no,M,drcmr,0,0
+MR_via.3,no,M,drcmr,0,0
+MR_via.3_a,no,M,drcmr,0,0
+MR_via.3_b,no,M,drcmr,0,0
+MR_via.4a,no,M,drcmr,0,0
+MR_via.4a_a,no,M,drcmr,0,0
+MR_via.5a,no,M,drcmr,0,0
+MR_m2.1,no,M,drcmr,0,0
+MR_m2.2,no,M,drcmr,0,0
+MR_m2.3b,no,M,drcmr,0,0
+MR_m2.3a,no,M,drcmr,0,0
+MR_m2.4,no,M,drcmr,0,0
+MR_m2.4_a,no,M,drcmr,0,0
+MR_m2.5,no,M,drcmr,0,0
+MR_m2.6,no,M,drcmr,0,0
+MR_m2.7,no,M,drcmr,0,0
+MR_m2.7_a,no,M,drcmr,0,0
+MR_via2.1a,no,M,drcmr,0,0
+MR_via2.1a_a,no,M,drcmr,0,0
+MR_via2.1a_b,no,M,drcmr,0,0
+MR_via2.2,no,M,drcmr,0,0
+MR_via2.3,no,M,drcmr,0,0
+MR_via2.3_a,no,M,drcmr,0,0
+MR_via2.3_b,no,M,drcmr,0,0
+MR_via2.4,no,M,drcmr,0,0
+MR_via2.4_a,no,M,drcmr,0,0
+MR_via2.5,no,M,drcmr,0,0
+MR_m3.1,no,M,drcmr,0,0
+MR_m3.2,no,M,drcmr,0,0
+MR_m3.4,no,M,drcmr,0,0
+MR_m3.4_a,no,M,drcmr,0,0
+MR_m3.3d,no,M,drcmr,0,0
+MR_m3.3c,no,M,drcmr,0,0
+MR_via3.1,no,M,drcmr,0,0
+MR_via3.1_a,no,M,drcmr,0,0
+MR_via3.1_b,no,M,drcmr,0,0
+MR_via3.2,no,M,drcmr,0,0
+MR_via3.4,no,M,drcmr,0,0
+MR_via3.4_a,no,M,drcmr,0,0
+MR_via3.5,no,M,drcmr,0,0
+MR_m4.1,no,M,drcmr,0,0
+MR_m4.2,no,M,drcmr,0,0
+MR_m4.3,no,M,drcmr,0,0
+MR_m4.3_a,no,M,drcmr,0,0
+MR_m4.4a,no,M,drcmr,0,0
+MR_m4.5b,no,M,drcmr,0,0
+MR_m4.5a,no,M,drcmr,0,0
+MR_via4.1,no,M,drcmr,0,0
+MR_via4.1_a,no,M,drcmr,0,0
+MR_via4.1_b,no,M,drcmr,0,0
+MR_via4.2,no,M,drcmr,0,0
+MR_via4.3,no,M,drcmr,0,0
+MR_via4.3_a,no,M,drcmr,0,0
+MR_via4.3_b,no,M,drcmr,0,0
+MR_via4.4,no,M,drcmr,0,0
+MR_via4.4_a,no,M,drcmr,0,0
+MR_m5.1,no,M,drcmr,0,0
+MR_m5.2,no,M,drcmr,0,0
+MR_m5.3,no,M,drcmr,0,0
+MR_m5.3_a,no,M,drcmr,0,0
+MR_m5.4,no,M,drcmr,0,0
+MR_pad.2,no,M,drcmr,0,0
+MR_hvi.1,no,M,drcmr,0,0
+MR_hvi.2a,no,M,drcmr,0,0
+MR_hvntm.1,no,M,drcmr,0,0
+MR_hvntm.2,no,M,drcmr,0,0
+MR_cfom.waffle.1,no,M,drcmr,0,0
+MR_cfom.waffle.2,no,M,drcmr,0,0
+MR_cfom.waffle.2a,no,M,drcmr,0,0
+MR_cp1m.waffle.1,no,M,drcmr,0,0
+MR_cp1m.waffle.2a,no,M,drcmr,0,0
+MR_li1m.waffle.1,no,M,drcmr,0,0
+MR_li1m.waffle.2a,no,M,drcmr,0,0
+MR_cmm1.waffle.1,no,M,drcmr,0,0
+MR_cmm1.waffle.2,no,M,drcmr,0,0
+MR_cmm2.waffle.1,no,M,drcmr,0,0
+MR_cmm2.waffle.2,no,M,drcmr,0,0
+MR_cmm3.waffle.1,no,M,drcmr,0,0
+MR_cmm3.waffle.2,no,M,drcmr,0,0
+MR_cmm4.waffle.1,no,M,drcmr,0,0
+MR_cmm4.waffle.2,no,M,drcmr,0,0
+MR_cmm5.waffle.1,no,M,drcmr,0,0
+MR_cmm5.waffle.2,no,M,drcmr,0,0
+MR_cfom.pd.1d,no,M,drcmr,0,0
+MR_cfom.pd.1e,no,M,drcmr,0,0
+MR_cli1m.4,no,M,drcmr,0,0
+MR_cli1m.5,no,M,drcmr,0,0
+MR_cmm1.pd.3,no,M,drcmr,0,0
+MR_cmm1.pd.4,no,M,drcmr,0,0
+MR_cmm2.pd.3,no,M,drcmr,0,0
+MR_cmm2.pd.4,no,M,drcmr,0,0
+MR_cmm3.pd.3,no,M,drcmr,0,0
+MR_cmm3.pd.4,no,M,drcmr,0,0
+MR_cmm4.pd.3,no,M,drcmr,0,0
+MR_cmm4.pd.4,no,M,drcmr,0,0
+MR_cmm5.pd.4,no,M,drcmr,0,0
+MR_cmm5.pd.5,no,M,drcmr,0,0
diff --git a/signoff/cdrcpost/caravel_0001001f_non_waivable.csv b/signoff/cdrcpost/caravel_0001001f_non_waivable.csv
new file mode 100644
index 0000000..dd05cba
--- /dev/null
+++ b/signoff/cdrcpost/caravel_0001001f_non_waivable.csv
@@ -0,0 +1 @@
+RULE,Waivable,rule_letter,category,COUNT 1, COUNT 2
diff --git a/signoff/cdrcpost/drcmr.caravel_0001001f.drc.summary.csv b/signoff/cdrcpost/drcmr.caravel_0001001f.drc.summary.csv
new file mode 100644
index 0000000..9d8489b
--- /dev/null
+++ b/signoff/cdrcpost/drcmr.caravel_0001001f.drc.summary.csv
@@ -0,0 +1,172 @@
+RULE,Waivable,rule_letter,category,COUNT 1, COUNT 2
+MR_dnwell.2,no,M,drcmr,0,0
+MR_nwell.1,no,M,drcmr,0,0
+MR_nwell.2a,no,M,drcmr,0,0
+MR_hvtp.1,no,M,drcmr,0,0
+MR_hvtp.2,no,M,drcmr,0,0
+MR_hvtr.1,no,M,drcmr,0,0
+MR_hvtr.2,no,M,drcmr,0,0
+MR_hvtr.2_a,no,M,drcmr,0,0
+MR_lvtn.1a,no,M,drcmr,0,0
+MR_lvtn.2,no,M,drcmr,0,0
+MR_ncm.1,no,M,drcmr,0,0
+MR_ncm.2a,no,M,drcmr,0,0
+MR_difftap.1,no,M,drcmr,0,0
+MR_difftap.1_a,no,M,drcmr,0,0
+MR_difftap.1_b,no,M,drcmr,0,0
+MR_difftap.1_c,no,M,drcmr,0,0
+MR_difftap.3,no,M,drcmr,0,0
+MR_tunm.1,no,M,drcmr,0,0
+MR_tunm.2,no,M,drcmr,0,0
+MR_poly.1a,no,M,drcmr,0,0
+MR_poly.2,no,M,drcmr,0,0
+MR_rpm.1a,no,M,drcmr,0,0
+MR_rpm.2,no,M,drcmr,0,0
+MR_urpm.1a,no,M,drcmr,0,0
+MR_urpm.2,no,M,drcmr,0,0
+MR_npc.1,no,M,drcmr,0,0
+MR_npc.2,no,M,drcmr,0,0
+MR_licon.1,no,M,drcmr,0,0
+MR_licon.1_a,no,M,drcmr,0,0
+MR_licon.1_b,no,M,drcmr,0,0
+MR_licon.13,no,M,drcmr,0,0
+MR_licon.13_a,no,M,drcmr,0,0
+MR_licon.17,no,M,drcmr,0,0
+MR_li.1,no,M,drcmr,0,0
+MR_li.3,no,M,drcmr,0,0
+MR_li.5,no,M,drcmr,0,0
+MR_li.6,no,M,drcmr,0,0
+MR_ct.1,no,M,drcmr,0,0
+MR_ct.1_a,no,M,drcmr,0,0
+MR_ct.1_b,no,M,drcmr,0,0
+MR_ct.2,no,M,drcmr,0,0
+MR_ct.3,no,M,drcmr,0,0
+MR_ct.3_a,no,M,drcmr,0,0
+MR_ct.3_b,no,M,drcmr,0,0
+MR_ct.4,no,M,drcmr,0,0
+MR_capm.1,no,M,drcmr,0,0
+MR_capm.2a,no,M,drcmr,0,0
+MR_capm.2b,no,M,drcmr,0,0
+MR_capm.2b_a,no,M,drcmr,0,0
+MR_capm.3,no,M,drcmr,0,0
+MR_capm.4,no,M,drcmr,0,0
+MR_capm.5,no,M,drcmr,0,0
+MR_cap2m.1,no,M,drcmr,0,0
+MR_cap2m.2a,no,M,drcmr,0,0
+MR_cap2m.2b,no,M,drcmr,0,0
+MR_cap2m.2b_a,no,M,drcmr,0,0
+MR_cap2m.3,no,M,drcmr,0,0
+MR_cap2m.4,no,M,drcmr,0,0
+MR_cap2m.5,no,M,drcmr,0,0
+MR_m1.1,no,M,drcmr,0,0
+MR_m1.2,no,M,drcmr,0,0
+MR_m1.3b,no,M,drcmr,0,0
+MR_m1.3a,no,M,drcmr,0,0
+MR_791_m1.4,no,M,drcmr,0,0
+MR_m1.4,no,M,drcmr,0,0
+MR_m1.4a,no,M,drcmr,0,0
+MR_m1.4a_a,no,M,drcmr,0,0
+MR_m1.5,no,M,drcmr,0,0
+MR_m1.6,no,M,drcmr,0,0
+MR_m1.7,no,M,drcmr,0,0
+MR_m1.7_a,no,M,drcmr,0,0
+MR_via.1a,no,M,drcmr,0,0
+MR_via.1a_a,no,M,drcmr,0,0
+MR_via.1a_b,no,M,drcmr,0,0
+MR_via.2,no,M,drcmr,0,0
+MR_via.3,no,M,drcmr,0,0
+MR_via.3_a,no,M,drcmr,0,0
+MR_via.3_b,no,M,drcmr,0,0
+MR_via.4a,no,M,drcmr,0,0
+MR_via.4a_a,no,M,drcmr,0,0
+MR_via.5a,no,M,drcmr,0,0
+MR_m2.1,no,M,drcmr,0,0
+MR_m2.2,no,M,drcmr,0,0
+MR_m2.3b,no,M,drcmr,0,0
+MR_m2.3a,no,M,drcmr,0,0
+MR_m2.4,no,M,drcmr,0,0
+MR_m2.4_a,no,M,drcmr,0,0
+MR_m2.5,no,M,drcmr,0,0
+MR_m2.6,no,M,drcmr,0,0
+MR_m2.7,no,M,drcmr,0,0
+MR_m2.7_a,no,M,drcmr,0,0
+MR_via2.1a,no,M,drcmr,0,0
+MR_via2.1a_a,no,M,drcmr,0,0
+MR_via2.1a_b,no,M,drcmr,0,0
+MR_via2.2,no,M,drcmr,0,0
+MR_via2.3,no,M,drcmr,0,0
+MR_via2.3_a,no,M,drcmr,0,0
+MR_via2.3_b,no,M,drcmr,0,0
+MR_via2.4,no,M,drcmr,0,0
+MR_via2.4_a,no,M,drcmr,0,0
+MR_via2.5,no,M,drcmr,0,0
+MR_m3.1,no,M,drcmr,0,0
+MR_m3.2,no,M,drcmr,0,0
+MR_m3.4,no,M,drcmr,0,0
+MR_m3.4_a,no,M,drcmr,0,0
+MR_m3.3d,no,M,drcmr,0,0
+MR_m3.3c,no,M,drcmr,0,0
+MR_via3.1,no,M,drcmr,0,0
+MR_via3.1_a,no,M,drcmr,0,0
+MR_via3.1_b,no,M,drcmr,0,0
+MR_via3.2,no,M,drcmr,0,0
+MR_via3.4,no,M,drcmr,0,0
+MR_via3.4_a,no,M,drcmr,0,0
+MR_via3.5,no,M,drcmr,0,0
+MR_m4.1,no,M,drcmr,0,0
+MR_m4.2,no,M,drcmr,0,0
+MR_m4.3,no,M,drcmr,0,0
+MR_m4.3_a,no,M,drcmr,0,0
+MR_m4.4a,no,M,drcmr,0,0
+MR_m4.5b,no,M,drcmr,0,0
+MR_m4.5a,no,M,drcmr,0,0
+MR_via4.1,no,M,drcmr,0,0
+MR_via4.1_a,no,M,drcmr,0,0
+MR_via4.1_b,no,M,drcmr,0,0
+MR_via4.2,no,M,drcmr,0,0
+MR_via4.3,no,M,drcmr,0,0
+MR_via4.3_a,no,M,drcmr,0,0
+MR_via4.3_b,no,M,drcmr,0,0
+MR_via4.4,no,M,drcmr,0,0
+MR_via4.4_a,no,M,drcmr,0,0
+MR_m5.1,no,M,drcmr,0,0
+MR_m5.2,no,M,drcmr,0,0
+MR_m5.3,no,M,drcmr,0,0
+MR_m5.3_a,no,M,drcmr,0,0
+MR_m5.4,no,M,drcmr,0,0
+MR_pad.2,no,M,drcmr,0,0
+MR_hvi.1,no,M,drcmr,0,0
+MR_hvi.2a,no,M,drcmr,0,0
+MR_hvntm.1,no,M,drcmr,0,0
+MR_hvntm.2,no,M,drcmr,0,0
+MR_cfom.waffle.1,no,M,drcmr,0,0
+MR_cfom.waffle.2,no,M,drcmr,0,0
+MR_cfom.waffle.2a,no,M,drcmr,0,0
+MR_cp1m.waffle.1,no,M,drcmr,0,0
+MR_cp1m.waffle.2a,no,M,drcmr,0,0
+MR_li1m.waffle.1,no,M,drcmr,0,0
+MR_li1m.waffle.2a,no,M,drcmr,0,0
+MR_cmm1.waffle.1,no,M,drcmr,0,0
+MR_cmm1.waffle.2,no,M,drcmr,0,0
+MR_cmm2.waffle.1,no,M,drcmr,0,0
+MR_cmm2.waffle.2,no,M,drcmr,0,0
+MR_cmm3.waffle.1,no,M,drcmr,0,0
+MR_cmm3.waffle.2,no,M,drcmr,0,0
+MR_cmm4.waffle.1,no,M,drcmr,0,0
+MR_cmm4.waffle.2,no,M,drcmr,0,0
+MR_cmm5.waffle.1,no,M,drcmr,0,0
+MR_cmm5.waffle.2,no,M,drcmr,0,0
+MR_cfom.pd.1d,no,M,drcmr,0,0
+MR_cfom.pd.1e,no,M,drcmr,0,0
+MR_cli1m.4,no,M,drcmr,0,0
+MR_cli1m.5,no,M,drcmr,0,0
+MR_cmm1.pd.3,no,M,drcmr,0,0
+MR_cmm1.pd.4,no,M,drcmr,0,0
+MR_cmm2.pd.3,no,M,drcmr,0,0
+MR_cmm2.pd.4,no,M,drcmr,0,0
+MR_cmm3.pd.3,no,M,drcmr,0,0
+MR_cmm3.pd.4,no,M,drcmr,0,0
+MR_cmm4.pd.3,no,M,drcmr,0,0
+MR_cmm4.pd.4,no,M,drcmr,0,0
+MR_cmm5.pd.4,no,M,drcmr,0,0
+MR_cmm5.pd.5,no,M,drcmr,0,0
diff --git a/signoff/compositor.out b/signoff/compositor.out
new file mode 100644
index 0000000..606e6d5
--- /dev/null
+++ b/signoff/compositor.out
@@ -0,0 +1,1280 @@
+Building final GDS file caravel_0001001f.gds
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/compose_final.tcl" from command line.
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+Creating new cell
+Creating new cell
+Scaled magic input cell advSeal_6um_gen geometry by factor of 2
+Writing final GDS. . .
+Scaled magic input cell seal_ring_corner_abstract geometry by factor of 2
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Scaled magic input cell alpha_F geometry by factor of 72
+Scaled magic input cell alpha_1 geometry by factor of 72
+Scaled magic input cell alpha_0 geometry by factor of 72
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_6D geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+chip_io: 10000 rects
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+Processing timestamp mismatches: gpio_control_block, open_source, copyright_block, alpha_1, alpha_F, user_id_textblock, seal_ring_corner_abstract.
+ Generating output for cell caravel_0001001f
+ Generating output for cell advSeal_6um_gen
+Reading "sealring_slots".
+Reading "seal_ring_slots_array".
+Reading "sr_polygon00011".
+Reading "sr_polygon00039".
+Reading "sr_polygon00035".
+Reading "sr_polygon00015".
+Reading "sr_polygon00007".
+Reading "sr_polygon00001".
+Reading "sr_polygon00002".
+Reading "sr_polygon00003".
+Reading "sr_polygon00004".
+Reading "sr_polygon00005".
+Reading "sr_polygon00006".
+Reading "nikon_sealring_shape".
+Reading "sr_polygon00019".
+Reading "sr_polygon00023".
+Reading "sr_polygon00027".
+Reading "sr_polygon00031".
+Reading "sr_polygon00036".
+Reading "sr_polygon00032".
+Reading "sr_polygon00016".
+Reading "sr_polygon00020".
+Reading "sr_polygon00024".
+Reading "sr_polygon00028".
+Reading "seal_ring_corner".
+Reading "advSeal_6um_gen".
+ Generating output for cell caravel_0001001f_fill_pattern
+Reading "caravel_0001001f_fill_pattern_5_7".
+Reading "caravel_0001001f_fill_pattern_4_7".
+Reading "caravel_0001001f_fill_pattern_3_7".
+Reading "caravel_0001001f_fill_pattern_2_7".
+Reading "caravel_0001001f_fill_pattern_1_7".
+Reading "caravel_0001001f_fill_pattern_0_7".
+Reading "caravel_0001001f_fill_pattern_5_6".
+Reading "caravel_0001001f_fill_pattern_4_6".
+Reading "caravel_0001001f_fill_pattern_3_6".
+Reading "caravel_0001001f_fill_pattern_2_6".
+Reading "caravel_0001001f_fill_pattern_1_6".
+Reading "caravel_0001001f_fill_pattern_0_6".
+Reading "caravel_0001001f_fill_pattern_5_5".
+Reading "caravel_0001001f_fill_pattern_4_5".
+Reading "caravel_0001001f_fill_pattern_3_5".
+Reading "caravel_0001001f_fill_pattern_2_5".
+Reading "caravel_0001001f_fill_pattern_1_5".
+Reading "caravel_0001001f_fill_pattern_0_5".
+Reading "caravel_0001001f_fill_pattern_5_4".
+Reading "caravel_0001001f_fill_pattern_4_4".
+Reading "caravel_0001001f_fill_pattern_3_4".
+Reading "caravel_0001001f_fill_pattern_2_4".
+Reading "caravel_0001001f_fill_pattern_1_4".
+Reading "caravel_0001001f_fill_pattern_0_4".
+Reading "caravel_0001001f_fill_pattern_5_3".
+Reading "caravel_0001001f_fill_pattern_4_3".
+Reading "caravel_0001001f_fill_pattern_3_3".
+Reading "caravel_0001001f_fill_pattern_2_3".
+Reading "caravel_0001001f_fill_pattern_1_3".
+Reading "caravel_0001001f_fill_pattern_0_3".
+Reading "caravel_0001001f_fill_pattern_5_2".
+Reading "caravel_0001001f_fill_pattern_4_2".
+Reading "caravel_0001001f_fill_pattern_3_2".
+Reading "caravel_0001001f_fill_pattern_2_2".
+Reading "caravel_0001001f_fill_pattern_1_2".
+Reading "caravel_0001001f_fill_pattern_0_2".
+Reading "caravel_0001001f_fill_pattern_5_1".
+Reading "caravel_0001001f_fill_pattern_5_0".
+Reading "caravel_0001001f_fill_pattern_4_1".
+Reading "caravel_0001001f_fill_pattern_4_0".
+Reading "caravel_0001001f_fill_pattern_3_1".
+Reading "caravel_0001001f_fill_pattern_3_0".
+Reading "caravel_0001001f_fill_pattern_2_1".
+Reading "caravel_0001001f_fill_pattern_2_0".
+Reading "caravel_0001001f_fill_pattern_1_1".
+Reading "caravel_0001001f_fill_pattern_0_1".
+Reading "caravel_0001001f_fill_pattern_1_0".
+Reading "caravel_0001001f_fill_pattern_0_0".
+Reading "caravel_0001001f_fill_pattern".
+ Generating output for cell caravel
+Reading "alpha_F".
+Reading "alpha_1".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "font_73".
+Reading "font_6C".
+Reading "font_65".
+Reading "font_61".
+Reading "font_62".
+Reading "font_66".
+Reading "font_20".
+Reading "font_29".
+Reading "font_28".
+Reading "font_43".
+Reading "font_76".
+Reading "font_72".
+Reading "font_2D".
+Reading "font_4B".
+Reading "font_44".
+Reading "font_50".
+Reading "font_6E".
+Reading "font_70".
+Reading "font_6F".
+Reading "font_74".
+Reading "font_57".
+Reading "font_6B".
+Reading "font_79".
+Reading "font_53".
+Reading "font_67".
+Reading "font_47".
+Reading "font_30".
+Reading "font_32".
+Reading "font_6D".
+Reading "font_63".
+Reading "copyright_block".
+Reading "open_source".
+Reading "dT_sky130_fd_sc_hd__diode_2".
+Reading "dT_sky130_fd_sc_hd__fill_2".
+Reading "dT_sky130_fd_sc_hd__decap_3".
+Reading "dT_sky130_fd_sc_hd__decap_12".
+Reading "dT_sky130_fd_sc_hd__decap_8".
+Reading "dT_sky130_fd_sc_hd__decap_6".
+Reading "dT_sky130_fd_sc_hd__decap_4".
+Reading "dT_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "dT_sky130_fd_sc_hd__fill_1".
+Reading "dT_pk_contact_17".
+Reading "dT_pk_contact_11".
+Reading "dT_pk_contact_13".
+Reading "dT_pk_contact_18".
+Reading "dT_pk_nmos_m1_w0_360_sli_dli_da_p".
+Reading "dT_pk_pmos_m1_w1_120_sli_dli_da_p".
+Reading "dT_pk_nmos_m2_w0_740_sli_dli_da_p".
+Reading "dT_pk_contact_24".
+Reading "dT_pk_contact_23".
+Reading "dT_pk_pmos_m2_w1_120_sli_dli_da_p".
+Reading "dT_pk_contact_7".
+Reading "dT_pk_contact_12".
+Reading "dT_pk_nmos_m10_w7_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m1_w0_740_sactive_dli".
+Reading "dT_pk_pmos_m1_w1_120_sli_dli".
+Reading "dT_pk_pinv".
+Reading "dT_pk_pmos_m10_w7_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m1_w0_740_sli_dactive".
+Reading "dT_pk_nand2_dec".
+Reading "dT_pk_pinv_dec".
+Reading "dT_pk_nand3_dec".
+Reading "dT_pk_nmos_m7_w1_680_sli_dli_da_p".
+Reading "dT_pk_pmos_m7_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m22_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m22_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m18_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m18_w2_000_sli_dli_da_p".
+Reading "dT_pk_contact_16".
+Reading "dT_pk_contact_15".
+Reading "dT_pk_pmos_m1_w0_550_sli_dli".
+Reading "dT_pk_contact_14".
+Reading "dT_pk_and2_dec".
+Reading "dT_pk_contact_29".
+Reading "dT_pk_contact_28".
+Reading "dT_pk_contact_26".
+Reading "dT_pk_nmos_m1_w2_880_sli_dli".
+Reading "dT_pk_pdriver".
+Reading "dT_pk_pnand2".
+Reading "dT_pk_nmos_m3_w1_680_sli_dli_da_p".
+Reading "dT_pk_contact_9".
+Reading "dT_pk_pinv_dec_0".
+Reading "dT_pk_contact_8".
+Reading "dT_pk_and3_dec".
+Reading "dT_pk_pmos_m3_w1_650_sli_dli_da_p".
+Reading "dT_pk_contact_27".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell".
+Reading "dT_pk_pmos_m2_w1_650_sli_dli_da_p".
+Reading "dT_pk_pinv_16".
+Reading "dT_pk_nmos_m2_w1_260_sli_dli_da_p".
+Reading "dT_pk_nmos_m40_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m5_w1_680_sli_dli_da_p".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "dT_pk_nmos_m24_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m4_w1_260_sli_dli_da_p".
+Reading "dT_pk_pmos_m4_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m3_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_17".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "dT_pk_write_driver".
+Reading "dT_pk_hierarchical_predecode3x8".
+Reading "dT_pk_hierarchical_predecode2x4".
+Reading "dT_pk_precharge_1".
+Reading "dT_pk_pmos_m5_w2_000_sli_dli_da_p".
+Reading "dT_pk_contact_22".
+Reading "dT_pk_contact_21".
+Reading "dT_pk_contact_20".
+Reading "dT_pk_contact_19".
+Reading "dT_pk_single_level_column_mux".
+Reading "dT_pk_dff".
+Reading "dT_pk_nmos_m1_w0_740_sactive_dactive".
+Reading "dT_pk_pinv_1".
+Reading "dT_pk_sense_amp".
+Reading "dT_pk_single_level_column_mux_0".
+Reading "dT_pk_pmos_m3_w2_000_sli_dli_da_p".
+Reading "dT_pk_pand2".
+Reading "dT_pk_pmos_m40_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m24_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_2".
+Reading "dT_pk_precharge_0".
+Reading "dT_pk_nmos_m8_w1_680_sli_dli_da_p".
+Reading "dT_pk_wordline_driver".
+Reading "dT_pk_pinv_3".
+Reading "dT_pk_pmos_m13_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m13_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m8_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m12_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m12_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_15".
+Reading "dT_pk_row_cap_array".
+Reading "dT_pk_col_cap_array".
+Reading "dT_pk_dummy_array".
+Reading "dT_pk_row_cap_array_0".
+Reading "dT_pk_pdriver_3".
+Reading "dT_pk_replica_column".
+Reading "dT_pk_dff_buf_0".
+Reading "dT_pk_pinv_13".
+Reading "dT_pk_wordline_driver_array".
+Reading "dT_pk_pinv_11".
+Reading "dT_pk_pinv_9".
+Reading "dT_pk_pinv_8".
+Reading "dT_pk_pinv_7".
+Reading "dT_pk_pinv_14".
+Reading "dT_pk_replica_column_0".
+Reading "dT_pk_pdriver_4".
+Reading "dT_pk_pnand3".
+Reading "dT_pk_pinv_18".
+Reading "dT_pk_pinv_12".
+Reading "dT_pk_pinv_6".
+Reading "dT_pk_pnand2_0".
+Reading "dT_pk_hierarchical_decoder".
+Reading "dT_pk_pinv_0".
+Reading "dT_pk_single_level_column_mux_array_0".
+Reading "dT_pk_precharge_array_0".
+Reading "dT_pk_pinv_20".
+Reading "dT_pk_pdriver_0".
+Reading "dT_pk_single_level_column_mux_array".
+Reading "dT_pk_write_mask_and_array".
+Reading "dT_pk_write_driver_array".
+Reading "dT_pk_sense_amp_array".
+Reading "dT_pk_precharge_array".
+Reading "dT_pk_pinv_10".
+Reading "dT_pk_pinv_19".
+Reading "dT_pk_bitcell_array".
+Reading "dT_pk_dff_buf_array".
+Reading "dT_pk_pand3".
+Reading "dT_pk_pdriver_1".
+Reading "dT_pk_port_address".
+Reading "dT_pk_replica_bitcell_array".
+Reading "dT_pk_cr_0".
+Reading "dT_pk_contact_32".
+Reading "dT_pk_pdriver_5".
+Reading "dT_pk_pnand2_1".
+Reading "dT_pk_delay_chain".
+Reading "dT_pk_pand3_0".
+Reading "dT_pk_pdriver_2".
+Reading "dT_pk_pand2_0".
+Reading "dT_pk_pinvbuf".
+Reading "dT_pk_port_data_0".
+Reading "dT_pk_contact_33".
+Reading "dT_pk_cr_1".
+Reading "dT_pk_port_data".
+Reading "dT_pk_cr_3".
+Reading "dT_pk_data_dff".
+Reading "dT_pk_wmask_dff".
+Reading "dT_pk_row_addr_dff".
+Reading "dT_pk_control_logic_rw".
+Reading "dT_pk_bank".
+Reading "dT_pk_control_logic_r".
+Reading "dT_pk_col_addr_dff".
+Reading "dT_pk_cr_2".
+Reading "dT_pk_contact_34".
+Reading "dT_pk_pk_sram_1rw1r_32_256_8_sky130".
+Reading "dT_sram_1rw1r_32_256_8_sky130".
+Reading "storage".
+Reading "GB_sky130_fd_sc_hvl__decap_4".
+Reading "GB_sky130_fd_sc_hvl__decap_8".
+Reading "GB_sky130_fd_sc_hvl__fill_1".
+Reading "GB_sky130_fd_sc_hvl__fill_2".
+Reading "GB_sky130_fd_sc_hvl__diode_2".
+Reading "GB_sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped".
+Reading "ju_sky130_fd_sc_hd__dfrtp_4".
+Reading "ju_sky130_fd_sc_hd__decap_3".
+Reading "ju_sky130_fd_sc_hd__decap_12".
+Reading "ju_sky130_fd_sc_hd__decap_8".
+Reading "ju_sky130_fd_sc_hd__decap_4".
+Reading "ju_sky130_fd_sc_hd__fill_1".
+Reading "ju_sky130_fd_sc_hd__buf_2".
+Reading "ju_sky130_fd_sc_hd__fill_2".
+Reading "ju_sky130_fd_sc_hd__decap_6".
+Reading "ju_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "ju_sky130_fd_sc_hd__dfstp_4".
+Reading "ju_sky130_fd_sc_hd__or2_4".
+Reading "ju_sky130_fd_sc_hd__diode_2".
+Reading "ju_sky130_fd_sc_hd__and3_4".
+Reading "ju_sky130_fd_sc_hd__inv_2".
+Reading "ju_sky130_fd_sc_hd__conb_1".
+Reading "ju_sky130_fd_sc_hd__nand2_4".
+Reading "ju_sky130_fd_sc_hd__clkbuf_16".
+Reading "ju_sky130_fd_sc_hd__ebufn_2".
+Reading "ju_sky130_fd_sc_hd__clkbuf_1".
+Reading "ju_sky130_fd_sc_hd__a32o_4".
+Reading "ju_sky130_fd_sc_hd__and2_4".
+Reading "ju_sky130_fd_sc_hd__einvp_8".
+Reading "gpio_control_block".
+Reading "fr_sky130_fd_sc_hd__decap_3".
+Reading "fr_sky130_fd_sc_hd__conb_1".
+Reading "fr_sky130_fd_sc_hd__fill_1".
+Reading "fr_sky130_fd_sc_hd__decap_8".
+Reading "fr_sky130_fd_sc_hd__fill_2".
+Reading "fr_sky130_fd_sc_hd__decap_6".
+Reading "fr_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "fr_sky130_fd_sc_hd__decap_4".
+Reading "fr_sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "RT_sky130_fd_sc_hvl__buf_8".
+Reading "RT_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "RT_sky130_fd_sc_hvl__inv_8".
+Reading "RT_sky130_fd_sc_hvl__fill_4".
+Reading "RT_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "RT_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "RT_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+Reading "TH_sky130_fd_sc_hd__conb_1".
+Reading "TH_sky130_fd_sc_hd__fill_1".
+Reading "TH_sky130_fd_sc_hd__decap_8".
+Reading "TH_sky130_fd_sc_hd__decap_3".
+Reading "TH_sky130_fd_sc_hd__decap_12".
+Reading "TH_sky130_fd_sc_hd__decap_4".
+Reading "TH_sky130_fd_sc_hd__buf_2".
+Reading "TH_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "TH_sky130_fd_sc_hd__inv_2".
+Reading "TH_sky130_fd_sc_hd__diode_2".
+Reading "TH_sky130_fd_sc_hd__fill_2".
+Reading "TH_sky130_fd_sc_hd__decap_6".
+Reading "TH_sky130_fd_sc_hd__a2bb2o_4".
+Reading "TH_sky130_fd_sc_hd__dfxtp_4".
+Reading "TH_sky130_fd_sc_hd__o22a_4".
+Reading "TH_sky130_fd_sc_hd__o21a_4".
+Reading "TH_sky130_fd_sc_hd__or2_4".
+Reading "TH_sky130_fd_sc_hd__and3_4".
+Reading "TH_sky130_fd_sc_hd__a22oi_4".
+Reading "TH_sky130_fd_sc_hd__and2_4".
+Reading "TH_sky130_fd_sc_hd__nand2_4".
+Reading "TH_sky130_fd_sc_hd__a21oi_4".
+Reading "TH_sky130_fd_sc_hd__or3_4".
+Reading "TH_sky130_fd_sc_hd__nor2_4".
+Reading "TH_sky130_fd_sc_hd__or4_4".
+Reading "TH_sky130_fd_sc_hd__and4_4".
+Reading "TH_sky130_fd_sc_hd__a32o_4".
+Reading "TH_sky130_fd_sc_hd__o21ai_4".
+Reading "TH_sky130_fd_sc_hd__a211o_4".
+Reading "TH_sky130_fd_sc_hd__a21o_4".
+Reading "TH_sky130_fd_sc_hd__buf_8".
+Reading "TH_sky130_fd_sc_hd__o32a_4".
+Reading "TH_sky130_fd_sc_hd__a21bo_4".
+Reading "TH_sky130_fd_sc_hd__a2111o_4".
+Reading "TH_sky130_fd_sc_hd__o41a_4".
+Reading "TH_sky130_fd_sc_hd__dfrtp_4".
+Reading "TH_sky130_fd_sc_hd__dfstp_4".
+Reading "TH_sky130_fd_sc_hd__ebufn_2".
+Reading "TH_sky130_fd_sc_hd__buf_4".
+Reading "TH_sky130_fd_sc_hd__clkbuf_8".
+Reading "TH_sky130_fd_sc_hd__dfxtp_1".
+Reading "TH_sky130_fd_sc_hd__clkbuf_16".
+Reading "TH_sky130_fd_sc_hd__and2_1".
+Reading "TH_sky130_fd_sc_hd__inv_1".
+Reading "TH_sky130_fd_sc_hd__dlclkp_1".
+Reading "TH_sky130_fd_sc_hd__ebufn_4".
+Reading "TH_sky130_fd_sc_hd__and4_2".
+Reading "TH_sky130_fd_sc_hd__and4bb_2".
+Reading "TH_sky130_fd_sc_hd__and4b_2".
+Reading "TH_sky130_fd_sc_hd__nor4b_2".
+Reading "TH_sky130_fd_sc_hd__clkbuf_4".
+Reading "TH_sky130_fd_sc_hd__nor3b_4".
+Reading "TH_sky130_fd_sc_hd__mux4_1".
+Reading "TH_sky130_fd_sc_hd__and3b_4".
+Reading "TH_DFFRAM".
+Reading "TH_sky130_fd_sc_hd__a41o_4".
+Reading "TH_sky130_fd_sc_hd__inv_4".
+Reading "TH_sky130_fd_sc_hd__clkbuf_1".
+Reading "TH_sky130_fd_sc_hd__clkinv_1".
+Reading "TH_sky130_fd_sc_hd__einvn_4".
+Reading "TH_sky130_fd_sc_hd__einvp_2".
+Reading "TH_sky130_fd_sc_hd__clkbuf_2".
+Reading "TH_sky130_fd_sc_hd__einvn_8".
+Reading "TH_sky130_fd_sc_hd__clkinv_8".
+Reading "TH_sky130_fd_sc_hd__clkinv_2".
+Reading "TH_sky130_fd_sc_hd__einvp_1".
+Reading "TH_sky130_fd_sc_hd__or2_2".
+Reading "TH_digital_pll".
+Reading "mgmt_core".
+Reading "rX_sky130_fd_sc_hd__decap_12".
+Reading "rX_sky130_fd_sc_hd__decap_3".
+Reading "rX_sky130_fd_sc_hd__decap_4".
+Reading "rX_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "rX_sky130_fd_sc_hd__decap_8".
+Reading "rX_sky130_fd_sc_hd__inv_2".
+Reading "rX_sky130_fd_sc_hd__fill_2".
+Reading "rX_sky130_fd_sc_hd__diode_2".
+Reading "rX_sky130_fd_sc_hd__fill_1".
+Reading "rX_sky130_fd_sc_hd__decap_6".
+Reading "rX_sky130_fd_sc_hd__buf_8".
+Reading "rX_sky130_fd_sc_hd__inv_8".
+Reading "rX_sky130_fd_sc_hd__conb_1".
+Reading "rX_mprj2_logic_high".
+Reading "rX_sky130_fd_sc_hvl__fill_2".
+Reading "rX_sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "rX_sky130_fd_sc_hvl__decap_8".
+Reading "rX_sky130_fd_sc_hvl__decap_4".
+Reading "rX_sky130_fd_sc_hvl__conb_1".
+Reading "rX_sky130_fd_sc_hvl__fill_1".
+Reading "rX_mgmt_protect_hv".
+Reading "rX_sky130_fd_sc_hd__einvp_8".
+Reading "rX_sky130_fd_sc_hd__nand2_4".
+Reading "rX_mprj_logic_high".
+Reading "mgmt_protect".
+Reading "i4_sky130_ef_io__com_bus_slice_20um".
+Reading "i4_sky130_fd_io__corner_bus_overlay".
+Reading "i4_sky130_ef_io__corner_pad".
+Reading "i4_sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "i4_sky130_ef_io__com_bus_slice_10um".
+Reading "i4_sky130_ef_io__com_bus_slice_5um".
+Reading "i4_sky130_ef_io__com_bus_slice_1um".
+Reading "i4_sky130_fd_io__com_bus_slice".
+Reading "i4_sky130_fd_io__com_bus_hookup".
+Reading "i4_sky130_fd_io__overlay_vssa_hvc".
+Reading "i4_sky130_ef_io__hvc_vdda_overlay".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "i4_sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "i4_sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808663".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "i4_sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808662".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "i4_sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "i4_sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "i4_sky130_fd_pr__gendlring__example_559591418081".
+Reading "i4_sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "i4_sky130_fd_pr__padplhp__example_559591418080".
+Reading "i4_sky130_fd_io__pad_esd".
+Reading "i4_sky130_fd_io__com_busses_esd".
+Reading "i4_sky130_fd_io__top_ground_hvc_wpad".
+Reading "i4_sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "i4_sky130_fd_io__xres_inv_hysv2".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "i4_sky130_fd_io__tk_tie_r_out_esd".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "i4_sky130_fd_io__res250_sub_small".
+Reading "i4_sky130_fd_io__res250only_small".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "i4_sky130_fd_io__com_res_weak_v2".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808148".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808149".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808150".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808151".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808158".
+Reading "i4_sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "i4_sky130_fd_io__gpio_buf_localesdv2".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "i4_sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "i4_sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "i4_sky130_fd_pr__via_pol1__example_559591418083".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "i4_sky130_fd_io__hvsbt_inv_x4".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "i4_sky130_fd_io__hvsbt_inv_x2".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "i4_sky130_fd_io__hvsbt_inv_x1".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "i4_sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "i4_sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "i4_sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "i4_sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "i4_sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "i4_sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "i4_sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "i4_sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808187".
+Reading "i4_sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "i4_sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808729".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "i4_sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "i4_sky130_fd_io__com_res_weak_bentbigres".
+Reading "i4_sky130_fd_io__com_res_weak".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "i4_sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "i4_sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "i4_sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "i4_sky130_fd_io__top_gpio_pad".
+Reading "i4_sky130_fd_io__com_busses".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "i4_sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "i4_sky130_fd_io__inv_1".
+Reading "i4_sky130_fd_io__tap_1".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "i4_sky130_fd_io__hvsbt_nand2".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "i4_sky130_fd_io__xres4v2_in_buf".
+Reading "i4_sky130_fd_io__top_xres4v2".
+Reading "i4_sky130_fd_io__com_bus_slice_m4".
+Reading "i4_sky130_fd_io__overlay_gpiov2_m4".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "i4_sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "i4_sky130_fd_io__amux_switch_1v2b".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "i4_sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "i4_sky130_fd_io__gpiov2_amx_inv4".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "i4_sky130_fd_io__amx_inv1".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr".
+Reading "i4_sky130_fd_io__xor2_1".
+Reading "i4_sky130_fd_io__nand2_1".
+Reading "i4_sky130_fd_io__nor2_1".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "i4_sky130_fd_io__hvsbt_nor".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "i4_sky130_fd_io__gpiov2_amux_nand5".
+Reading "i4_sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "i4_sky130_fd_io__gpiov2_amux_nand4".
+Reading "i4_sky130_fd_io__gpiov2_amux_decoder".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "i4_sky130_fd_io__gpiov2_amux_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "i4_sky130_fd_io__res75only_small".
+Reading "i4_sky130_fd_io__gpiov2_amux".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "i4_sky130_fd_io__gpiov2_in_buf".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "i4_sky130_fd_io__gpiov2_ipath_hvls".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "i4_sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "i4_sky130_fd_io__gpiov2_ipath_lvls".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "i4_sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "i4_sky130_fd_io__gpiov2_ibuf_se".
+Reading "i4_sky130_fd_io__gpiov2_buf_localesd".
+Reading "i4_sky130_fd_io__hvsbt_nand2v2".
+Reading "i4_sky130_fd_io__gpiov2_ictl_logic".
+Reading "i4_sky130_fd_io__gpiov2_ipath".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "i4_sky130_fd_io__hvsbt_inv_x8v2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "i4_sky130_fd_io__com_ctl_ls".
+Reading "i4_sky130_fd_io__hvsbt_inv_x8".
+Reading "i4_sky130_fd_io__com_ctl_hldv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "i4_sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "i4_sky130_fd_io__com_ctl_ls_v2".
+Reading "i4_sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "i4_sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "i4_sky130_fd_io__com_ctl_ls_1v2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "i4_sky130_fd_io__com_ctl_lsv2".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "i4_sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "i4_sky130_fd_io__gpiov2_ctl".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808374".
+Reading "i4_sky130_fd_io__gpio_dat_ls_1v2".
+Reading "i4_sky130_fd_io__gpio_dat_lsv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "i4_sky130_fd_io__com_cclat".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808625".
+Reading "i4_sky130_fd_io__com_opath_datoev2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "i4_sky130_fd_io__hvsbt_xor".
+Reading "i4_sky130_fd_io__hvsbt_xorv2".
+Reading "i4_sky130_fd_io__com_ctl_ls_octl".
+Reading "i4_sky130_fd_io__gpiov2_octl".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "i4_sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "i4_sky130_fd_io__gpiov2_octl_mux".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "i4_sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "i4_sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "i4_sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "i4_sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "i4_sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "i4_sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808299".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808300".
+Reading "i4_sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "i4_sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "i4_sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "i4_sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "i4_sky130_fd_io__gpiov2_obpredrvr".
+Reading "i4_sky130_fd_io__gpiov2_octl_dat".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "i4_sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "i4_sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "i4_sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "i4_sky130_fd_io__com_pudrvr_weakv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "i4_sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "i4_sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "i4_sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "i4_sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "i4_sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "i4_sky130_fd_io__gpio_odrvr_subv2".
+Reading "i4_sky130_fd_io__gpio_odrvrv2".
+Reading "i4_sky130_fd_io__gpio_opathv2".
+Reading "i4_sky130_fd_io__top_gpiov2".
+Reading "i4_sky130_fd_io__overlay_gpiov2".
+Reading "i4_sky130_ef_io__gpiov2_pad".
+Reading "i4_sky130_ef_io__gpiov2_pad_wrapped".
+Reading "i4_sky130_ef_io__lvc_vccd_overlay".
+Reading "i4_sky130_fd_io__overlay_vssd_lvc".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "i4_sky130_fd_io__gnd2gnd_strap".
+Reading "i4_sky130_fd_io__gnd2gnd_tap".
+Reading "i4_sky130_fd_io__gnd2gnd_diff".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808685".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808686".
+Reading "i4_sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "i4_sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "i4_sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808682".
+Reading "i4_sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808681".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "i4_sky130_fd_io__top_ground_lvc_wpad".
+Reading "i4_sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vssio_hvc".
+Reading "i4_sky130_ef_io__hvc_vssio_overlay".
+Reading "i4_sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vdda_hvc".
+Reading "i4_sky130_fd_io__hvc_clampv2".
+Reading "i4_sky130_fd_io__top_power_hvc_wpadv2".
+Reading "i4_sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vccd_lvc".
+Reading "i4_sky130_fd_io__top_power_lvc_wpad".
+Reading "i4_sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "i4_sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "i4_sky130_ef_io__disconnect_vccd_slice_5um".
+Reading "i4_sky130_fd_io__overlay_vddio_hvc".
+Reading "i4_sky130_ef_io__hvc_vddio_overlay".
+Reading "i4_sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "i4_sky130_ef_io__lvc_vccdx_overlay".
+Reading "i4_sky130_ef_io__vssd_lvc_clamped2_pad".
+Reading "i4_sky130_ef_io__vccd_lvc_clamped2_pad".
+Reading "chip_io".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "DFFRAM_4K".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "apb_sys_0".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "DMC_32x16HC".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "ibex_wrapper".
+Reading "user_project_wrapper".
+Reading "caravel".
+Error message output from magic:
+Warning: Parent cell lists instance of "alpha_F" at bad file path hexdigits/alpha_F.mag.
+The cell exists in the search paths at alpha_F.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "alpha_1" at bad file path hexdigits/alpha_1.mag.
+The cell exists in the search paths at alpha_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "alpha_0" at bad file path hexdigits/alpha_0.mag.
+The cell exists in the search paths at alpha_0.mag.
+The discovered version will be used.
+Done!
diff --git a/signoff/fill_generated b/signoff/fill_generated
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/signoff/fill_generated
diff --git a/signoff/generate_fill.out b/signoff/generate_fill.out
new file mode 100644
index 0000000..3749d5b
--- /dev/null
+++ b/signoff/generate_fill.out
@@ -0,0 +1,27067 @@
+This script will generate files caravel_0001001f_fill_pattern_x_y.gds
+Now generating fill patterns. This may take. . . quite. . . a while.
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill.tcl" from command line.
+Started: 02/17/2021 18:39:58
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "alpha_F".
+Reading "alpha_1".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "font_73".
+Reading "font_6C".
+Reading "font_65".
+Reading "font_61".
+Reading "font_62".
+Reading "font_66".
+Reading "font_20".
+Reading "font_29".
+Reading "font_28".
+Reading "font_43".
+Reading "font_76".
+Reading "font_72".
+Reading "font_2D".
+Reading "font_4B".
+Reading "font_44".
+Reading "font_50".
+Reading "font_6E".
+Reading "font_70".
+Reading "font_6F".
+Reading "font_74".
+Reading "font_57".
+Reading "font_6B".
+Reading "font_79".
+Reading "font_53".
+Reading "font_67".
+Reading "font_47".
+Reading "font_30".
+Reading "font_32".
+Reading "font_6D".
+Reading "font_63".
+Reading "copyright_block".
+Reading "open_source".
+Reading "dT_sky130_fd_sc_hd__diode_2".
+Reading "dT_sky130_fd_sc_hd__fill_2".
+Reading "dT_sky130_fd_sc_hd__decap_3".
+Reading "dT_sky130_fd_sc_hd__decap_12".
+Reading "dT_sky130_fd_sc_hd__decap_8".
+Reading "dT_sky130_fd_sc_hd__decap_6".
+Reading "dT_sky130_fd_sc_hd__decap_4".
+Reading "dT_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "dT_sky130_fd_sc_hd__fill_1".
+Reading "dT_pk_contact_17".
+Reading "dT_pk_contact_11".
+Reading "dT_pk_contact_13".
+Reading "dT_pk_contact_18".
+Reading "dT_pk_nmos_m1_w0_360_sli_dli_da_p".
+Reading "dT_pk_pmos_m1_w1_120_sli_dli_da_p".
+Reading "dT_pk_nmos_m2_w0_740_sli_dli_da_p".
+Reading "dT_pk_contact_24".
+Reading "dT_pk_contact_23".
+Reading "dT_pk_pmos_m2_w1_120_sli_dli_da_p".
+Reading "dT_pk_contact_7".
+Reading "dT_pk_contact_12".
+Reading "dT_pk_nmos_m10_w7_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m1_w0_740_sactive_dli".
+Reading "dT_pk_pmos_m1_w1_120_sli_dli".
+Reading "dT_pk_pinv".
+Reading "dT_pk_pmos_m10_w7_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m1_w0_740_sli_dactive".
+Reading "dT_pk_nand2_dec".
+Reading "dT_pk_pinv_dec".
+Reading "dT_pk_nand3_dec".
+Reading "dT_pk_nmos_m7_w1_680_sli_dli_da_p".
+Reading "dT_pk_pmos_m7_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m22_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m22_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m18_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m18_w2_000_sli_dli_da_p".
+Reading "dT_pk_contact_16".
+Reading "dT_pk_contact_15".
+Reading "dT_pk_pmos_m1_w0_550_sli_dli".
+Reading "dT_pk_contact_14".
+Reading "dT_pk_and2_dec".
+Reading "dT_pk_contact_29".
+Reading "dT_pk_contact_28".
+Reading "dT_pk_contact_26".
+Reading "dT_pk_nmos_m1_w2_880_sli_dli".
+Reading "dT_pk_pdriver".
+Reading "dT_pk_pnand2".
+Reading "dT_pk_nmos_m3_w1_680_sli_dli_da_p".
+Reading "dT_pk_contact_9".
+Reading "dT_pk_pinv_dec_0".
+Reading "dT_pk_contact_8".
+Reading "dT_pk_and3_dec".
+Reading "dT_pk_pmos_m3_w1_650_sli_dli_da_p".
+Reading "dT_pk_contact_27".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell".
+Reading "dT_pk_pmos_m2_w1_650_sli_dli_da_p".
+Reading "dT_pk_pinv_16".
+Reading "dT_pk_nmos_m2_w1_260_sli_dli_da_p".
+Reading "dT_pk_nmos_m40_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m5_w1_680_sli_dli_da_p".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "dT_pk_nmos_m24_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m4_w1_260_sli_dli_da_p".
+Reading "dT_pk_pmos_m4_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m3_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_17".
+Reading "dT_pk_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "dT_pk_write_driver".
+Reading "dT_pk_hierarchical_predecode3x8".
+ 100 uses
+Reading "dT_pk_hierarchical_predecode2x4".
+Reading "dT_pk_precharge_1".
+Reading "dT_pk_pmos_m5_w2_000_sli_dli_da_p".
+Reading "dT_pk_contact_22".
+Reading "dT_pk_contact_21".
+Reading "dT_pk_contact_20".
+Reading "dT_pk_contact_19".
+Reading "dT_pk_single_level_column_mux".
+Reading "dT_pk_dff".
+Reading "dT_pk_nmos_m1_w0_740_sactive_dactive".
+Reading "dT_pk_pinv_1".
+Reading "dT_pk_sense_amp".
+Reading "dT_pk_single_level_column_mux_0".
+Reading "dT_pk_pmos_m3_w2_000_sli_dli_da_p".
+Reading "dT_pk_pand2".
+Reading "dT_pk_pmos_m40_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m24_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_2".
+Reading "dT_pk_precharge_0".
+Reading "dT_pk_nmos_m8_w1_680_sli_dli_da_p".
+Reading "dT_pk_wordline_driver".
+Reading "dT_pk_pinv_3".
+Reading "dT_pk_pmos_m13_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m13_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m8_w2_000_sli_dli_da_p".
+Reading "dT_pk_nmos_m12_w2_000_sli_dli_da_p".
+Reading "dT_pk_pmos_m12_w2_000_sli_dli_da_p".
+Reading "dT_pk_pinv_15".
+Reading "dT_pk_row_cap_array".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_col_cap_array".
+ 100 uses
+Reading "dT_pk_dummy_array".
+Reading "dT_pk_row_cap_array_0".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_pdriver_3".
+Reading "dT_pk_replica_column".
+ 100 uses
+Reading "dT_pk_dff_buf_0".
+Reading "dT_pk_pinv_13".
+Reading "dT_pk_wordline_driver_array".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_pinv_11".
+Reading "dT_pk_pinv_9".
+Reading "dT_pk_pinv_8".
+Reading "dT_pk_pinv_7".
+Reading "dT_pk_pinv_14".
+Reading "dT_pk_replica_column_0".
+ 100 uses
+Reading "dT_pk_pdriver_4".
+Reading "dT_pk_pnand3".
+Reading "dT_pk_pinv_18".
+Reading "dT_pk_pinv_12".
+Reading "dT_pk_pinv_6".
+Reading "dT_pk_pnand2_0".
+Reading "dT_pk_hierarchical_decoder".
+ 100 uses
+ 200 uses
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+Reading "dT_pk_pinv_0".
+Reading "dT_pk_single_level_column_mux_array_0".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+Reading "dT_pk_precharge_array_0".
+ 100 uses
+Reading "dT_pk_pinv_20".
+Reading "dT_pk_pdriver_0".
+Reading "dT_pk_single_level_column_mux_array".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+Reading "dT_pk_write_mask_and_array".
+Reading "dT_pk_write_driver_array".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_sense_amp_array".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_precharge_array".
+ 100 uses
+Reading "dT_pk_pinv_10".
+Reading "dT_pk_pinv_19".
+Reading "dT_pk_bitcell_array".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
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+ 8100 uses
+Reading "dT_pk_dff_buf_array".
+Reading "dT_pk_pand3".
+Reading "dT_pk_pdriver_1".
+Reading "dT_pk_port_address".
+Reading "dT_pk_replica_bitcell_array".
+Reading "dT_pk_cr_0".
+Reading "dT_pk_contact_32".
+Reading "dT_pk_pdriver_5".
+Reading "dT_pk_pnand2_1".
+Reading "dT_pk_delay_chain".
+ 100 uses
+ 200 uses
+ 300 uses
+Reading "dT_pk_pand3_0".
+Reading "dT_pk_pdriver_2".
+Reading "dT_pk_pand2_0".
+Reading "dT_pk_pinvbuf".
+Reading "dT_pk_port_data_0".
+Reading "dT_pk_contact_33".
+Reading "dT_pk_cr_1".
+Reading "dT_pk_port_data".
+Reading "dT_pk_cr_3".
+Reading "dT_pk_data_dff".
+ 100 uses
+ 200 uses
+Reading "dT_pk_wmask_dff".
+Reading "dT_pk_row_addr_dff".
+Reading "dT_pk_control_logic_rw".
+ 100 uses
+Reading "dT_pk_bank".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+Reading "dT_pk_control_logic_r".
+Reading "dT_pk_col_addr_dff".
+Reading "dT_pk_cr_2".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+Reading "dT_pk_contact_34".
+Reading "dT_pk_pk_sram_1rw1r_32_256_8_sky130".
+ 100 uses
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+ 150000 uses
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+ 155000 uses
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+ 155300 uses
+ 155400 uses
+ 155500 uses
+ 155600 uses
+ 155700 uses
+ 155800 uses
+Reading "dT_sram_1rw1r_32_256_8_sky130".
+Reading "storage".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+Reading "GB_sky130_fd_sc_hvl__decap_4".
+Reading "GB_sky130_fd_sc_hvl__decap_8".
+Reading "GB_sky130_fd_sc_hvl__fill_1".
+Reading "GB_sky130_fd_sc_hvl__fill_2".
+Reading "GB_sky130_fd_sc_hvl__diode_2".
+Reading "GB_sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped".
+Reading "ju_sky130_fd_sc_hd__dfrtp_4".
+Reading "ju_sky130_fd_sc_hd__decap_3".
+Reading "ju_sky130_fd_sc_hd__decap_12".
+Reading "ju_sky130_fd_sc_hd__decap_8".
+Reading "ju_sky130_fd_sc_hd__decap_4".
+Reading "ju_sky130_fd_sc_hd__fill_1".
+Reading "ju_sky130_fd_sc_hd__buf_2".
+Reading "ju_sky130_fd_sc_hd__fill_2".
+Reading "ju_sky130_fd_sc_hd__decap_6".
+Reading "ju_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "ju_sky130_fd_sc_hd__dfstp_4".
+Reading "ju_sky130_fd_sc_hd__or2_4".
+Reading "ju_sky130_fd_sc_hd__diode_2".
+Reading "ju_sky130_fd_sc_hd__and3_4".
+Reading "ju_sky130_fd_sc_hd__inv_2".
+Reading "ju_sky130_fd_sc_hd__conb_1".
+Reading "ju_sky130_fd_sc_hd__nand2_4".
+Reading "ju_sky130_fd_sc_hd__clkbuf_16".
+Reading "ju_sky130_fd_sc_hd__ebufn_2".
+Reading "ju_sky130_fd_sc_hd__clkbuf_1".
+Reading "ju_sky130_fd_sc_hd__a32o_4".
+Reading "ju_sky130_fd_sc_hd__and2_4".
+Reading "ju_sky130_fd_sc_hd__einvp_8".
+Reading "gpio_control_block".
+ 100 uses
+Reading "fr_sky130_fd_sc_hd__decap_3".
+Reading "fr_sky130_fd_sc_hd__conb_1".
+Reading "fr_sky130_fd_sc_hd__fill_1".
+Reading "fr_sky130_fd_sc_hd__decap_8".
+Reading "fr_sky130_fd_sc_hd__fill_2".
+Reading "fr_sky130_fd_sc_hd__decap_6".
+Reading "fr_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "fr_sky130_fd_sc_hd__decap_4".
+Reading "fr_sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+ 100 uses
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "RT_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "RT_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "RT_sky130_fd_sc_hvl__buf_8".
+Reading "RT_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "RT_sky130_fd_sc_hvl__inv_8".
+Reading "RT_sky130_fd_sc_hvl__fill_4".
+Reading "RT_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "RT_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "RT_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+Reading "TH_sky130_fd_sc_hd__conb_1".
+Reading "TH_sky130_fd_sc_hd__fill_1".
+Reading "TH_sky130_fd_sc_hd__decap_8".
+Reading "TH_sky130_fd_sc_hd__decap_3".
+Reading "TH_sky130_fd_sc_hd__decap_12".
+Reading "TH_sky130_fd_sc_hd__decap_4".
+Reading "TH_sky130_fd_sc_hd__buf_2".
+Reading "TH_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "TH_sky130_fd_sc_hd__inv_2".
+Reading "TH_sky130_fd_sc_hd__diode_2".
+Reading "TH_sky130_fd_sc_hd__fill_2".
+Reading "TH_sky130_fd_sc_hd__decap_6".
+Reading "TH_sky130_fd_sc_hd__a2bb2o_4".
+Reading "TH_sky130_fd_sc_hd__dfxtp_4".
+Reading "TH_sky130_fd_sc_hd__o22a_4".
+Reading "TH_sky130_fd_sc_hd__o21a_4".
+Reading "TH_sky130_fd_sc_hd__or2_4".
+Reading "TH_sky130_fd_sc_hd__and3_4".
+Reading "TH_sky130_fd_sc_hd__a22oi_4".
+Reading "TH_sky130_fd_sc_hd__and2_4".
+Reading "TH_sky130_fd_sc_hd__nand2_4".
+Reading "TH_sky130_fd_sc_hd__a21oi_4".
+Reading "TH_sky130_fd_sc_hd__or3_4".
+Reading "TH_sky130_fd_sc_hd__nor2_4".
+Reading "TH_sky130_fd_sc_hd__or4_4".
+Reading "TH_sky130_fd_sc_hd__and4_4".
+Reading "TH_sky130_fd_sc_hd__a32o_4".
+Reading "TH_sky130_fd_sc_hd__o21ai_4".
+Reading "TH_sky130_fd_sc_hd__a211o_4".
+Reading "TH_sky130_fd_sc_hd__a21o_4".
+Reading "TH_sky130_fd_sc_hd__buf_8".
+Reading "TH_sky130_fd_sc_hd__o32a_4".
+Reading "TH_sky130_fd_sc_hd__a21bo_4".
+Reading "TH_sky130_fd_sc_hd__a2111o_4".
+Reading "TH_sky130_fd_sc_hd__o41a_4".
+Reading "TH_sky130_fd_sc_hd__dfrtp_4".
+Reading "TH_sky130_fd_sc_hd__dfstp_4".
+Reading "TH_sky130_fd_sc_hd__ebufn_2".
+Reading "TH_sky130_fd_sc_hd__buf_4".
+Reading "TH_sky130_fd_sc_hd__clkbuf_8".
+Reading "TH_sky130_fd_sc_hd__dfxtp_1".
+Reading "TH_sky130_fd_sc_hd__clkbuf_16".
+Reading "TH_sky130_fd_sc_hd__and2_1".
+Reading "TH_sky130_fd_sc_hd__inv_1".
+Reading "TH_sky130_fd_sc_hd__dlclkp_1".
+Reading "TH_sky130_fd_sc_hd__ebufn_4".
+Reading "TH_sky130_fd_sc_hd__and4_2".
+Reading "TH_sky130_fd_sc_hd__and4bb_2".
+Reading "TH_sky130_fd_sc_hd__and4b_2".
+Reading "TH_sky130_fd_sc_hd__nor4b_2".
+Reading "TH_sky130_fd_sc_hd__clkbuf_4".
+Reading "TH_sky130_fd_sc_hd__nor3b_4".
+Reading "TH_sky130_fd_sc_hd__mux4_1".
+Reading "TH_sky130_fd_sc_hd__and3b_4".
+Reading "TH_DFFRAM".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
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+ 3000 uses
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+Reading "TH_sky130_fd_sc_hd__a41o_4".
+Reading "TH_sky130_fd_sc_hd__inv_4".
+Reading "TH_sky130_fd_sc_hd__clkbuf_1".
+Reading "TH_sky130_fd_sc_hd__clkinv_1".
+Reading "TH_sky130_fd_sc_hd__einvn_4".
+Reading "TH_sky130_fd_sc_hd__einvp_2".
+Reading "TH_sky130_fd_sc_hd__clkbuf_2".
+Reading "TH_sky130_fd_sc_hd__einvn_8".
+Reading "TH_sky130_fd_sc_hd__clkinv_8".
+Reading "TH_sky130_fd_sc_hd__clkinv_2".
+Reading "TH_sky130_fd_sc_hd__einvp_1".
+Reading "TH_sky130_fd_sc_hd__or2_2".
+Reading "TH_digital_pll".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
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+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+Reading "mgmt_core".
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+ 193000 uses
+ 193100 uses
+Reading "rX_sky130_fd_sc_hd__decap_12".
+Reading "rX_sky130_fd_sc_hd__decap_3".
+Reading "rX_sky130_fd_sc_hd__decap_4".
+Reading "rX_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "rX_sky130_fd_sc_hd__decap_8".
+Reading "rX_sky130_fd_sc_hd__inv_2".
+Reading "rX_sky130_fd_sc_hd__fill_2".
+Reading "rX_sky130_fd_sc_hd__diode_2".
+Reading "rX_sky130_fd_sc_hd__fill_1".
+Reading "rX_sky130_fd_sc_hd__decap_6".
+Reading "rX_sky130_fd_sc_hd__buf_8".
+Reading "rX_sky130_fd_sc_hd__inv_8".
+Reading "rX_sky130_fd_sc_hd__conb_1".
+Reading "rX_mprj2_logic_high".
+Reading "rX_sky130_fd_sc_hvl__fill_2".
+Reading "rX_sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "rX_sky130_fd_sc_hvl__decap_8".
+Reading "rX_sky130_fd_sc_hvl__decap_4".
+Reading "rX_sky130_fd_sc_hvl__conb_1".
+Reading "rX_sky130_fd_sc_hvl__fill_1".
+Reading "rX_mgmt_protect_hv".
+Reading "rX_sky130_fd_sc_hd__einvp_8".
+Reading "rX_sky130_fd_sc_hd__nand2_4".
+Reading "rX_mprj_logic_high".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+Reading "mgmt_protect".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
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+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
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+ 3000 uses
+ 3100 uses
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+ 3800 uses
+ 3900 uses
+ 4000 uses
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+ 5000 uses
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+ 6000 uses
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+ 7100 uses
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+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+Reading "i4_sky130_ef_io__com_bus_slice_20um".
+Reading "i4_sky130_fd_io__corner_bus_overlay".
+Reading "i4_sky130_ef_io__corner_pad".
+Reading "i4_sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "i4_sky130_ef_io__com_bus_slice_10um".
+Reading "i4_sky130_ef_io__com_bus_slice_5um".
+Reading "i4_sky130_ef_io__com_bus_slice_1um".
+Reading "i4_sky130_fd_io__com_bus_slice".
+Reading "i4_sky130_fd_io__com_bus_hookup".
+Reading "i4_sky130_fd_io__overlay_vssa_hvc".
+Reading "i4_sky130_ef_io__hvc_vdda_overlay".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "i4_sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "i4_sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808663".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "i4_sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808662".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "i4_sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "i4_sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "i4_sky130_fd_pr__gendlring__example_559591418081".
+Reading "i4_sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "i4_sky130_fd_pr__padplhp__example_559591418080".
+Reading "i4_sky130_fd_io__pad_esd".
+Reading "i4_sky130_fd_io__com_busses_esd".
+Reading "i4_sky130_fd_io__top_ground_hvc_wpad".
+ 100 uses
+Reading "i4_sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "i4_sky130_fd_io__xres_inv_hysv2".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "i4_sky130_fd_io__tk_tie_r_out_esd".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "i4_sky130_fd_io__res250_sub_small".
+Reading "i4_sky130_fd_io__res250only_small".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "i4_sky130_fd_io__com_res_weak_v2".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808148".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808149".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808150".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808151".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808158".
+Reading "i4_sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "i4_sky130_fd_io__gpio_buf_localesdv2".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "i4_sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "i4_sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "i4_sky130_fd_pr__via_pol1__example_559591418083".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "i4_sky130_fd_io__hvsbt_inv_x4".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "i4_sky130_fd_io__hvsbt_inv_x2".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "i4_sky130_fd_io__hvsbt_inv_x1".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "i4_sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "i4_sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "i4_sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "i4_sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "i4_sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "i4_sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "i4_sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "i4_sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808187".
+Reading "i4_sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "i4_sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "i4_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "i4_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808729".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "i4_sky130_fd_io__xres2v2_rcfilter_lpfv2".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "i4_sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "i4_sky130_fd_io__com_res_weak_bentbigres".
+Reading "i4_sky130_fd_io__com_res_weak".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "i4_sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "i4_sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "i4_sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "i4_sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "i4_sky130_fd_io__top_gpio_pad".
+Reading "i4_sky130_fd_io__com_busses".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "i4_sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "i4_sky130_fd_io__inv_1".
+Reading "i4_sky130_fd_io__tap_1".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "i4_sky130_fd_io__hvsbt_nand2".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "i4_sky130_fd_io__xres4v2_in_buf".
+Reading "i4_sky130_fd_io__top_xres4v2".
+Reading "i4_sky130_fd_io__com_bus_slice_m4".
+Reading "i4_sky130_fd_io__overlay_gpiov2_m4".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "i4_sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "i4_sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "i4_sky130_fd_io__amux_switch_1v2b".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "i4_sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "i4_sky130_fd_io__gpiov2_amx_inv4".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "i4_sky130_fd_io__amx_inv1".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_drvr".
+Reading "i4_sky130_fd_io__xor2_1".
+Reading "i4_sky130_fd_io__nand2_1".
+Reading "i4_sky130_fd_io__nor2_1".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "i4_sky130_fd_io__hvsbt_nor".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "i4_sky130_fd_io__gpiov2_amux_nand5".
+Reading "i4_sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "i4_sky130_fd_io__gpiov2_amux_nand4".
+Reading "i4_sky130_fd_io__gpiov2_amux_decoder".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "i4_sky130_fd_io__gpiov2_amux_ls".
+Reading "i4_sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "i4_sky130_fd_io__res75only_small".
+Reading "i4_sky130_fd_io__gpiov2_amux".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "i4_sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "i4_sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "i4_sky130_fd_io__gpiov2_in_buf".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "i4_sky130_fd_io__gpiov2_ipath_hvls".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "i4_sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "i4_sky130_fd_io__gpiov2_ipath_lvls".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "i4_sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "i4_sky130_fd_io__gpiov2_ibuf_se".
+Reading "i4_sky130_fd_io__gpiov2_buf_localesd".
+Reading "i4_sky130_fd_io__hvsbt_nand2v2".
+Reading "i4_sky130_fd_io__gpiov2_ictl_logic".
+Reading "i4_sky130_fd_io__gpiov2_ipath".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "i4_sky130_fd_io__hvsbt_inv_x8v2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "i4_sky130_fd_io__com_ctl_ls".
+Reading "i4_sky130_fd_io__hvsbt_inv_x8".
+Reading "i4_sky130_fd_io__com_ctl_hldv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "i4_sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "i4_sky130_fd_io__com_ctl_ls_v2".
+Reading "i4_sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "i4_sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "i4_sky130_fd_io__com_ctl_ls_1v2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "i4_sky130_fd_io__com_ctl_lsv2".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "i4_sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "i4_sky130_fd_io__gpiov2_ctl".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808374".
+Reading "i4_sky130_fd_io__gpio_dat_ls_1v2".
+Reading "i4_sky130_fd_io__gpio_dat_lsv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "i4_sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "i4_sky130_fd_io__com_cclat".
+ 100 uses
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808625".
+Reading "i4_sky130_fd_io__com_opath_datoev2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "i4_sky130_fd_io__hvsbt_xor".
+Reading "i4_sky130_fd_io__hvsbt_xorv2".
+Reading "i4_sky130_fd_io__com_ctl_ls_octl".
+Reading "i4_sky130_fd_io__gpiov2_octl".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "i4_sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "i4_sky130_fd_io__com_pdpredrvr_pbiasv2".
+ 100 uses
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "i4_sky130_fd_io__gpiov2_octl_mux".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "i4_sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "i4_sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "i4_sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "i4_sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "i4_sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "i4_sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "i4_sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "i4_sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "i4_sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "i4_sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "i4_sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "i4_sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808299".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808300".
+Reading "i4_sky130_fd_io__feascom_pupredrvr_nbiasv2".
+ 100 uses
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "i4_sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "i4_sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "i4_sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "i4_sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "i4_sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "i4_sky130_fd_io__gpiov2_obpredrvr".
+Reading "i4_sky130_fd_io__gpiov2_octl_dat".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "i4_sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "i4_sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "i4_sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "i4_sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "i4_sky130_fd_io__com_pudrvr_weakv2".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "i4_sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "i4_sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "i4_sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "i4_sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "i4_sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "i4_sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "i4_sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "i4_sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "i4_sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "i4_sky130_fd_io__gpio_odrvr_subv2".
+Reading "i4_sky130_fd_io__gpio_odrvrv2".
+Reading "i4_sky130_fd_io__gpio_opathv2".
+Reading "i4_sky130_fd_io__top_gpiov2".
+Reading "i4_sky130_fd_io__overlay_gpiov2".
+Reading "i4_sky130_ef_io__gpiov2_pad".
+Reading "i4_sky130_ef_io__gpiov2_pad_wrapped".
+Reading "i4_sky130_ef_io__lvc_vccd_overlay".
+Reading "i4_sky130_fd_io__overlay_vssd_lvc".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "i4_sky130_fd_io__gnd2gnd_strap".
+Reading "i4_sky130_fd_io__gnd2gnd_tap".
+Reading "i4_sky130_fd_io__gnd2gnd_diff".
+Reading "i4_sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808685".
+Reading "i4_sky130_fd_pr__tpl1__example_55959141808686".
+Reading "i4_sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "i4_sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "i4_sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "i4_sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808682".
+Reading "i4_sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "i4_sky130_fd_pr__dfl1__example_55959141808681".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "i4_sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "i4_sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "i4_sky130_fd_io__top_ground_lvc_wpad".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+Reading "i4_sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vssio_hvc".
+Reading "i4_sky130_ef_io__hvc_vssio_overlay".
+Reading "i4_sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vdda_hvc".
+Reading "i4_sky130_fd_io__hvc_clampv2".
+ 100 uses
+Reading "i4_sky130_fd_io__top_power_hvc_wpadv2".
+Reading "i4_sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "i4_sky130_fd_io__overlay_vccd_lvc".
+Reading "i4_sky130_fd_io__top_power_lvc_wpad".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+Reading "i4_sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "i4_sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "i4_sky130_ef_io__disconnect_vccd_slice_5um".
+Reading "i4_sky130_fd_io__overlay_vddio_hvc".
+Reading "i4_sky130_ef_io__hvc_vddio_overlay".
+Reading "i4_sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "i4_sky130_ef_io__lvc_vccdx_overlay".
+Reading "i4_sky130_ef_io__vssd_lvc_clamped2_pad".
+Reading "i4_sky130_ef_io__vccd_lvc_clamped2_pad".
+Reading "chip_io".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+Reading "sky130_ef_sc_hd__decap_12".
+Moving label "VGND" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Moving label "VNB" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Moving label "decap_12" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "DFFRAM_4K".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
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+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
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+ 4900 uses
+ 5000 uses
+ 5100 uses
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+ 6000 uses
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+ 7900 uses
+ 8000 uses
+ 8100 uses
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+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
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+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
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+ 10800 uses
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+ 11000 uses
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+ 12000 uses
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+ 62800 uses
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+ 68000 uses
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+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "apb_sys_0".
+ 100 uses
+ 200 uses
+ 300 uses
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+ 12900 uses
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+ 39000 uses
+ 39100 uses
+ 39200 uses
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "DMC_32x16HC".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
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+ 28000 uses
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+ 28300 uses
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "ibex_wrapper".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
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+ 62800 uses
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+ 63000 uses
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+ 63200 uses
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+Reading "user_project_wrapper".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
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+ 12900 uses
+ 13000 uses
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+Reading "caravel".
+Flattening layout of tile x=0 y=0. . .
+Flattening layout of tile x=1 y=0. . .
+Flattening layout of tile x=2 y=0. . .
+Flattening layout of tile x=3 y=0. . .
+Flattening layout of tile x=4 y=0. . .
+Flattening layout of tile x=5 y=0. . .
+Flattening layout of tile x=0 y=1. . .
+Flattening layout of tile x=1 y=1. . .
+Flattening layout of tile x=2 y=1. . .
+Flattening layout of tile x=3 y=1. . .
+Flattening layout of tile x=4 y=1. . .
+Flattening layout of tile x=5 y=1. . .
+Flattening layout of tile x=0 y=2. . .
+Flattening layout of tile x=1 y=2. . .
+Flattening layout of tile x=2 y=2. . .
+Flattening layout of tile x=3 y=2. . .
+Flattening layout of tile x=4 y=2. . .
+Flattening layout of tile x=5 y=2. . .
+Flattening layout of tile x=0 y=3. . .
+Flattening layout of tile x=1 y=3. . .
+Flattening layout of tile x=2 y=3. . .
+Flattening layout of tile x=3 y=3. . .
+Flattening layout of tile x=4 y=3. . .
+Flattening layout of tile x=5 y=3. . .
+Flattening layout of tile x=0 y=4. . .
+Flattening layout of tile x=1 y=4. . .
+Flattening layout of tile x=2 y=4. . .
+Flattening layout of tile x=3 y=4. . .
+Flattening layout of tile x=4 y=4. . .
+Flattening layout of tile x=5 y=4. . .
+Flattening layout of tile x=0 y=5. . .
+Flattening layout of tile x=1 y=5. . .
+Flattening layout of tile x=2 y=5. . .
+Flattening layout of tile x=3 y=5. . .
+Flattening layout of tile x=4 y=5. . .
+Flattening layout of tile x=5 y=5. . .
+Flattening layout of tile x=0 y=6. . .
+Flattening layout of tile x=1 y=6. . .
+Flattening layout of tile x=2 y=6. . .
+Flattening layout of tile x=3 y=6. . .
+Flattening layout of tile x=4 y=6. . .
+Flattening layout of tile x=5 y=6. . .
+Flattening layout of tile x=0 y=7. . .
+Flattening layout of tile x=1 y=7. . .
+Flattening layout of tile x=2 y=7. . .
+Flattening layout of tile x=3 y=7. . .
+Flattening layout of tile x=4 y=7. . .
+Flattening layout of tile x=5 y=7. . .
+Error message output from magic:
+CIF file read warning: CIF style sky130(): units rescaled by factor of 5 / 1
+Error while reading cell "dT_pk_control_logic_r" (byte position 6612948): Warning: Cell dT_pk_control_logic_r boundary was redefined.
+Error while reading cell "dT_pk_control_logic_r" (byte position 6612948): Warning: Cell dT_pk_control_logic_r boundary was redefined.
+Error while reading cell "dT_pk_control_logic_r" (byte position 6612948): Warning: Cell dT_pk_control_logic_r boundary was redefined.
+Error while reading cell "dT_pk_control_logic_r" (byte position 6612948): Warning: Cell dT_pk_control_logic_r boundary was redefined.
+Error while reading cell "dT_pk_control_logic_r" (byte position 6612948): Warning: Cell dT_pk_control_logic_r boundary was redefined.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204338350): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204338382): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204340974): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204341006): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204341038): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204341070): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204341102): NODE elements not supported: skipping.
+Error while reading cell "i4_sky130_fd_io__res250_sub_small" (byte position 204341198): NODE elements not supported: skipping.
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_final.tcl" from command line.
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Creating new cell
+Writing final GDS
+ Generating output for cell caravel_0001001f_fill_pattern
+ Generating output for cell caravel_0001001f_fill_pattern_0_0
+Reading "caravel_0001001f_fill_pattern_0_0".
+ Generating output for cell caravel_0001001f_fill_pattern_1_0
+Reading "caravel_0001001f_fill_pattern_1_0".
+ Generating output for cell caravel_0001001f_fill_pattern_0_1
+Reading "caravel_0001001f_fill_pattern_0_1".
+ Generating output for cell caravel_0001001f_fill_pattern_1_1
+Reading "caravel_0001001f_fill_pattern_1_1".
+ Generating output for cell caravel_0001001f_fill_pattern_2_0
+Reading "caravel_0001001f_fill_pattern_2_0".
+ Generating output for cell caravel_0001001f_fill_pattern_2_1
+Reading "caravel_0001001f_fill_pattern_2_1".
+ Generating output for cell caravel_0001001f_fill_pattern_3_0
+Reading "caravel_0001001f_fill_pattern_3_0".
+ Generating output for cell caravel_0001001f_fill_pattern_3_1
+Reading "caravel_0001001f_fill_pattern_3_1".
+ Generating output for cell caravel_0001001f_fill_pattern_4_0
+Reading "caravel_0001001f_fill_pattern_4_0".
+ Generating output for cell caravel_0001001f_fill_pattern_4_1
+Reading "caravel_0001001f_fill_pattern_4_1".
+ Generating output for cell caravel_0001001f_fill_pattern_5_0
+Reading "caravel_0001001f_fill_pattern_5_0".
+ Generating output for cell caravel_0001001f_fill_pattern_5_1
+Reading "caravel_0001001f_fill_pattern_5_1".
+ Generating output for cell caravel_0001001f_fill_pattern_0_2
+Reading "caravel_0001001f_fill_pattern_0_2".
+ Generating output for cell caravel_0001001f_fill_pattern_1_2
+Reading "caravel_0001001f_fill_pattern_1_2".
+ Generating output for cell caravel_0001001f_fill_pattern_2_2
+Reading "caravel_0001001f_fill_pattern_2_2".
+ Generating output for cell caravel_0001001f_fill_pattern_3_2
+Reading "caravel_0001001f_fill_pattern_3_2".
+ Generating output for cell caravel_0001001f_fill_pattern_4_2
+Reading "caravel_0001001f_fill_pattern_4_2".
+ Generating output for cell caravel_0001001f_fill_pattern_5_2
+Reading "caravel_0001001f_fill_pattern_5_2".
+ Generating output for cell caravel_0001001f_fill_pattern_0_3
+Reading "caravel_0001001f_fill_pattern_0_3".
+ Generating output for cell caravel_0001001f_fill_pattern_1_3
+Reading "caravel_0001001f_fill_pattern_1_3".
+ Generating output for cell caravel_0001001f_fill_pattern_2_3
+Reading "caravel_0001001f_fill_pattern_2_3".
+ Generating output for cell caravel_0001001f_fill_pattern_3_3
+Reading "caravel_0001001f_fill_pattern_3_3".
+ Generating output for cell caravel_0001001f_fill_pattern_4_3
+Reading "caravel_0001001f_fill_pattern_4_3".
+ Generating output for cell caravel_0001001f_fill_pattern_5_3
+Reading "caravel_0001001f_fill_pattern_5_3".
+ Generating output for cell caravel_0001001f_fill_pattern_0_4
+Reading "caravel_0001001f_fill_pattern_0_4".
+ Generating output for cell caravel_0001001f_fill_pattern_1_4
+Reading "caravel_0001001f_fill_pattern_1_4".
+ Generating output for cell caravel_0001001f_fill_pattern_2_4
+Reading "caravel_0001001f_fill_pattern_2_4".
+ Generating output for cell caravel_0001001f_fill_pattern_3_4
+Reading "caravel_0001001f_fill_pattern_3_4".
+ Generating output for cell caravel_0001001f_fill_pattern_4_4
+Reading "caravel_0001001f_fill_pattern_4_4".
+ Generating output for cell caravel_0001001f_fill_pattern_5_4
+Reading "caravel_0001001f_fill_pattern_5_4".
+ Generating output for cell caravel_0001001f_fill_pattern_0_5
+Reading "caravel_0001001f_fill_pattern_0_5".
+ Generating output for cell caravel_0001001f_fill_pattern_1_5
+Reading "caravel_0001001f_fill_pattern_1_5".
+ Generating output for cell caravel_0001001f_fill_pattern_2_5
+Reading "caravel_0001001f_fill_pattern_2_5".
+ Generating output for cell caravel_0001001f_fill_pattern_3_5
+Reading "caravel_0001001f_fill_pattern_3_5".
+ Generating output for cell caravel_0001001f_fill_pattern_4_5
+Reading "caravel_0001001f_fill_pattern_4_5".
+ Generating output for cell caravel_0001001f_fill_pattern_5_5
+Reading "caravel_0001001f_fill_pattern_5_5".
+ Generating output for cell caravel_0001001f_fill_pattern_0_6
+Reading "caravel_0001001f_fill_pattern_0_6".
+ Generating output for cell caravel_0001001f_fill_pattern_1_6
+Reading "caravel_0001001f_fill_pattern_1_6".
+ Generating output for cell caravel_0001001f_fill_pattern_2_6
+Reading "caravel_0001001f_fill_pattern_2_6".
+ Generating output for cell caravel_0001001f_fill_pattern_3_6
+Reading "caravel_0001001f_fill_pattern_3_6".
+ Generating output for cell caravel_0001001f_fill_pattern_4_6
+Reading "caravel_0001001f_fill_pattern_4_6".
+ Generating output for cell caravel_0001001f_fill_pattern_5_6
+Reading "caravel_0001001f_fill_pattern_5_6".
+ Generating output for cell caravel_0001001f_fill_pattern_0_7
+Reading "caravel_0001001f_fill_pattern_0_7".
+ Generating output for cell caravel_0001001f_fill_pattern_1_7
+Reading "caravel_0001001f_fill_pattern_1_7".
+ Generating output for cell caravel_0001001f_fill_pattern_2_7
+Reading "caravel_0001001f_fill_pattern_2_7".
+ Generating output for cell caravel_0001001f_fill_pattern_3_7
+Reading "caravel_0001001f_fill_pattern_3_7".
+ Generating output for cell caravel_0001001f_fill_pattern_4_7
+Reading "caravel_0001001f_fill_pattern_4_7".
+ Generating output for cell caravel_0001001f_fill_pattern_5_7
+Reading "caravel_0001001f_fill_pattern_5_7".
+Ended: 02/17/2021 19:31:50
+Done!
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_4.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_3_4: 10000 rects
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+caravel_0001001f_fill_pattern_3_4: 100000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_4
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_4.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_0.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+caravel_0001001f_fill_pattern_4_0: 2910000 rects
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+caravel_0001001f_fill_pattern_4_0: 3590000 rects
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+caravel_0001001f_fill_pattern_4_0: 3650000 rects
+caravel_0001001f_fill_pattern_4_0: 3660000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_4_0
+Error message output from magic:
+File caravel_0001001f_fill_pattern_4_0.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_7.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_4_7: 10000 rects
+caravel_0001001f_fill_pattern_4_7: 20000 rects
+caravel_0001001f_fill_pattern_4_7: 30000 rects
+caravel_0001001f_fill_pattern_4_7: 40000 rects
+caravel_0001001f_fill_pattern_4_7: 50000 rects
+caravel_0001001f_fill_pattern_4_7: 60000 rects
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+caravel_0001001f_fill_pattern_4_7: 80000 rects
+caravel_0001001f_fill_pattern_4_7: 90000 rects
+caravel_0001001f_fill_pattern_4_7: 100000 rects
+caravel_0001001f_fill_pattern_4_7: 110000 rects
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+caravel_0001001f_fill_pattern_4_7: 770000 rects
+caravel_0001001f_fill_pattern_4_7: 780000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_4_7
+Error message output from magic:
+File caravel_0001001f_fill_pattern_4_7.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_5_0.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_5_0: 10000 rects
+caravel_0001001f_fill_pattern_5_0: 20000 rects
+caravel_0001001f_fill_pattern_5_0: 30000 rects
+caravel_0001001f_fill_pattern_5_0: 40000 rects
+caravel_0001001f_fill_pattern_5_0: 50000 rects
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+caravel_0001001f_fill_pattern_5_0: 80000 rects
+caravel_0001001f_fill_pattern_5_0: 90000 rects
+caravel_0001001f_fill_pattern_5_0: 100000 rects
+caravel_0001001f_fill_pattern_5_0: 110000 rects
+caravel_0001001f_fill_pattern_5_0: 120000 rects
+caravel_0001001f_fill_pattern_5_0: 130000 rects
+caravel_0001001f_fill_pattern_5_0: 140000 rects
+caravel_0001001f_fill_pattern_5_0: 150000 rects
+caravel_0001001f_fill_pattern_5_0: 160000 rects
+caravel_0001001f_fill_pattern_5_0: 170000 rects
+caravel_0001001f_fill_pattern_5_0: 180000 rects
+caravel_0001001f_fill_pattern_5_0: 190000 rects
+caravel_0001001f_fill_pattern_5_0: 200000 rects
+caravel_0001001f_fill_pattern_5_0: 210000 rects
+caravel_0001001f_fill_pattern_5_0: 220000 rects
+caravel_0001001f_fill_pattern_5_0: 230000 rects
+caravel_0001001f_fill_pattern_5_0: 240000 rects
+caravel_0001001f_fill_pattern_5_0: 250000 rects
+caravel_0001001f_fill_pattern_5_0: 260000 rects
+caravel_0001001f_fill_pattern_5_0: 270000 rects
+caravel_0001001f_fill_pattern_5_0: 280000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_5_0
+Error message output from magic:
+File caravel_0001001f_fill_pattern_5_0.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_1.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_4_1: 10000 rects
+caravel_0001001f_fill_pattern_4_1: 20000 rects
+caravel_0001001f_fill_pattern_4_1: 30000 rects
+caravel_0001001f_fill_pattern_4_1: 40000 rects
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+caravel_0001001f_fill_pattern_4_1: 100000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_4_1
+Error message output from magic:
+File caravel_0001001f_fill_pattern_4_1.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_5.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_5
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_5.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_5_4.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_5_4: 10000 rects
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+caravel_0001001f_fill_pattern_5_4: 890000 rects
+caravel_0001001f_fill_pattern_5_4: 900000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_5_4
+Error message output from magic:
+File caravel_0001001f_fill_pattern_5_4.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_2.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_3_2: 10000 rects
+caravel_0001001f_fill_pattern_3_2: 20000 rects
+caravel_0001001f_fill_pattern_3_2: 30000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_2
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_2.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_3.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_3
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_3.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_4.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_4_4
+Error message output from magic:
+File caravel_0001001f_fill_pattern_4_4.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_6.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_4_6
+Error message output from magic:
+File caravel_0001001f_fill_pattern_4_6.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_6.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_6
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_6.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_2_2.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+caravel_0001001f_fill_pattern_2_2: 7710000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_2_2
+Error message output from magic:
+File caravel_0001001f_fill_pattern_2_2.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_2_7.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_2_7: 10000 rects
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+caravel_0001001f_fill_pattern_2_7: 1360000 rects
+caravel_0001001f_fill_pattern_2_7: 1370000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_2_7
+Error message output from magic:
+File caravel_0001001f_fill_pattern_2_7.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_1_4.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_1_4: 10000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_1_4
+Error message output from magic:
+File caravel_0001001f_fill_pattern_1_4.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_1_1.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_1_1
+Error message output from magic:
+File caravel_0001001f_fill_pattern_1_1.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_2_5.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_2_5
+Error message output from magic:
+File caravel_0001001f_fill_pattern_2_5.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_1.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_1
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_1.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_3_0.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_3_0
+Error message output from magic:
+File caravel_0001001f_fill_pattern_3_0.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_4.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_4
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_4.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_2.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+caravel_0001001f_fill_pattern_0_2: 5450000 rects
+caravel_0001001f_fill_pattern_0_2: 5460000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_2
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_2.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_7.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_0_7: 10000 rects
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+caravel_0001001f_fill_pattern_0_7: 960000 rects
+caravel_0001001f_fill_pattern_0_7: 970000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_7
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_7.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_5.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_0_5: 10000 rects
+caravel_0001001f_fill_pattern_0_5: 20000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_5
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_5.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_0.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_0
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_0.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_1_6.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_1_6
+Error message output from magic:
+File caravel_0001001f_fill_pattern_1_6.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_0_6.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
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+caravel_0001001f_fill_pattern_0_6: 4700000 rects
+caravel_0001001f_fill_pattern_0_6: 4710000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_0_6
+Error message output from magic:
+File caravel_0001001f_fill_pattern_0_6.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_1_2.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_1_2: 10000 rects
+caravel_0001001f_fill_pattern_1_2: 20000 rects
+caravel_0001001f_fill_pattern_1_2: 30000 rects
+caravel_0001001f_fill_pattern_1_2: 40000 rects
+caravel_0001001f_fill_pattern_1_2: 50000 rects
+caravel_0001001f_fill_pattern_1_2: 60000 rects
+caravel_0001001f_fill_pattern_1_2: 70000 rects
+caravel_0001001f_fill_pattern_1_2: 80000 rects
+caravel_0001001f_fill_pattern_1_2: 90000 rects
+caravel_0001001f_fill_pattern_1_2: 100000 rects
+caravel_0001001f_fill_pattern_1_2: 110000 rects
+caravel_0001001f_fill_pattern_1_2: 120000 rects
+caravel_0001001f_fill_pattern_1_2: 130000 rects
+caravel_0001001f_fill_pattern_1_2: 140000 rects
+caravel_0001001f_fill_pattern_1_2: 150000 rects
+caravel_0001001f_fill_pattern_1_2: 160000 rects
+caravel_0001001f_fill_pattern_1_2: 170000 rects
+caravel_0001001f_fill_pattern_1_2: 180000 rects
+caravel_0001001f_fill_pattern_1_2: 190000 rects
+caravel_0001001f_fill_pattern_1_2: 200000 rects
+caravel_0001001f_fill_pattern_1_2: 210000 rects
+caravel_0001001f_fill_pattern_1_2: 220000 rects
+caravel_00010
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_3.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_4_3: 10000 rects
+caravel_0001001f_fill_pattern_4_3: 20000 rects
+caravel_0001001f_fill_pattern_4_3: 30000 rects
+caravel_0001001f_fill_pattern_4_3: 40000 rects
+caravel_0001001f_fill_pattern_4_3: 50000 rects
+caravel_0001001f_fill_pattern_4_3: 60000 rects
+caravel_0001001f_fill_pattern_4_3: 70000 rects
+caravel_0001001f_fill_pattern_4_3: 80000 rects
+caravel_0001001f_fill_pattern_4_3: 90000 rects
+caravel_0001001f_fill_pattern_4_3: 100000 rects
+caravel_0001001f_fill_pattern_4_3: 110000 rects
+caravel_0001001f_fill_pattern_4_3: 120000 rects
+caravel_0001001f_fill_pattern_4_3: 130000 rects
+caravel_0001001f_fill_pattern_4_3: 140000 rects
+caravel_0001001f_fill_pattern_4_3: 150000 rects
+caravel_0001001f_fill_pattern_4_3: 160000 rects
+caravel_0001001f_fill_pattern_4_3: 170000 rects
+caravel_0001001f_fill_pattern_4_3: 180000 rects
+caravel_0001001f_fill_pattern_4_3: 190000 rects
+caravel_0001001f_fill_pattern_4_3: 200000 rects
+caravel_0001001f_fill_pattern_4_3: 210000 rects
+caravel_0001001f_fill_pattern_4_3: 220000 rects
+caravel_0001001f_fill_pattern_4_3: 230000 rects
+caravel_0001001f_fill_pattern_4_3: 240000 rects
+caravel_0001001f_fill_pattern_4_3: 250000 rects
+caravel_0001001f_fill_pattern_4_3: 260000 rects
+caravel_0001001f_fill_pattern_4_3: 270000 rects
+caravel_0001001f_fill_pattern_4_3: 280000 rects
+caravel_0001001f_fill_pattern_4_3: 290000 rects
+caravel_0001001f_fill_pattern_4_3: 300000 rects
+caravel_0001001f_fill_pattern_4_3: 310000 rects
+caravel_0001001f_fill_pattern_4_3: 320000 rects
+caravel_0001001f_fill_pattern_4_3: 330000 rects
+caravel_0001001f_fill_pattern_4_3: 340000 rects
+caravel_0001001f_fill_pattern_4_3: 350000 rects
+caravel_0001001f_fill_pattern_4_3: 360000 rects
+caravel_0001001f_fill_pattern_4_3: 370000 rects
+caravel_0001001f_fill_pattern_4_3: 380000 rects
+caravel_0001001f_fill_pattern_4_3: 390000 rects
+caravel_0001001f_fill_pattern_4_3: 400000 rects
+caravel_0001001f_fill_pattern_4_3: 410000 rects
+caravel_0001001f_fill_pattern_4_3: 420000 rects
+caravel_0001001f_fill_pattern_4_3: 430000 rects
+caravel_0001001f_fill_pattern_4_3: 440000 rects
+caravel_0001001f_fill_pattern_4_3: 450000 rects
+caravel_0001001f_fill_pattern_4_3: 460000 rects
+caravel_0001001f_fill_pattern_4_3: 470000 rects
+caravel_0001001f_fill_pattern_4_3: 480000 rects
+caravel_0001001f_fill_pattern_4_3: 490000 rects
+caravel_0001001f_fill_pattern_4_3: 500000 rects
+caravel_0001001f_fill_pattern_4_3: 510000 rects
+caravel_0001001f_fill_pattern_4_3: 520000 rects
+caravel_0001001f_fill_pattern_4_3: 530000 rects
+caravel_0001001f_fill_pattern_4_3: 540000 rects
+caravel_0001001f_fill_pattern_4_3: 550000 rects
+caravel_0001001f_fill_pattern_4_3: 560000 rects
+caravel_0001001f_fill_pattern_4_3: 570000 rects
+caravel_0001001f_fill_pattern_4_3: 580000 rects
+caravel_0001001f_fill_pattern_4_3: 590000 rects
+caravel_0001001f_fill_pattern_4_3: 600000 rects
+caravel_0001001f_fill_pattern_4_3: 610000 rects
+caravel_0001001f_fill_pattern_4_3: 620000 rects
+caravel_0001001f_fill_pattern_4_3: 630000 rects
+caravel_0001001f_fill_pattern_4_3: 640000 rects
+caravel_0001001f_fill_pattern_4_3: 650000 rects
+caravel_0001001f_fill_pattern_4_3: 660000 rects
+caravel_0001001f_fill_pattern_4_3: 670000 rects
+caravel_0001001f_fill_pattern_4_3: 680000 rects
+caravel_00010
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_5_2.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_5_2: 10000 rects
+caravel_0001001f_fill_pattern_5_2: 20000 rects
+caravel_0001001f_fill_pattern_5_2: 30000 rects
+caravel_0001001f_fill_pattern_5_2: 40000 rects
+caravel_0001001f_fill_pattern_5_2: 50000 rects
+caravel_0001001f_fill_pattern_5_2: 60000 rects
+caravel_0001001f_fill_pattern_5_2: 70000 rects
+caravel_0001001f_fill_pattern_5_2: 80000 rects
+caravel_0001001f_fill_pattern_5_2: 90000 rects
+caravel_0001001f_fill_pattern_5_2: 100000 rects
+caravel_0001001f_fill_pattern_5_2: 110000 rects
+caravel_0001001f_fill_pattern_5_2: 120000 rects
+caravel_0001001f_fill_pattern_5_2: 130000 rects
+caravel_0001001f_fill_pattern_5_2: 140000 rects
+caravel_0001001f_fill_pattern_5_2: 150000 rects
+caravel_0001001f_fill_pattern_5_2: 160000 rects
+caravel_0001001f_fill_pattern_5_2: 170000 rects
+caravel_0001001f_fill_pattern_5_2: 180000 rects
+caravel_0001001f_fill_pattern_5_2: 190000 rects
+caravel_0001001f_fill_pattern_5_2: 200000 rects
+caravel_0001001f_fill_pattern_5_2: 210000 rects
+caravel_0001001f_fill_pattern_5_2: 220000 rects
+caravel_0001001f_fill_pattern_5_2: 230000 rects
+caravel_0001001f_fill_pattern_5_2: 240000 rects
+caravel_0001001f_fill_pattern_5_2: 250000 rects
+caravel_0001001f_fill_pattern_5_2: 260000 rects
+caravel_0001001f_fill_pattern_5_2: 270000 rects
+caravel_0001001f_fill_pattern_5_2: 280000 rects
+caravel_0001001f_fill_pattern_5_2: 290000 rects
+caravel_0001001f_fill_pattern_5_2: 300000 rects
+caravel_0001001f_fill_pattern_5_2: 310000 rects
+caravel_0001001f_fill_pattern_5_2: 320000 rects
+caravel_0001001f_fill_pattern_5_2: 330000 rects
+caravel_0001001f_fill_pattern_5_2: 340000 rects
+caravel_0001001f_fill_pattern_5_2: 350000 rects
+caravel_0001001f_fill_pattern_5_2: 360000 rects
+caravel_0001001f_fill_pattern_5_2: 370000 rects
+caravel_0001001f_fill_pattern_5_2: 380000 rects
+caravel_0001001f_fill_pattern_5_2: 390000 rects
+caravel_0001001f_fill_pattern_5_2: 400000 rects
+caravel_0001001f_fill_pattern_5_2: 410000 rects
+caravel_0001001f_fill_pattern_5_2: 420000 rects
+caravel_0001001f_fill_pattern_5_2: 430000 rects
+caravel_0001001f_fill_pattern_5_2: 440000 rects
+caravel_0001001f_fill_pattern_5_2: 450000 rects
+caravel_0001001f_fill_pattern_5_2: 460000 rects
+caravel_0001001f_fill_pattern_5_2: 470000 rects
+caravel_0001001f_fill_pattern_5_2: 480000 rects
+caravel_0001001f_fill_pattern_5_2: 490000 rects
+caravel_0001001f_fill_pattern_5_2: 500000 rects
+caravel_0001001f_fill_pattern_5_2: 510000 rects
+caravel_0001001f_fill_pattern_5_2: 520000 rects
+caravel_0001001f_fill_pattern_5_2: 530000 rects
+caravel_0001001f_fill_pattern_5_2: 540000 rects
+caravel_0001001f_fill_pattern_5_2: 550000 rects
+caravel_0001001f_fill_pattern_5_2: 560000 rects
+caravel_0001001f_fill_pattern_5_2: 570000 rects
+caravel_0001001f_fill_pattern_5_2: 580000 rects
+caravel_0001001f_fill_pattern_5_2: 590000 rects
+caravel_0001001f_fill_pattern_5_2: 600000 rects
+caravel_0001001f_fill_pattern_5_2: 610000 rects
+caravel_0001001f_fill_pattern_5_2: 620000 rects
+caravel_0001001f_fill_pattern_5_2: 630000 rects
+caravel_0001001f_fill_pattern_5_2: 640000 rects
+caravel_0001001f_fill_pattern_5_2: 650000 rects
+caravel_0001001f_fill_pattern_5_2: 660000 rects
+caravel_0001001f_fill_pattern_5_2: 670000 rects
+caravel_0001001f_fill_pattern_5_2: 680000 rects
+caravel_00010
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_4_5.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_4_5: 10000 rects
+caravel_0001001f_fill_pattern_4_5: 20000 rects
+caravel_0001001f_fill_pattern_4_5: 30000 rects
+caravel_0001001f_fill_pattern_4_5: 40000 rects
+caravel_0001001f_fill_pattern_4_5: 50000 rects
+caravel_0001001f_fill_pattern_4_5: 60000 rects
+caravel_0001001f_fill_pattern_4_5: 70000 rects
+caravel_0001001f_fill_pattern_4_5: 80000 rects
+caravel_0001001f_fill_pattern_4_5: 90000 rects
+caravel_0001001f_fill_pattern_4_5: 100000 rects
+caravel_0001001f_fill_pattern_4_5: 110000 rects
+caravel_0001001f_fill_pattern_4_5: 120000 rects
+caravel_0001001f_fill_pattern_4_5: 130000 rects
+caravel_0001001f_fill_pattern_4_5: 140000 rects
+caravel_0001001f_fill_pattern_4_5: 150000 rects
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+caravel_0001001f_fill_pattern_4_5: 170000 rects
+caravel_0001001f_fill_pattern_4_5: 180000 rects
+caravel_0001001f_fill_pattern_4_5: 190000 rects
+caravel_0001001f_fill_pattern_4_5: 200000 rects
+caravel_0001001f_fill_pattern_4_5: 210000 rects
+caravel_0001001f_fill_pattern_4_5: 220000 rects
+caravel_0001001f_fill_pattern_4_5: 230000 rects
+caravel_0001001f_fill_pattern_4_5: 240000 rects
+caravel_0001001f_fill_pattern_4_5: 250000 rects
+caravel_0001001f_fill_pattern_4_5: 260000 rects
+caravel_0001001f_fill_pattern_4_5: 270000 rects
+caravel_0001001f_fill_pattern_4_5: 280000 rects
+caravel_0001001f_fill_pattern_4_5: 290000 rects
+caravel_0001001f_fill_pattern_4_5: 300000 rects
+caravel_0001001f_fill_pattern_4_5: 310000 rects
+caravel_0001001f_fill_pattern_4_5: 320000 rects
+caravel_0001001f_fill_pattern_4_5: 330000 rects
+caravel_0001001f_fill_pattern_4_5: 340000 rects
+caravel_0001001f_fill_pattern_4_5: 350000 rects
+caravel_0001001f_fill_pattern_4_5: 360000 rects
+caravel_0001001f_fill_pattern_4_5: 370000 rects
+caravel_0001001f_fill_pattern_4_5: 380000 rects
+caravel_0001001f_fill_pattern_4_5: 390000 rects
+caravel_0001001f_fill_pattern_4_5: 400000 rects
+caravel_0001001f_fill_pattern_4_5: 410000 rects
+caravel_0001001f_fill_pattern_4_5: 420000 rects
+caravel_0001001f_fill_pattern_4_5: 430000 rects
+caravel_0001001f_fill_pattern_4_5: 440000 rects
+caravel_0001001f_fill_pattern_4_5: 450000 rects
+caravel_0001001f_fill_pattern_4_5: 460000 rects
+caravel_0001001f_fill_pattern_4_5: 470000 rects
+caravel_0001001f_fill_pattern_4_5: 480000 rects
+caravel_0001001f_fill_pattern_4_5: 490000 rects
+caravel_0001001f_fill_pattern_4_5: 500000 rects
+caravel_0001001f_fill_pattern_4_5: 510000 rects
+caravel_0001001f_fill_pattern_4_5: 520000 rects
+caravel_0001001f_fill_pattern_4_5: 530000 rects
+caravel_0001001f_fill_pattern_4_5: 540000 rects
+caravel_0001001f_fill_pattern_4_5: 550000 rects
+caravel_0001001f_fill_pattern_4_5: 560000 rects
+caravel_0001001f_fill_pattern_4_5: 570000 rects
+caravel_0001001f_fill_pattern_4_5: 580000 rects
+caravel_0001001f_fill_pattern_4_5: 590000 rects
+caravel_0001001f_fill_pattern_4_5: 600000 rects
+caravel_0001001f_fill_pattern_4_5: 610000 rects
+caravel_0001001f_fill_pattern_4_5: 620000 rects
+caravel_0001001f_fill_pattern_4_5: 630000 rects
+caravel_0001001f_fill_pattern_4_5: 640000 rects
+caravel_0001001f_fill_pattern_4_5: 650000 rects
+caravel_0001001f_fill_pattern_4_5: 660000 rects
+caravel_0001001f_fill_pattern_4_5: 670000 rects
+caravel_0001001f_fill_pattern_4_5: 680000 rects
+caravel_00010
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_2_1.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_2_1: 10000 rects
+caravel_0001001f_fill_pattern_2_1: 20000 rects
+caravel_0001001f_fill_pattern_2_1: 30000 rects
+caravel_0001001f_fill_pattern_2_1: 40000 rects
+caravel_0001001f_fill_pattern_2_1: 50000 rects
+caravel_0001001f_fill_pattern_2_1: 60000 rects
+caravel_0001001f_fill_pattern_2_1: 70000 rects
+caravel_0001001f_fill_pattern_2_1: 80000 rects
+caravel_0001001f_fill_pattern_2_1: 90000 rects
+caravel_0001001f_fill_pattern_2_1: 100000 rects
+caravel_0001001f_fill_pattern_2_1: 110000 rects
+caravel_0001001f_fill_pattern_2_1: 120000 rects
+caravel_0001001f_fill_pattern_2_1: 130000 rects
+caravel_0001001f_fill_pattern_2_1: 140000 rects
+caravel_0001001f_fill_pattern_2_1: 150000 rects
+caravel_0001001f_fill_pattern_2_1: 160000 rects
+caravel_0001001f_fill_pattern_2_1: 170000 rects
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+caravel_0001001f_fill_pattern_2_1: 190000 rects
+caravel_0001001f_fill_pattern_2_1: 200000 rects
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+caravel_0001001f_fill_pattern_2_1: 220000 rects
+caravel_0001001f_fill_pattern_2_1: 230000 rects
+caravel_0001001f_fill_pattern_2_1: 240000 rects
+caravel_0001001f_fill_pattern_2_1: 250000 rects
+caravel_0001001f_fill_pattern_2_1: 260000 rects
+caravel_0001001f_fill_pattern_2_1: 270000 rects
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+caravel_0001001f_fill_pattern_2_1: 290000 rects
+caravel_0001001f_fill_pattern_2_1: 300000 rects
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+caravel_0001001f_fill_pattern_2_1: 330000 rects
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+caravel_0001001f_fill_pattern_2_1: 360000 rects
+caravel_0001001f_fill_pattern_2_1: 370000 rects
+caravel_0001001f_fill_pattern_2_1: 380000 rects
+caravel_0001001f_fill_pattern_2_1: 390000 rects
+caravel_0001001f_fill_pattern_2_1: 400000 rects
+caravel_0001001f_fill_pattern_2_1: 410000 rects
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+caravel_0001001f_fill_pattern_2_1: 430000 rects
+caravel_0001001f_fill_pattern_2_1: 440000 rects
+caravel_0001001f_fill_pattern_2_1: 450000 rects
+caravel_0001001f_fill_pattern_2_1: 460000 rects
+caravel_0001001f_fill_pattern_2_1: 470000 rects
+caravel_0001001f_fill_pattern_2_1: 480000 rects
+caravel_0001001f_fill_pattern_2_1: 490000 rects
+caravel_0001001f_fill_pattern_2_1: 500000 rects
+caravel_0001001f_fill_pattern_2_1: 510000 rects
+caravel_0001001f_fill_pattern_2_1: 520000 rects
+caravel_0001001f_fill_pattern_2_1: 530000 rects
+caravel_0001001f_fill_pattern_2_1: 540000 rects
+caravel_0001001f_fill_pattern_2_1: 550000 rects
+caravel_0001001f_fill_pattern_2_1: 560000 rects
+caravel_0001001f_fill_pattern_2_1: 570000 rects
+caravel_0001001f_fill_pattern_2_1: 580000 rects
+caravel_0001001f_fill_pattern_2_1: 590000 rects
+caravel_0001001f_fill_pattern_2_1: 600000 rects
+caravel_0001001f_fill_pattern_2_1: 610000 rects
+caravel_0001001f_fill_pattern_2_1: 620000 rects
+caravel_0001001f_fill_pattern_2_1: 630000 rects
+caravel_0001001f_fill_pattern_2_1: 640000 rects
+caravel_0001001f_fill_pattern_2_1: 650000 rects
+caravel_0001001f_fill_pattern_2_1: 660000 rects
+caravel_0001001f_fill_pattern_2_1: 670000 rects
+caravel_0001001f_fill_pattern_2_1: 680000 rects
+caravel_00010
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "caravel_0001001f_fill_pattern_5_6.magx" from command line.
+Creating new cell
+Loading "/mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC/mag/generate_fill_dist.tcl" from command line.
+caravel_0001001f_fill_pattern_5_6: 10000 rects
+caravel_0001001f_fill_pattern_5_6: 20000 rects
+caravel_0001001f_fill_pattern_5_6: 30000 rects
+caravel_0001001f_fill_pattern_5_6: 40000 rects
+caravel_0001001f_fill_pattern_5_6: 50000 rects
+caravel_0001001f_fill_pattern_5_6: 60000 rects
+caravel_0001001f_fill_pattern_5_6: 70000 rects
+caravel_0001001f_fill_pattern_5_6: 80000 rects
+caravel_0001001f_fill_pattern_5_6: 90000 rects
+caravel_0001001f_fill_pattern_5_6: 100000 rects
+caravel_0001001f_fill_pattern_5_6: 110000 rects
+caravel_0001001f_fill_pattern_5_6: 120000 rects
+caravel_0001001f_fill_pattern_5_6: 130000 rects
+caravel_0001001f_fill_pattern_5_6: 140000 rects
+caravel_0001001f_fill_pattern_5_6: 150000 rects
+caravel_0001001f_fill_pattern_5_6: 160000 rects
+caravel_0001001f_fill_pattern_5_6: 170000 rects
+caravel_0001001f_fill_pattern_5_6: 180000 rects
+caravel_0001001f_fill_pattern_5_6: 190000 rects
+caravel_0001001f_fill_pattern_5_6: 200000 rects
+caravel_0001001f_fill_pattern_5_6: 210000 rects
+caravel_0001001f_fill_pattern_5_6: 220000 rects
+caravel_0001001f_fill_pattern_5_6: 230000 rects
+caravel_0001001f_fill_pattern_5_6: 240000 rects
+caravel_0001001f_fill_pattern_5_6: 250000 rects
+caravel_0001001f_fill_pattern_5_6: 260000 rects
+caravel_0001001f_fill_pattern_5_6: 270000 rects
+caravel_0001001f_fill_pattern_5_6: 280000 rects
+caravel_0001001f_fill_pattern_5_6: 290000 rects
+caravel_0001001f_fill_pattern_5_6: 300000 rects
+caravel_0001001f_fill_pattern_5_6: 310000 rects
+caravel_0001001f_fill_pattern_5_6: 320000 rects
+caravel_0001001f_fill_pattern_5_6: 330000 rects
+caravel_0001001f_fill_pattern_5_6: 340000 rects
+caravel_0001001f_fill_pattern_5_6: 350000 rects
+caravel_0001001f_fill_pattern_5_6: 360000 rects
+caravel_0001001f_fill_pattern_5_6: 370000 rects
+caravel_0001001f_fill_pattern_5_6: 380000 rects
+caravel_0001001f_fill_pattern_5_6: 390000 rects
+caravel_0001001f_fill_pattern_5_6: 400000 rects
+caravel_0001001f_fill_pattern_5_6: 410000 rects
+caravel_0001001f_fill_pattern_5_6: 420000 rects
+caravel_0001001f_fill_pattern_5_6: 430000 rects
+caravel_0001001f_fill_pattern_5_6: 440000 rects
+caravel_0001001f_fill_pattern_5_6: 450000 rects
+caravel_0001001f_fill_pattern_5_6: 460000 rects
+caravel_0001001f_fill_pattern_5_6: 470000 rects
+caravel_0001001f_fill_pattern_5_6: 480000 rects
+caravel_0001001f_fill_pattern_5_6: 490000 rects
+caravel_0001001f_fill_pattern_5_6: 500000 rects
+caravel_0001001f_fill_pattern_5_6: 510000 rects
+caravel_0001001f_fill_pattern_5_6: 520000 rects
+caravel_0001001f_fill_pattern_5_6: 530000 rects
+caravel_0001001f_fill_pattern_5_6: 540000 rects
+caravel_0001001f_fill_pattern_5_6: 550000 rects
+caravel_0001001f_fill_pattern_5_6: 560000 rects
+caravel_0001001f_fill_pattern_5_6: 570000 rects
+caravel_0001001f_fill_pattern_5_6: 580000 rects
+caravel_0001001f_fill_pattern_5_6: 590000 rects
+caravel_0001001f_fill_pattern_5_6: 600000 rects
+caravel_0001001f_fill_pattern_5_6: 610000 rects
+caravel_0001001f_fill_pattern_5_6: 620000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_0001001f_fill_pattern_5_6
+Error message output from magic:
+File caravel_0001001f_fill_pattern_5_6.magx.mag couldn't be read
+No such file or directory
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+S
\ No newline at end of file
diff --git a/signoff/make_final b/signoff/make_final
new file mode 100644
index 0000000..e75570e
--- /dev/null
+++ b/signoff/make_final
@@ -0,0 +1 @@
+700a0479a393f2e21210764f6b625deb6f62fb90 ./gds/caravel_0001001f.gds
diff --git a/signoff/make_ship b/signoff/make_ship
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/signoff/make_ship
diff --git a/signoff/make_ship.out b/signoff/make_ship.out
new file mode 100644
index 0000000..1b38212
--- /dev/null
+++ b/signoff/make_ship.out
@@ -0,0 +1,8263 @@
+All files are uncompressed!
+mv: cannot move `./doc/' to `./docs/doc': Not a directory
+DONE
+Setting project user ID to: 0001001f
+Step 1: Modify GDS of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to verilog.
+Done!
+Step 3: Add user project ID text to top level layout.
+Done!
+user_id = 0001001f
+All files are uncompressed!
+###############################################
+Generating Caravel GDS (sources are in the 'gds' directory)
+
+Magic 8.3 revision 122 - Compiled on Mon Jan 25 17:32:18 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "mag2gds_caravel.tcl" from command line.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: LIB
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_ef_sc_hd__decap_12".
+Moving label "VGND" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Moving label "VNB" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Moving label "decap_12" from space to metal1 in cell sky130_ef_sc_hd__decap_12.
+Reading "DFFRAM_4K".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
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+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+Processing timestamp mismatches: user_project_wrapper.
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Warning: Parent cell lists instance of "alpha_F" at bad file path hexdigits/alpha_F.mag.
+The cell exists in the search paths at alpha_F.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_F geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_1" at bad file path hexdigits/alpha_1.mag.
+The cell exists in the search paths at alpha_1.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_1 geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_0" at bad file path hexdigits/alpha_0.mag.
+The cell exists in the search paths at alpha_0.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_0 geometry by factor of 72
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_6D geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+chip_io: 10000 rects
+Processing timestamp mismatches: gpio_control_block, open_source, copyright_block, alpha_1, alpha_F, user_id_textblock.
+ Generating output for cell caravel
+ Generating output for cell user_id_textblock
+ Generating output for cell alpha_F
+ Generating output for cell alpha_1
+ Generating output for cell alpha_0
+ Generating output for cell copyright_block
+ Generating output for cell font_73
+ Generating output for cell font_6C
+ Generating output for cell font_65
+ Generating output for cell font_61
+ Generating output for cell font_62
+ Generating output for cell font_66
+ Generating output for cell font_20
+ Generating output for cell font_29
+ Generating output for cell font_28
+ Generating output for cell font_43
+ Generating output for cell font_76
+ Generating output for cell font_72
+ Generating output for cell font_2D
+ Generating output for cell font_4B
+ Generating output for cell font_44
+ Generating output for cell font_50
+ Generating output for cell font_6E
+ Generating output for cell font_70
+ Generating output for cell font_6F
+ Generating output for cell font_74
+ Generating output for cell font_57
+ Generating output for cell font_6B
+ Generating output for cell font_79
+ Generating output for cell font_53
+ Generating output for cell font_67
+ Generating output for cell font_47
+ Generating output for cell font_30
+ Generating output for cell font_32
+ Generating output for cell font_6D
+ Generating output for cell font_63
+ Generating output for cell open_source
+ Generating output for cell storage
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "pk_contact_17".
+Reading "pk_contact_11".
+Reading "pk_contact_13".
+Reading "pk_contact_18".
+Reading "pk_nmos_m1_w0_360_sli_dli_da_p".
+Reading "pk_pmos_m1_w1_120_sli_dli_da_p".
+Reading "pk_nmos_m2_w0_740_sli_dli_da_p".
+Reading "pk_contact_24".
+Reading "pk_contact_23".
+Reading "pk_pmos_m2_w1_120_sli_dli_da_p".
+Reading "pk_contact_7".
+Reading "pk_contact_12".
+Reading "pk_nmos_m10_w7_000_sli_dli_da_p".
+Reading "pk_nmos_m1_w0_740_sactive_dli".
+Reading "pk_pmos_m1_w1_120_sli_dli".
+Reading "pk_pinv".
+Reading "pk_pmos_m10_w7_000_sli_dli_da_p".
+Reading "pk_nmos_m1_w0_740_sli_dactive".
+Reading "pk_nand2_dec".
+Reading "pk_pinv_dec".
+Reading "pk_nand3_dec".
+Reading "pk_nmos_m7_w1_680_sli_dli_da_p".
+Reading "pk_pmos_m7_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m22_w2_000_sli_dli_da_p".
+Reading "pk_pmos_m22_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m18_w2_000_sli_dli_da_p".
+Reading "pk_pmos_m18_w2_000_sli_dli_da_p".
+Reading "pk_contact_16".
+Reading "pk_contact_15".
+Reading "pk_pmos_m1_w0_550_sli_dli".
+Reading "pk_contact_14".
+Reading "pk_and2_dec".
+Reading "pk_contact_29".
+Reading "pk_contact_28".
+Reading "pk_contact_26".
+Reading "pk_nmos_m1_w2_880_sli_dli".
+Reading "pk_pdriver".
+Reading "pk_pnand2".
+Reading "pk_nmos_m3_w1_680_sli_dli_da_p".
+Reading "pk_contact_9".
+Reading "pk_pinv_dec_0".
+Reading "pk_contact_8".
+Reading "pk_and3_dec".
+Reading "pk_pmos_m3_w1_650_sli_dli_da_p".
+Reading "pk_contact_27".
+Reading "pk_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "pk_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "pk_sky130_fd_bd_sram__openram_dp_cell".
+Reading "pk_pmos_m2_w1_650_sli_dli_da_p".
+Reading "pk_pinv_16".
+Reading "pk_nmos_m2_w1_260_sli_dli_da_p".
+Reading "pk_nmos_m40_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m5_w1_680_sli_dli_da_p".
+Reading "pk_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "pk_nmos_m24_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m4_w1_260_sli_dli_da_p".
+Reading "pk_pmos_m4_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m3_w2_000_sli_dli_da_p".
+Reading "pk_pinv_17".
+Reading "pk_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "pk_write_driver".
+Reading "pk_hierarchical_predecode3x8".
+Reading "pk_hierarchical_predecode2x4".
+Reading "pk_precharge_1".
+Reading "pk_pmos_m5_w2_000_sli_dli_da_p".
+Reading "pk_contact_22".
+Reading "pk_contact_21".
+Reading "pk_contact_20".
+Reading "pk_contact_19".
+Reading "pk_single_level_column_mux".
+Reading "pk_dff".
+Reading "pk_nmos_m1_w0_740_sactive_dactive".
+Reading "pk_pinv_1".
+Reading "pk_sense_amp".
+Reading "pk_single_level_column_mux_0".
+Reading "pk_pmos_m3_w2_000_sli_dli_da_p".
+Reading "pk_pand2".
+Reading "pk_pmos_m40_w2_000_sli_dli_da_p".
+Reading "pk_pmos_m24_w2_000_sli_dli_da_p".
+Reading "pk_pinv_2".
+Reading "pk_precharge_0".
+Reading "pk_nmos_m8_w1_680_sli_dli_da_p".
+Reading "pk_wordline_driver".
+Reading "pk_pinv_3".
+Reading "pk_pmos_m13_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m13_w2_000_sli_dli_da_p".
+Reading "pk_pmos_m8_w2_000_sli_dli_da_p".
+Reading "pk_nmos_m12_w2_000_sli_dli_da_p".
+Reading "pk_pmos_m12_w2_000_sli_dli_da_p".
+Reading "pk_pinv_15".
+Reading "pk_row_cap_array".
+Reading "pk_col_cap_array".
+Reading "pk_dummy_array".
+Reading "pk_row_cap_array_0".
+Reading "pk_pdriver_3".
+Reading "pk_replica_column".
+Reading "pk_dff_buf_0".
+Reading "pk_pinv_13".
+Reading "pk_wordline_driver_array".
+Reading "pk_pinv_11".
+Reading "pk_pinv_9".
+Reading "pk_pinv_8".
+Reading "pk_pinv_7".
+Reading "pk_pinv_14".
+Reading "pk_replica_column_0".
+Reading "pk_pdriver_4".
+Reading "pk_pnand3".
+Reading "pk_pinv_18".
+Reading "pk_pinv_12".
+Reading "pk_pinv_6".
+Reading "pk_pnand2_0".
+Reading "pk_hierarchical_decoder".
+Reading "pk_pinv_0".
+Reading "pk_single_level_column_mux_array_0".
+Reading "pk_precharge_array_0".
+Reading "pk_pinv_20".
+Reading "pk_pdriver_0".
+Reading "pk_single_level_column_mux_array".
+Reading "pk_write_mask_and_array".
+Reading "pk_write_driver_array".
+Reading "pk_sense_amp_array".
+Reading "pk_precharge_array".
+Reading "pk_pinv_10".
+Reading "pk_pinv_19".
+Reading "pk_bitcell_array".
+Reading "pk_dff_buf_array".
+Reading "pk_pand3".
+Reading "pk_pdriver_1".
+Reading "pk_port_address".
+Reading "pk_replica_bitcell_array".
+Reading "pk_cr_0".
+Reading "pk_contact_32".
+Reading "pk_pdriver_5".
+Reading "pk_pnand2_1".
+Reading "pk_delay_chain".
+Reading "pk_pand3_0".
+Reading "pk_pdriver_2".
+Reading "pk_pand2_0".
+Reading "pk_pinvbuf".
+Reading "pk_port_data_0".
+Reading "pk_contact_33".
+Reading "pk_cr_1".
+Reading "pk_port_data".
+Reading "pk_cr_3".
+Reading "pk_data_dff".
+Reading "pk_wmask_dff".
+Reading "pk_row_addr_dff".
+Reading "pk_control_logic_rw".
+Reading "pk_bank".
+Reading "pk_control_logic_r".
+Reading "pk_col_addr_dff".
+Reading "pk_cr_2".
+Reading "pk_contact_34".
+Reading "pk_pk_sram_1rw1r_32_256_8_sky130".
+Reading "sram_1rw1r_32_256_8_sky130".
+Reading "storage".
+ Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped".
+ Generating output for cell gpio_control_block
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "gpio_control_block".
+ Generating output for cell user_id_programming
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "user_id_programming".
+ Generating output for cell simple_por
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "simple_por".
+ Generating output for cell mgmt_core
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__ebufn_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "DFFRAM".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "digital_pll".
+Reading "mgmt_core".
+ Generating output for cell mgmt_protect
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "mgmt_protect_hv".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "mprj_logic_high".
+Reading "mgmt_protect".
+ Generating output for cell chip_io
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_ef_io__lvc_vccd_overlay".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_ef_io__disconnect_vccd_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped2_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped2_pad".
+Reading "chip_io".
+ Generating output for cell user_project_wrapper
+ Generating output for cell sky130_ef_sc_hd__decap_12
+ Generating output for cell sky130_fd_sc_hd__fill_1
+ Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+ Generating output for cell sky130_fd_sc_hd__decap_3
+ Generating output for cell sky130_fd_sc_hd__fill_4
+ Generating output for cell sky130_fd_sc_hd__fill_8
+ Generating output for cell sky130_fd_sc_hd__conb_1
+ Generating output for cell sky130_fd_sc_hd__fill_2
+ Generating output for cell sky130_fd_sc_hd__decap_6
+ Generating output for cell sky130_fd_sc_hd__buf_2
+ Generating output for cell sky130_fd_sc_hd__diode_2
+ Generating output for cell sky130_fd_sc_hd__mux4_1
+ Generating output for cell sky130_fd_sc_hd__nor3b_4
+ Generating output for cell sky130_fd_sc_hd__clkbuf_4
+ Generating output for cell sky130_fd_sc_hd__and3b_4
+ Generating output for cell DFFRAM_4K
+ Generating output for cell sky130_fd_sc_hd__ebufn_2
+ Generating output for cell sky130_fd_sc_hd__dfxtp_1
+ Generating output for cell sky130_fd_sc_hd__and2_1
+ Generating output for cell sky130_fd_sc_hd__inv_1
+ Generating output for cell sky130_fd_sc_hd__dlclkp_1
+ Generating output for cell sky130_fd_sc_hd__clkbuf_16
+ Generating output for cell sky130_fd_sc_hd__ebufn_4
+ Generating output for cell sky130_fd_sc_hd__and4b_2
+ Generating output for cell sky130_fd_sc_hd__and4bb_2
+ Generating output for cell sky130_fd_sc_hd__nor4b_2
+ Generating output for cell sky130_fd_sc_hd__and4_2
+ Generating output for cell sky130_fd_sc_hd__clkbuf_8
+ Generating output for cell sky130_fd_sc_hd__and3_4
+ Generating output for cell sky130_fd_sc_hd__and2_4
+ Generating output for cell sky130_fd_sc_hd__a21o_4
+ Generating output for cell sky130_fd_sc_hd__dfrtp_4
+ Generating output for cell sky130_fd_sc_hd__o21a_4
+ Generating output for cell sky130_fd_sc_hd__o22a_4
+ Generating output for cell sky130_fd_sc_hd__clkbuf_1
+ Generating output for cell sky130_fd_sc_hd__a32o_4
+ Generating output for cell sky130_fd_sc_hd__or3_4
+ Generating output for cell sky130_fd_sc_hd__or2_4
+ Generating output for cell sky130_fd_sc_hd__inv_2
+ Generating output for cell sky130_fd_sc_hd__nor2_4
+ Generating output for cell sky130_fd_sc_hd__or4_4
+ Generating output for cell sky130_fd_sc_hd__nor3_4
+ Generating output for cell sky130_fd_sc_hd__nand2_4
+ Generating output for cell sky130_fd_sc_hd__dfstp_4
+ Generating output for cell sky130_fd_sc_hd__a2bb2o_4
+ Generating output for cell sky130_fd_sc_hd__a211o_4
+ Generating output for cell sky130_fd_sc_hd__nor4_4
+ Generating output for cell sky130_fd_sc_hd__o41a_4
+ Generating output for cell sky130_fd_sc_hd__a41o_4
+ Generating output for cell sky130_fd_sc_hd__xnor2_4
+ Generating output for cell sky130_fd_sc_hd__dfxtp_4
+ Generating output for cell sky130_fd_sc_hd__nand3_4
+ Generating output for cell sky130_fd_sc_hd__and4_4
+ Generating output for cell sky130_fd_sc_hd__o32a_4
+ Generating output for cell sky130_fd_sc_hd__a21bo_4
+ Generating output for cell sky130_fd_sc_hd__a22oi_4
+ Generating output for cell sky130_fd_sc_hd__a21oi_4
+ Generating output for cell apb_sys_0
+ Generating output for cell sky130_fd_sc_hd__o21ai_4
+ Generating output for cell sky130_fd_sc_hd__a2111o_4
+ Generating output for cell sky130_fd_sc_hd__a21boi_4
+ Generating output for cell DMC_32x16HC
+ Generating output for cell sky130_fd_sc_hd__and4bb_4
+ Generating output for cell sky130_fd_sc_hd__clkbuf_2
+ Generating output for cell sky130_fd_sc_hd__and2b_2
+ Generating output for cell sky130_fd_sc_hd__nor2_2
+ Generating output for cell sky130_fd_sc_hd__and4b_4
+ Generating output for cell sky130_fd_sc_hd__nor4b_4
+ Generating output for cell sky130_fd_sc_hd__dfrtp_1
+ Generating output for cell sky130_fd_sc_hd__and2_2
+ Generating output for cell ibex_wrapper
+ Generating output for cell sky130_fd_sc_hd__xor2_4
+ Generating output for cell sky130_fd_sc_hd__a2bb2oi_4
+ Generating output for cell sky130_fd_sc_hd__o32ai_4
+ Generating output for cell sky130_fd_sc_hd__a32oi_4
+ Generating output for cell sky130_fd_sc_hd__nand4_4
+ Generating output for cell sky130_fd_sc_hd__a2111oi_4
+ Generating output for cell sky130_fd_sc_hd__buf_4
+ Generating output for cell sky130_fd_sc_hd__buf_8
+ Generating output for cell sky130_fd_sc_hd__a41oi_4
+mv ./mag/caravel.gds ./gds
+make_ship complete: /mnt/share/open_mpw/shuttle/slot-031/Caravel_Chameleon_SoC;
diff --git a/signoff/remove_fill_areaid.out b/signoff/remove_fill_areaid.out
new file mode 100644
index 0000000..eb8d93a
--- /dev/null
+++ b/signoff/remove_fill_areaid.out
@@ -0,0 +1,5 @@
+got: fin='./gds/caravel_0001001f_fill_pattern.gds' fout='./gds/caravel_0001001f_fill_pattern_new.gds' lnum='81' dnum='14'
+Reading file ./gds/caravel_0001001f_fill_pattern.gds
+deleting layer: 81/14
+Writing file ./gds/caravel_0001001f_fill_pattern_new.gds...
+Done.
diff --git a/signoff/versions b/signoff/versions
new file mode 100644
index 0000000..58030ba
--- /dev/null
+++ b/signoff/versions
@@ -0,0 +1,36 @@
+------------------------------------
+make_ship: Wed Feb 17 16:53:54 PST 2021
+make_ship: caravel = commit bfc5d458
+make_ship: magic = 8.3.122
+make_ship: sky130A tech = version 1.0.121-9-g12f58a2
+make_ship: open_pdks = 1.0.122
+------------------------------------
+generate_fill: Wed Feb 17 17:55:20 PST 2021
+generate_fill: caravel = commit bfc5d458
+generate_fill: magic = 8.3.122
+generate_fill: sky130A tech = version 1.0.121-9-g12f58a2
+generate_fill: open_pdks = 1.0.122
+------------------------------------
+generate_fill: Wed Feb 17 18:39:58 PST 2021
+generate_fill: caravel = commit bfc5d458
+generate_fill: magic = 8.3.122
+generate_fill: sky130A tech = version 1.0.121-9-g12f58a2
+generate_fill: open_pdks = 1.0.122
+------------------------------------
+make_final: Wed Feb 17 19:36:43 PST 2021
+make_final: caravel = commit bfc5d458
+make_final: magic = 8.3.122
+make_final: sky130A tech = version 1.0.121-9-g12f58a2
+make_final: open_pdks = 1.0.122
+------------------------------------
+make_final: Wed Feb 17 20:25:52 PST 2021
+make_final: caravel = commit bfc5d458
+make_final: magic = 8.3.122
+make_final: sky130A tech = version 1.0.121-9-g12f58a2
+make_final: open_pdks = 1.0.122
+------------------------------------
+make_final: Thu Feb 18 16:19:09 PST 2021
+make_final: caravel = commit bfc5d458
+make_final: magic = 8.3.122
+make_final: sky130A tech = version 1.0.121-9-g12f58a2
+make_final: open_pdks = 1.0.122
diff --git a/signoff/waivers b/signoff/waivers
new file mode 100644
index 0000000..a0754b4
--- /dev/null
+++ b/signoff/waivers
@@ -0,0 +1,83 @@
+k_107_phighvt_L_0_15
+k_109_phighvt_L_0_25
+k_116_phighvt_valid
+k_132_nhvnative_L_0_90
+k_138_nhvnative_valid
+k_14_phvesd_L_0_55
+k_15_phvesd_valid
+k_157_npd_L_0_15
+k_158_npd_valid
+k_207_nlowvt_L_0_15
+k_216_nlowvt_valid
+k_238_nhv_L_0_50
+k_239_nhv_L_0_60
+k_240_nhv_L_0_80
+k_241_nhv_L_1_00
+k_243_nhv_L_4_00
+k_244_nhv_L_8_00
+k_246_nhv_valid
+k_274_nshort_L_0_15
+k_275_nshort_L_0_18
+k_276_nshort_L_0_25
+k_280_nshort_L_4_00
+k_281_nshort_L_8_00
+k_283_nshort_valid
+k_329_nhvesd_L_0_60
+k_331_nhvesd_valid
+k_40_phv_L_0_50
+k_41_phv_L_0_60
+k_42_phv_L_0_80
+k_43_phv_L_1_00
+k_44_phv_L_2_00
+k_45_phv_L_4_00
+k_46_phv_L_8_00
+k_48_phv_valid
+k_79_pshort_L_0_15
+k_81_pshort_L_0_18
+k_82_pshort_L_0_25
+k_89_pshort_valid
+k_90_ppu_L_0_15
+k_91_ppu_valid
+r_1189_X.22
+r_1193_X.22
+r_1197_X.22
+r_1201_X.22
+r_1205_X.22
+r_1252_metblk.6
+r_1333_pad.15
+s_0_X.18
+s_1_X.18
+s_2_X.18
+s_26_X.22
+s_3_X.18
+s_31_X.22
+s_36_X.22
+s_4_X.18
+s_41_X.22
+s_6_X.27
+s_68_metblk.6
+v_0_q0_mcon_NOTAreaidStdCellCore_added_vias
+v_1_q0_mcon_NOTAreaidStdCellCore_added_below
+v_10_q0_via3_NOTAreaidStdCellCore_added_below
+v_11_q0_via3_NOTAreaidStdCellCore_added_above
+v_12_q0_via4_NOTAreaidStdCellCore_added_vias
+v_13_q0_via4_NOTAreaidStdCellCore_added_below
+v_14_q0_via4_NOTAreaidStdCellCore_added_above
+v_2_q0_mcon_NOTAreaidStdCellCore_added_above
+v_3_q0_via_NOTAreaidStdCellCore_added_vias
+v_4_q0_via_NOTAreaidStdCellCore_added_below
+v_5_q0_via_NOTAreaidStdCellCore_added_above
+v_6_q0_via2_NOTAreaidStdCellCore_added_vias
+v_7_q0_via2_NOTAreaidStdCellCore_added_below
+v_8_q0_via2_NOTAreaidStdCellCore_added_above
+v_9_q0_via3_NOTAreaidStdCellCore_added_vias
+r_923_pwde.5
+r_1132_areaid.1
+r_1312_pad.1
+r_1321_pad.6
+r_1323_pad.6
+r_557_Poly.X.1
+r_575_Poly.X.1
+r_613_Poly.X.1
+r_623_Poly.X.1
+
diff --git a/spi/lvs/caravel.spice b/spi/lvs/caravel.spice
new file mode 100644
index 0000000..c77ab62
--- /dev/null
+++ b/spi/lvs/caravel.spice
@@ -0,0 +1,1731 @@
+* NGSPICE file created from caravel.ext - technology: sky130A
+
+* Black-box entry subcircuit for gpio_control_block abstract view
+.subckt gpio_control_block mgmt_gpio_in mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en
++ pad_gpio_ana_pol pad_gpio_ana_sel pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover
++ pad_gpio_ib_mode_sel pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel
++ pad_gpio_vtrip_sel resetn serial_clock serial_data_in serial_data_out user_gpio_in
++ user_gpio_oeb user_gpio_out zero vccd vssd vccd1 vssd1
+.ends
+
+* Black-box entry subcircuit for chip_io abstract view
+.subckt chip_io clock clock_core por flash_clk flash_clk_core flash_clk_ieb_core flash_clk_oeb_core
++ flash_csb flash_csb_core flash_csb_ieb_core flash_csb_oeb_core flash_io0 flash_io0_di_core
++ flash_io0_do_core flash_io0_ieb_core flash_io0_oeb_core flash_io1 flash_io1_di_core
++ flash_io1_do_core flash_io1_ieb_core flash_io1_oeb_core gpio gpio_in_core gpio_inenb_core
++ gpio_mode0_core gpio_mode1_core gpio_out_core gpio_outenb_core vccd vdda vddio vssa
++ vssd vssio mprj_io[0] mprj_io_analog_en[0] mprj_io_analog_pol[0] mprj_io_analog_sel[0]
++ mprj_io_dm[0] mprj_io_dm[1] mprj_io_dm[2] mprj_io_enh[0] mprj_io_hldh_n[0] mprj_io_holdover[0]
++ mprj_io_ib_mode_sel[0] mprj_io_inp_dis[0] mprj_io_oeb[0] mprj_io_out[0] mprj_io_slow_sel[0]
++ mprj_io_vtrip_sel[0] mprj_io_in[0] mprj_analog_io[3] mprj_io[10] mprj_io_analog_en[10]
++ mprj_io_analog_pol[10] mprj_io_analog_sel[10] mprj_io_dm[30] mprj_io_dm[31] mprj_io_dm[32]
++ mprj_io_enh[10] mprj_io_hldh_n[10] mprj_io_holdover[10] mprj_io_ib_mode_sel[10]
++ mprj_io_inp_dis[10] mprj_io_oeb[10] mprj_io_out[10] mprj_io_slow_sel[10] mprj_io_vtrip_sel[10]
++ mprj_io_in[10] mprj_analog_io[4] mprj_io[11] mprj_io_analog_en[11] mprj_io_analog_pol[11]
++ mprj_io_analog_sel[11] mprj_io_dm[33] mprj_io_dm[34] mprj_io_dm[35] mprj_io_enh[11]
++ mprj_io_hldh_n[11] mprj_io_holdover[11] mprj_io_ib_mode_sel[11] mprj_io_inp_dis[11]
++ mprj_io_oeb[11] mprj_io_out[11] mprj_io_slow_sel[11] mprj_io_vtrip_sel[11] mprj_io_in[11]
++ mprj_analog_io[5] mprj_io[12] mprj_io_analog_en[12] mprj_io_analog_pol[12] mprj_io_analog_sel[12]
++ mprj_io_dm[36] mprj_io_dm[37] mprj_io_dm[38] mprj_io_enh[12] mprj_io_hldh_n[12]
++ mprj_io_holdover[12] mprj_io_ib_mode_sel[12] mprj_io_inp_dis[12] mprj_io_oeb[12]
++ mprj_io_out[12] mprj_io_slow_sel[12] mprj_io_vtrip_sel[12] mprj_io_in[12] mprj_analog_io[6]
++ mprj_io[13] mprj_io_analog_en[13] mprj_io_analog_pol[13] mprj_io_analog_sel[13]
++ mprj_io_dm[39] mprj_io_dm[40] mprj_io_dm[41] mprj_io_enh[13] mprj_io_hldh_n[13]
++ mprj_io_holdover[13] mprj_io_ib_mode_sel[13] mprj_io_inp_dis[13] mprj_io_oeb[13]
++ mprj_io_out[13] mprj_io_slow_sel[13] mprj_io_vtrip_sel[13] mprj_io_in[13] mprj_analog_io[7]
++ mprj_io[14] mprj_io_analog_en[14] mprj_io_analog_pol[14] mprj_io_analog_sel[14]
++ mprj_io_dm[42] mprj_io_dm[43] mprj_io_dm[44] mprj_io_enh[14] mprj_io_hldh_n[14]
++ mprj_io_holdover[14] mprj_io_ib_mode_sel[14] mprj_io_inp_dis[14] mprj_io_oeb[14]
++ mprj_io_out[14] mprj_io_slow_sel[14] mprj_io_vtrip_sel[14] mprj_io_in[14] mprj_analog_io[8]
++ mprj_io[15] mprj_io_analog_en[15] mprj_io_analog_pol[15] mprj_io_analog_sel[15]
++ mprj_io_dm[45] mprj_io_dm[46] mprj_io_dm[47] mprj_io_enh[15] mprj_io_hldh_n[15]
++ mprj_io_holdover[15] mprj_io_ib_mode_sel[15] mprj_io_inp_dis[15] mprj_io_oeb[15]
++ mprj_io_out[15] mprj_io_slow_sel[15] mprj_io_vtrip_sel[15] mprj_io_in[15] mprj_analog_io[9]
++ mprj_io[16] mprj_io_analog_en[16] mprj_io_analog_pol[16] mprj_io_analog_sel[16]
++ mprj_io_dm[48] mprj_io_dm[49] mprj_io_dm[50] mprj_io_enh[16] mprj_io_hldh_n[16]
++ mprj_io_holdover[16] mprj_io_ib_mode_sel[16] mprj_io_inp_dis[16] mprj_io_oeb[16]
++ mprj_io_out[16] mprj_io_slow_sel[16] mprj_io_vtrip_sel[16] mprj_io_in[16] mprj_analog_io[10]
++ mprj_io[17] mprj_io_analog_en[17] mprj_io_analog_pol[17] mprj_io_analog_sel[17]
++ mprj_io_dm[51] mprj_io_dm[52] mprj_io_dm[53] mprj_io_enh[17] mprj_io_hldh_n[17]
++ mprj_io_holdover[17] mprj_io_ib_mode_sel[17] mprj_io_inp_dis[17] mprj_io_oeb[17]
++ mprj_io_out[17] mprj_io_slow_sel[17] mprj_io_vtrip_sel[17] mprj_io_in[17] mprj_io[1]
++ mprj_io_analog_en[1] mprj_io_analog_pol[1] mprj_io_analog_sel[1] mprj_io_dm[3] mprj_io_dm[4]
++ mprj_io_dm[5] mprj_io_enh[1] mprj_io_hldh_n[1] mprj_io_holdover[1] mprj_io_ib_mode_sel[1]
++ mprj_io_inp_dis[1] mprj_io_oeb[1] mprj_io_out[1] mprj_io_slow_sel[1] mprj_io_vtrip_sel[1]
++ mprj_io_in[1] mprj_io[2] mprj_io_analog_en[2] mprj_io_analog_pol[2] mprj_io_analog_sel[2]
++ mprj_io_dm[6] mprj_io_dm[7] mprj_io_dm[8] mprj_io_enh[2] mprj_io_hldh_n[2] mprj_io_holdover[2]
++ mprj_io_ib_mode_sel[2] mprj_io_inp_dis[2] mprj_io_oeb[2] mprj_io_out[2] mprj_io_slow_sel[2]
++ mprj_io_vtrip_sel[2] mprj_io_in[2] mprj_io[3] mprj_io_analog_en[3] mprj_io_analog_pol[3]
++ mprj_io_analog_sel[3] mprj_io_dm[10] mprj_io_dm[11] mprj_io_dm[9] mprj_io_enh[3]
++ mprj_io_hldh_n[3] mprj_io_holdover[3] mprj_io_ib_mode_sel[3] mprj_io_inp_dis[3]
++ mprj_io_oeb[3] mprj_io_out[3] mprj_io_slow_sel[3] mprj_io_vtrip_sel[3] mprj_io_in[3]
++ mprj_io[4] mprj_io_analog_en[4] mprj_io_analog_pol[4] mprj_io_analog_sel[4] mprj_io_dm[12]
++ mprj_io_dm[13] mprj_io_dm[14] mprj_io_enh[4] mprj_io_hldh_n[4] mprj_io_holdover[4]
++ mprj_io_ib_mode_sel[4] mprj_io_inp_dis[4] mprj_io_oeb[4] mprj_io_out[4] mprj_io_slow_sel[4]
++ mprj_io_vtrip_sel[4] mprj_io_in[4] mprj_io[5] mprj_io_analog_en[5] mprj_io_analog_pol[5]
++ mprj_io_analog_sel[5] mprj_io_dm[15] mprj_io_dm[16] mprj_io_dm[17] mprj_io_enh[5]
++ mprj_io_hldh_n[5] mprj_io_holdover[5] mprj_io_ib_mode_sel[5] mprj_io_inp_dis[5]
++ mprj_io_oeb[5] mprj_io_out[5] mprj_io_slow_sel[5] mprj_io_vtrip_sel[5] mprj_io_in[5]
++ mprj_io[6] mprj_io_analog_en[6] mprj_io_analog_pol[6] mprj_io_analog_sel[6] mprj_io_dm[18]
++ mprj_io_dm[19] mprj_io_dm[20] mprj_io_enh[6] mprj_io_hldh_n[6] mprj_io_holdover[6]
++ mprj_io_ib_mode_sel[6] mprj_io_inp_dis[6] mprj_io_oeb[6] mprj_io_out[6] mprj_io_slow_sel[6]
++ mprj_io_vtrip_sel[6] mprj_io_in[6] mprj_analog_io[0] mprj_io[7] mprj_io_analog_en[7]
++ mprj_io_analog_pol[7] mprj_io_analog_sel[7] mprj_io_dm[21] mprj_io_dm[22] mprj_io_dm[23]
++ mprj_io_enh[7] mprj_io_hldh_n[7] mprj_io_holdover[7] mprj_io_ib_mode_sel[7] mprj_io_inp_dis[7]
++ mprj_io_oeb[7] mprj_io_out[7] mprj_io_slow_sel[7] mprj_io_vtrip_sel[7] mprj_io_in[7]
++ mprj_analog_io[1] mprj_io[8] mprj_io_analog_en[8] mprj_io_analog_pol[8] mprj_io_analog_sel[8]
++ mprj_io_dm[24] mprj_io_dm[25] mprj_io_dm[26] mprj_io_enh[8] mprj_io_hldh_n[8] mprj_io_holdover[8]
++ mprj_io_ib_mode_sel[8] mprj_io_inp_dis[8] mprj_io_oeb[8] mprj_io_out[8] mprj_io_slow_sel[8]
++ mprj_io_vtrip_sel[8] mprj_io_in[8] mprj_analog_io[2] mprj_io[9] mprj_io_analog_en[9]
++ mprj_io_analog_pol[9] mprj_io_analog_sel[9] mprj_io_dm[27] mprj_io_dm[28] mprj_io_dm[29]
++ mprj_io_enh[9] mprj_io_hldh_n[9] mprj_io_holdover[9] mprj_io_ib_mode_sel[9] mprj_io_inp_dis[9]
++ mprj_io_oeb[9] mprj_io_out[9] mprj_io_slow_sel[9] mprj_io_vtrip_sel[9] mprj_io_in[9]
++ mprj_analog_io[11] mprj_io[18] mprj_io_analog_en[18] mprj_io_analog_pol[18] mprj_io_analog_sel[18]
++ mprj_io_dm[54] mprj_io_dm[55] mprj_io_dm[56] mprj_io_enh[18] mprj_io_hldh_n[18]
++ mprj_io_holdover[18] mprj_io_ib_mode_sel[18] mprj_io_inp_dis[18] mprj_io_oeb[18]
++ mprj_io_out[18] mprj_io_slow_sel[18] mprj_io_vtrip_sel[18] mprj_io_in[18] mprj_analog_io[21]
++ mprj_io[28] mprj_io_analog_en[28] mprj_io_analog_pol[28] mprj_io_analog_sel[28]
++ mprj_io_dm[84] mprj_io_dm[85] mprj_io_dm[86] mprj_io_enh[28] mprj_io_hldh_n[28]
++ mprj_io_holdover[28] mprj_io_ib_mode_sel[28] mprj_io_inp_dis[28] mprj_io_oeb[28]
++ mprj_io_out[28] mprj_io_slow_sel[28] mprj_io_vtrip_sel[28] mprj_io_in[28] mprj_analog_io[22]
++ mprj_io[29] mprj_io_analog_en[29] mprj_io_analog_pol[29] mprj_io_analog_sel[29]
++ mprj_io_dm[87] mprj_io_dm[88] mprj_io_dm[89] mprj_io_enh[29] mprj_io_hldh_n[29]
++ mprj_io_holdover[29] mprj_io_ib_mode_sel[29] mprj_io_inp_dis[29] mprj_io_oeb[29]
++ mprj_io_out[29] mprj_io_slow_sel[29] mprj_io_vtrip_sel[29] mprj_io_in[29] mprj_analog_io[23]
++ mprj_io[30] mprj_io_analog_en[30] mprj_io_analog_pol[30] mprj_io_analog_sel[30]
++ mprj_io_dm[90] mprj_io_dm[91] mprj_io_dm[92] mprj_io_enh[30] mprj_io_hldh_n[30]
++ mprj_io_holdover[30] mprj_io_ib_mode_sel[30] mprj_io_inp_dis[30] mprj_io_oeb[30]
++ mprj_io_out[30] mprj_io_slow_sel[30] mprj_io_vtrip_sel[30] mprj_io_in[30] mprj_analog_io[24]
++ mprj_io[31] mprj_io_analog_en[31] mprj_io_analog_pol[31] mprj_io_analog_sel[31]
++ mprj_io_dm[93] mprj_io_dm[94] mprj_io_dm[95] mprj_io_enh[31] mprj_io_hldh_n[31]
++ mprj_io_holdover[31] mprj_io_ib_mode_sel[31] mprj_io_inp_dis[31] mprj_io_oeb[31]
++ mprj_io_out[31] mprj_io_slow_sel[31] mprj_io_vtrip_sel[31] mprj_io_in[31] mprj_analog_io[25]
++ mprj_io[32] mprj_io_analog_en[32] mprj_io_analog_pol[32] mprj_io_analog_sel[32]
++ mprj_io_dm[96] mprj_io_dm[97] mprj_io_dm[98] mprj_io_enh[32] mprj_io_hldh_n[32]
++ mprj_io_holdover[32] mprj_io_ib_mode_sel[32] mprj_io_inp_dis[32] mprj_io_oeb[32]
++ mprj_io_out[32] mprj_io_slow_sel[32] mprj_io_vtrip_sel[32] mprj_io_in[32] mprj_analog_io[26]
++ mprj_io[33] mprj_io_analog_en[33] mprj_io_analog_pol[33] mprj_io_analog_sel[33]
++ mprj_io_dm[100] mprj_io_dm[101] mprj_io_dm[99] mprj_io_enh[33] mprj_io_hldh_n[33]
++ mprj_io_holdover[33] mprj_io_ib_mode_sel[33] mprj_io_inp_dis[33] mprj_io_oeb[33]
++ mprj_io_out[33] mprj_io_slow_sel[33] mprj_io_vtrip_sel[33] mprj_io_in[33] mprj_analog_io[27]
++ mprj_io[34] mprj_io_analog_en[34] mprj_io_analog_pol[34] mprj_io_analog_sel[34]
++ mprj_io_dm[102] mprj_io_dm[103] mprj_io_dm[104] mprj_io_enh[34] mprj_io_hldh_n[34]
++ mprj_io_holdover[34] mprj_io_ib_mode_sel[34] mprj_io_inp_dis[34] mprj_io_oeb[34]
++ mprj_io_out[34] mprj_io_slow_sel[34] mprj_io_vtrip_sel[34] mprj_io_in[34] mprj_analog_io[28]
++ mprj_io[35] mprj_io_analog_en[35] mprj_io_analog_pol[35] mprj_io_analog_sel[35]
++ mprj_io_dm[105] mprj_io_dm[106] mprj_io_dm[107] mprj_io_enh[35] mprj_io_hldh_n[35]
++ mprj_io_holdover[35] mprj_io_ib_mode_sel[35] mprj_io_inp_dis[35] mprj_io_oeb[35]
++ mprj_io_out[35] mprj_io_slow_sel[35] mprj_io_vtrip_sel[35] mprj_io_in[35] mprj_analog_io[29]
++ mprj_io[36] mprj_io_analog_en[36] mprj_io_analog_pol[36] mprj_io_analog_sel[36]
++ mprj_io_dm[108] mprj_io_dm[109] mprj_io_dm[110] mprj_io_enh[36] mprj_io_hldh_n[36]
++ mprj_io_holdover[36] mprj_io_ib_mode_sel[36] mprj_io_inp_dis[36] mprj_io_oeb[36]
++ mprj_io_out[36] mprj_io_slow_sel[36] mprj_io_vtrip_sel[36] mprj_io_in[36] mprj_analog_io[30]
++ mprj_io[37] mprj_io_analog_en[37] mprj_io_analog_pol[37] mprj_io_analog_sel[37]
++ mprj_io_dm[111] mprj_io_dm[112] mprj_io_dm[113] mprj_io_enh[37] mprj_io_hldh_n[37]
++ mprj_io_holdover[37] mprj_io_ib_mode_sel[37] mprj_io_inp_dis[37] mprj_io_oeb[37]
++ mprj_io_out[37] mprj_io_slow_sel[37] mprj_io_vtrip_sel[37] mprj_io_in[37] mprj_analog_io[12]
++ mprj_io[19] mprj_io_analog_en[19] mprj_io_analog_pol[19] mprj_io_analog_sel[19]
++ mprj_io_dm[57] mprj_io_dm[58] mprj_io_dm[59] mprj_io_enh[19] mprj_io_hldh_n[19]
++ mprj_io_holdover[19] mprj_io_ib_mode_sel[19] mprj_io_inp_dis[19] mprj_io_oeb[19]
++ mprj_io_out[19] mprj_io_slow_sel[19] mprj_io_vtrip_sel[19] mprj_io_in[19] mprj_analog_io[13]
++ mprj_io[20] mprj_io_analog_en[20] mprj_io_analog_pol[20] mprj_io_analog_sel[20]
++ mprj_io_dm[60] mprj_io_dm[61] mprj_io_dm[62] mprj_io_enh[20] mprj_io_hldh_n[20]
++ mprj_io_holdover[20] mprj_io_ib_mode_sel[20] mprj_io_inp_dis[20] mprj_io_oeb[20]
++ mprj_io_out[20] mprj_io_slow_sel[20] mprj_io_vtrip_sel[20] mprj_io_in[20] mprj_analog_io[14]
++ mprj_io[21] mprj_io_analog_en[21] mprj_io_analog_pol[21] mprj_io_analog_sel[21]
++ mprj_io_dm[63] mprj_io_dm[64] mprj_io_dm[65] mprj_io_enh[21] mprj_io_hldh_n[21]
++ mprj_io_holdover[21] mprj_io_ib_mode_sel[21] mprj_io_inp_dis[21] mprj_io_oeb[21]
++ mprj_io_out[21] mprj_io_slow_sel[21] mprj_io_vtrip_sel[21] mprj_io_in[21] mprj_analog_io[15]
++ mprj_io[22] mprj_io_analog_en[22] mprj_io_analog_pol[22] mprj_io_analog_sel[22]
++ mprj_io_dm[66] mprj_io_dm[67] mprj_io_dm[68] mprj_io_enh[22] mprj_io_hldh_n[22]
++ mprj_io_holdover[22] mprj_io_ib_mode_sel[22] mprj_io_inp_dis[22] mprj_io_oeb[22]
++ mprj_io_out[22] mprj_io_slow_sel[22] mprj_io_vtrip_sel[22] mprj_io_in[22] mprj_analog_io[16]
++ mprj_io[23] mprj_io_analog_en[23] mprj_io_analog_pol[23] mprj_io_analog_sel[23]
++ mprj_io_dm[69] mprj_io_dm[70] mprj_io_dm[71] mprj_io_enh[23] mprj_io_hldh_n[23]
++ mprj_io_holdover[23] mprj_io_ib_mode_sel[23] mprj_io_inp_dis[23] mprj_io_oeb[23]
++ mprj_io_out[23] mprj_io_slow_sel[23] mprj_io_vtrip_sel[23] mprj_io_in[23] mprj_analog_io[17]
++ mprj_io[24] mprj_io_analog_en[24] mprj_io_analog_pol[24] mprj_io_analog_sel[24]
++ mprj_io_dm[72] mprj_io_dm[73] mprj_io_dm[74] mprj_io_enh[24] mprj_io_hldh_n[24]
++ mprj_io_holdover[24] mprj_io_ib_mode_sel[24] mprj_io_inp_dis[24] mprj_io_oeb[24]
++ mprj_io_out[24] mprj_io_slow_sel[24] mprj_io_vtrip_sel[24] mprj_io_in[24] mprj_analog_io[18]
++ mprj_io[25] mprj_io_analog_en[25] mprj_io_analog_pol[25] mprj_io_analog_sel[25]
++ mprj_io_dm[75] mprj_io_dm[76] mprj_io_dm[77] mprj_io_enh[25] mprj_io_hldh_n[25]
++ mprj_io_holdover[25] mprj_io_ib_mode_sel[25] mprj_io_inp_dis[25] mprj_io_oeb[25]
++ mprj_io_out[25] mprj_io_slow_sel[25] mprj_io_vtrip_sel[25] mprj_io_in[25] mprj_analog_io[19]
++ mprj_io[26] mprj_io_analog_en[26] mprj_io_analog_pol[26] mprj_io_analog_sel[26]
++ mprj_io_dm[78] mprj_io_dm[79] mprj_io_dm[80] mprj_io_enh[26] mprj_io_hldh_n[26]
++ mprj_io_holdover[26] mprj_io_ib_mode_sel[26] mprj_io_inp_dis[26] mprj_io_oeb[26]
++ mprj_io_out[26] mprj_io_slow_sel[26] mprj_io_vtrip_sel[26] mprj_io_in[26] mprj_analog_io[20]
++ mprj_io[27] mprj_io_analog_en[27] mprj_io_analog_pol[27] mprj_io_analog_sel[27]
++ mprj_io_dm[81] mprj_io_dm[82] mprj_io_dm[83] mprj_io_enh[27] mprj_io_hldh_n[27]
++ mprj_io_holdover[27] mprj_io_ib_mode_sel[27] mprj_io_inp_dis[27] mprj_io_oeb[27]
++ mprj_io_out[27] mprj_io_slow_sel[27] mprj_io_vtrip_sel[27] mprj_io_in[27] porb_h
++ resetb resetb_core_h vccd1 vdda1 vssa1 vssd1 vccd2 vdda2 vssa2 vssd2
+.ends
+
+* Black-box entry subcircuit for mgmt_core abstract view
+.subckt mgmt_core clock core_clk core_rstn flash_clk flash_clk_ieb flash_clk_oeb flash_csb
++ flash_csb_ieb flash_csb_oeb flash_io0_di flash_io0_do flash_io0_ieb flash_io0_oeb
++ flash_io1_di flash_io1_do flash_io1_ieb flash_io1_oeb gpio_in_pad gpio_inenb_pad
++ gpio_mode0_pad gpio_mode1_pad gpio_out_pad gpio_outenb_pad jtag_out jtag_outenb
++ la_input[0] la_input[100] la_input[101] la_input[102] la_input[103] la_input[104]
++ la_input[105] la_input[106] la_input[107] la_input[108] la_input[109] la_input[10]
++ la_input[110] la_input[111] la_input[112] la_input[113] la_input[114] la_input[115]
++ la_input[116] la_input[117] la_input[118] la_input[119] la_input[11] la_input[120]
++ la_input[121] la_input[122] la_input[123] la_input[124] la_input[125] la_input[126]
++ la_input[127] la_input[12] la_input[13] la_input[14] la_input[15] la_input[16] la_input[17]
++ la_input[18] la_input[19] la_input[1] la_input[20] la_input[21] la_input[22] la_input[23]
++ la_input[24] la_input[25] la_input[26] la_input[27] la_input[28] la_input[29] la_input[2]
++ la_input[30] la_input[31] la_input[32] la_input[33] la_input[34] la_input[35] la_input[36]
++ la_input[37] la_input[38] la_input[39] la_input[3] la_input[40] la_input[41] la_input[42]
++ la_input[43] la_input[44] la_input[45] la_input[46] la_input[47] la_input[48] la_input[49]
++ la_input[4] la_input[50] la_input[51] la_input[52] la_input[53] la_input[54] la_input[55]
++ la_input[56] la_input[57] la_input[58] la_input[59] la_input[5] la_input[60] la_input[61]
++ la_input[62] la_input[63] la_input[64] la_input[65] la_input[66] la_input[67] la_input[68]
++ la_input[69] la_input[6] la_input[70] la_input[71] la_input[72] la_input[73] la_input[74]
++ la_input[75] la_input[76] la_input[77] la_input[78] la_input[79] la_input[7] la_input[80]
++ la_input[81] la_input[82] la_input[83] la_input[84] la_input[85] la_input[86] la_input[87]
++ la_input[88] la_input[89] la_input[8] la_input[90] la_input[91] la_input[92] la_input[93]
++ la_input[94] la_input[95] la_input[96] la_input[97] la_input[98] la_input[99] la_input[9]
++ la_oen[0] la_oen[100] la_oen[101] la_oen[102] la_oen[103] la_oen[104] la_oen[105]
++ la_oen[106] la_oen[107] la_oen[108] la_oen[109] la_oen[10] la_oen[110] la_oen[111]
++ la_oen[112] la_oen[113] la_oen[114] la_oen[115] la_oen[116] la_oen[117] la_oen[118]
++ la_oen[119] la_oen[11] la_oen[120] la_oen[121] la_oen[122] la_oen[123] la_oen[124]
++ la_oen[125] la_oen[126] la_oen[127] la_oen[12] la_oen[13] la_oen[14] la_oen[15]
++ la_oen[16] la_oen[17] la_oen[18] la_oen[19] la_oen[1] la_oen[20] la_oen[21] la_oen[22]
++ la_oen[23] la_oen[24] la_oen[25] la_oen[26] la_oen[27] la_oen[28] la_oen[29] la_oen[2]
++ la_oen[30] la_oen[31] la_oen[32] la_oen[33] la_oen[34] la_oen[35] la_oen[36] la_oen[37]
++ la_oen[38] la_oen[39] la_oen[3] la_oen[40] la_oen[41] la_oen[42] la_oen[43] la_oen[44]
++ la_oen[45] la_oen[46] la_oen[47] la_oen[48] la_oen[49] la_oen[4] la_oen[50] la_oen[51]
++ la_oen[52] la_oen[53] la_oen[54] la_oen[55] la_oen[56] la_oen[57] la_oen[58] la_oen[59]
++ la_oen[5] la_oen[60] la_oen[61] la_oen[62] la_oen[63] la_oen[64] la_oen[65] la_oen[66]
++ la_oen[67] la_oen[68] la_oen[69] la_oen[6] la_oen[70] la_oen[71] la_oen[72] la_oen[73]
++ la_oen[74] la_oen[75] la_oen[76] la_oen[77] la_oen[78] la_oen[79] la_oen[7] la_oen[80]
++ la_oen[81] la_oen[82] la_oen[83] la_oen[84] la_oen[85] la_oen[86] la_oen[87] la_oen[88]
++ la_oen[89] la_oen[8] la_oen[90] la_oen[91] la_oen[92] la_oen[93] la_oen[94] la_oen[95]
++ la_oen[96] la_oen[97] la_oen[98] la_oen[99] la_oen[9] la_output[0] la_output[100]
++ la_output[101] la_output[102] la_output[103] la_output[104] la_output[105] la_output[106]
++ la_output[107] la_output[108] la_output[109] la_output[10] la_output[110] la_output[111]
++ la_output[112] la_output[113] la_output[114] la_output[115] la_output[116] la_output[117]
++ la_output[118] la_output[119] la_output[11] la_output[120] la_output[121] la_output[122]
++ la_output[123] la_output[124] la_output[125] la_output[126] la_output[127] la_output[12]
++ la_output[13] la_output[14] la_output[15] la_output[16] la_output[17] la_output[18]
++ la_output[19] la_output[1] la_output[20] la_output[21] la_output[22] la_output[23]
++ la_output[24] la_output[25] la_output[26] la_output[27] la_output[28] la_output[29]
++ la_output[2] la_output[30] la_output[31] la_output[32] la_output[33] la_output[34]
++ la_output[35] la_output[36] la_output[37] la_output[38] la_output[39] la_output[3]
++ la_output[40] la_output[41] la_output[42] la_output[43] la_output[44] la_output[45]
++ la_output[46] la_output[47] la_output[48] la_output[49] la_output[4] la_output[50]
++ la_output[51] la_output[52] la_output[53] la_output[54] la_output[55] la_output[56]
++ la_output[57] la_output[58] la_output[59] la_output[5] la_output[60] la_output[61]
++ la_output[62] la_output[63] la_output[64] la_output[65] la_output[66] la_output[67]
++ la_output[68] la_output[69] la_output[6] la_output[70] la_output[71] la_output[72]
++ la_output[73] la_output[74] la_output[75] la_output[76] la_output[77] la_output[78]
++ la_output[79] la_output[7] la_output[80] la_output[81] la_output[82] la_output[83]
++ la_output[84] la_output[85] la_output[86] la_output[87] la_output[88] la_output[89]
++ la_output[8] la_output[90] la_output[91] la_output[92] la_output[93] la_output[94]
++ la_output[95] la_output[96] la_output[97] la_output[98] la_output[99] la_output[9]
++ mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13] mask_rev[14] mask_rev[15]
++ mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1] mask_rev[20] mask_rev[21]
++ mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26] mask_rev[27] mask_rev[28]
++ mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3] mask_rev[4] mask_rev[5]
++ mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] mgmt_addr[0] mgmt_addr[1] mgmt_addr[2]
++ mgmt_addr[3] mgmt_addr[4] mgmt_addr[5] mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0]
++ mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3] mgmt_addr_ro[4] mgmt_addr_ro[5]
++ mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_ena[0] mgmt_ena[1] mgmt_ena_ro mgmt_in_data[0]
++ mgmt_in_data[10] mgmt_in_data[11] mgmt_in_data[12] mgmt_in_data[13] mgmt_in_data[14]
++ mgmt_in_data[15] mgmt_in_data[16] mgmt_in_data[17] mgmt_in_data[18] mgmt_in_data[19]
++ mgmt_in_data[1] mgmt_in_data[20] mgmt_in_data[21] mgmt_in_data[22] mgmt_in_data[23]
++ mgmt_in_data[24] mgmt_in_data[25] mgmt_in_data[26] mgmt_in_data[27] mgmt_in_data[28]
++ mgmt_in_data[29] mgmt_in_data[2] mgmt_in_data[30] mgmt_in_data[31] mgmt_in_data[32]
++ mgmt_in_data[33] mgmt_in_data[34] mgmt_in_data[35] mgmt_in_data[36] mgmt_in_data[37]
++ mgmt_in_data[3] mgmt_in_data[4] mgmt_in_data[5] mgmt_in_data[6] mgmt_in_data[7]
++ mgmt_in_data[8] mgmt_in_data[9] mgmt_out_data[0] mgmt_out_data[10] mgmt_out_data[11]
++ mgmt_out_data[12] mgmt_out_data[13] mgmt_out_data[14] mgmt_out_data[15] mgmt_out_data[16]
++ mgmt_out_data[17] mgmt_out_data[18] mgmt_out_data[19] mgmt_out_data[1] mgmt_out_data[20]
++ mgmt_out_data[21] mgmt_out_data[22] mgmt_out_data[23] mgmt_out_data[24] mgmt_out_data[25]
++ mgmt_out_data[26] mgmt_out_data[27] mgmt_out_data[28] mgmt_out_data[29] mgmt_out_data[2]
++ mgmt_out_data[30] mgmt_out_data[31] mgmt_out_data[32] mgmt_out_data[33] mgmt_out_data[34]
++ mgmt_out_data[35] mgmt_out_data[36] mgmt_out_data[37] mgmt_out_data[3] mgmt_out_data[4]
++ mgmt_out_data[5] mgmt_out_data[6] mgmt_out_data[7] mgmt_out_data[8] mgmt_out_data[9]
++ mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12] mgmt_rdata[13] mgmt_rdata[14]
++ mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18] mgmt_rdata[19] mgmt_rdata[1]
++ mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23] mgmt_rdata[24] mgmt_rdata[25]
++ mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29] mgmt_rdata[2] mgmt_rdata[30]
++ mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34] mgmt_rdata[35] mgmt_rdata[36]
++ mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3] mgmt_rdata[40] mgmt_rdata[41]
++ mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45] mgmt_rdata[46] mgmt_rdata[47]
++ mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50] mgmt_rdata[51] mgmt_rdata[52]
++ mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56] mgmt_rdata[57] mgmt_rdata[58]
++ mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61] mgmt_rdata[62] mgmt_rdata[63]
++ mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9] mgmt_rdata_ro[0] mgmt_rdata_ro[10]
++ mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13] mgmt_rdata_ro[14] mgmt_rdata_ro[15]
++ mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18] mgmt_rdata_ro[19] mgmt_rdata_ro[1]
++ mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22] mgmt_rdata_ro[23] mgmt_rdata_ro[24]
++ mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27] mgmt_rdata_ro[28] mgmt_rdata_ro[29]
++ mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31] mgmt_rdata_ro[3] mgmt_rdata_ro[4]
++ mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7] mgmt_rdata_ro[8] mgmt_rdata_ro[9]
++ mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12] mgmt_wdata[13] mgmt_wdata[14]
++ mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18] mgmt_wdata[19] mgmt_wdata[1]
++ mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23] mgmt_wdata[24] mgmt_wdata[25]
++ mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29] mgmt_wdata[2] mgmt_wdata[30]
++ mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5] mgmt_wdata[6] mgmt_wdata[7]
++ mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1] mgmt_wen_mask[0] mgmt_wen_mask[1]
++ mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4] mgmt_wen_mask[5] mgmt_wen_mask[6]
++ mgmt_wen_mask[7] mprj2_vcc_pwrgood mprj2_vdd_pwrgood mprj_ack_i mprj_adr_o[0] mprj_adr_o[10]
++ mprj_adr_o[11] mprj_adr_o[12] mprj_adr_o[13] mprj_adr_o[14] mprj_adr_o[15] mprj_adr_o[16]
++ mprj_adr_o[17] mprj_adr_o[18] mprj_adr_o[19] mprj_adr_o[1] mprj_adr_o[20] mprj_adr_o[21]
++ mprj_adr_o[22] mprj_adr_o[23] mprj_adr_o[24] mprj_adr_o[25] mprj_adr_o[26] mprj_adr_o[27]
++ mprj_adr_o[28] mprj_adr_o[29] mprj_adr_o[2] mprj_adr_o[30] mprj_adr_o[31] mprj_adr_o[3]
++ mprj_adr_o[4] mprj_adr_o[5] mprj_adr_o[6] mprj_adr_o[7] mprj_adr_o[8] mprj_adr_o[9]
++ mprj_cyc_o mprj_dat_i[0] mprj_dat_i[10] mprj_dat_i[11] mprj_dat_i[12] mprj_dat_i[13]
++ mprj_dat_i[14] mprj_dat_i[15] mprj_dat_i[16] mprj_dat_i[17] mprj_dat_i[18] mprj_dat_i[19]
++ mprj_dat_i[1] mprj_dat_i[20] mprj_dat_i[21] mprj_dat_i[22] mprj_dat_i[23] mprj_dat_i[24]
++ mprj_dat_i[25] mprj_dat_i[26] mprj_dat_i[27] mprj_dat_i[28] mprj_dat_i[29] mprj_dat_i[2]
++ mprj_dat_i[30] mprj_dat_i[31] mprj_dat_i[3] mprj_dat_i[4] mprj_dat_i[5] mprj_dat_i[6]
++ mprj_dat_i[7] mprj_dat_i[8] mprj_dat_i[9] mprj_dat_o[0] mprj_dat_o[10] mprj_dat_o[11]
++ mprj_dat_o[12] mprj_dat_o[13] mprj_dat_o[14] mprj_dat_o[15] mprj_dat_o[16] mprj_dat_o[17]
++ mprj_dat_o[18] mprj_dat_o[19] mprj_dat_o[1] mprj_dat_o[20] mprj_dat_o[21] mprj_dat_o[22]
++ mprj_dat_o[23] mprj_dat_o[24] mprj_dat_o[25] mprj_dat_o[26] mprj_dat_o[27] mprj_dat_o[28]
++ mprj_dat_o[29] mprj_dat_o[2] mprj_dat_o[30] mprj_dat_o[31] mprj_dat_o[3] mprj_dat_o[4]
++ mprj_dat_o[5] mprj_dat_o[6] mprj_dat_o[7] mprj_dat_o[8] mprj_dat_o[9] mprj_io_loader_clock
++ mprj_io_loader_data mprj_io_loader_resetn mprj_sel_o[0] mprj_sel_o[1] mprj_sel_o[2]
++ mprj_sel_o[3] mprj_stb_o mprj_vcc_pwrgood mprj_vdd_pwrgood mprj_we_o porb pwr_ctrl_out[0]
++ pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] resetb sdo_out sdo_outenb user_clk
++ VPWR VGND
+.ends
+
+* Black-box entry subcircuit for user_id_textblock abstract view
+.subckt user_id_textblock VSUBS
+.ends
+
+* Black-box entry subcircuit for simple_por abstract view
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+.ends
+
+* Black-box entry subcircuit for user_id_programming abstract view
+.subckt user_id_programming mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13]
++ mask_rev[14] mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1]
++ mask_rev[20] mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26]
++ mask_rev[27] mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3]
++ mask_rev[4] mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for open_source abstract view
+.subckt open_source VSUBS
+.ends
+
+* Black-box entry subcircuit for mgmt_protect abstract view
+.subckt mgmt_protect caravel_clk caravel_clk2 caravel_rstn la_data_in_core[0] la_data_in_core[100]
++ la_data_in_core[101] la_data_in_core[102] la_data_in_core[103] la_data_in_core[104]
++ la_data_in_core[105] la_data_in_core[106] la_data_in_core[107] la_data_in_core[108]
++ la_data_in_core[109] la_data_in_core[10] la_data_in_core[110] la_data_in_core[111]
++ la_data_in_core[112] la_data_in_core[113] la_data_in_core[114] la_data_in_core[115]
++ la_data_in_core[116] la_data_in_core[117] la_data_in_core[118] la_data_in_core[119]
++ la_data_in_core[11] la_data_in_core[120] la_data_in_core[121] la_data_in_core[122]
++ la_data_in_core[123] la_data_in_core[124] la_data_in_core[125] la_data_in_core[126]
++ la_data_in_core[127] la_data_in_core[12] la_data_in_core[13] la_data_in_core[14]
++ la_data_in_core[15] la_data_in_core[16] la_data_in_core[17] la_data_in_core[18]
++ la_data_in_core[19] la_data_in_core[1] la_data_in_core[20] la_data_in_core[21] la_data_in_core[22]
++ la_data_in_core[23] la_data_in_core[24] la_data_in_core[25] la_data_in_core[26]
++ la_data_in_core[27] la_data_in_core[28] la_data_in_core[29] la_data_in_core[2] la_data_in_core[30]
++ la_data_in_core[31] la_data_in_core[32] la_data_in_core[33] la_data_in_core[34]
++ la_data_in_core[35] la_data_in_core[36] la_data_in_core[37] la_data_in_core[38]
++ la_data_in_core[39] la_data_in_core[3] la_data_in_core[40] la_data_in_core[41] la_data_in_core[42]
++ la_data_in_core[43] la_data_in_core[44] la_data_in_core[45] la_data_in_core[46]
++ la_data_in_core[47] la_data_in_core[48] la_data_in_core[49] la_data_in_core[4] la_data_in_core[50]
++ la_data_in_core[51] la_data_in_core[52] la_data_in_core[53] la_data_in_core[54]
++ la_data_in_core[55] la_data_in_core[56] la_data_in_core[57] la_data_in_core[58]
++ la_data_in_core[59] la_data_in_core[5] la_data_in_core[60] la_data_in_core[61] la_data_in_core[62]
++ la_data_in_core[63] la_data_in_core[64] la_data_in_core[65] la_data_in_core[66]
++ la_data_in_core[67] la_data_in_core[68] la_data_in_core[69] la_data_in_core[6] la_data_in_core[70]
++ la_data_in_core[71] la_data_in_core[72] la_data_in_core[73] la_data_in_core[74]
++ la_data_in_core[75] la_data_in_core[76] la_data_in_core[77] la_data_in_core[78]
++ la_data_in_core[79] la_data_in_core[7] la_data_in_core[80] la_data_in_core[81] la_data_in_core[82]
++ la_data_in_core[83] la_data_in_core[84] la_data_in_core[85] la_data_in_core[86]
++ la_data_in_core[87] la_data_in_core[88] la_data_in_core[89] la_data_in_core[8] la_data_in_core[90]
++ la_data_in_core[91] la_data_in_core[92] la_data_in_core[93] la_data_in_core[94]
++ la_data_in_core[95] la_data_in_core[96] la_data_in_core[97] la_data_in_core[98]
++ la_data_in_core[99] la_data_in_core[9] la_data_in_mprj[0] la_data_in_mprj[100] la_data_in_mprj[101]
++ la_data_in_mprj[102] la_data_in_mprj[103] la_data_in_mprj[104] la_data_in_mprj[105]
++ la_data_in_mprj[106] la_data_in_mprj[107] la_data_in_mprj[108] la_data_in_mprj[109]
++ la_data_in_mprj[10] la_data_in_mprj[110] la_data_in_mprj[111] la_data_in_mprj[112]
++ la_data_in_mprj[113] la_data_in_mprj[114] la_data_in_mprj[115] la_data_in_mprj[116]
++ la_data_in_mprj[117] la_data_in_mprj[118] la_data_in_mprj[119] la_data_in_mprj[11]
++ la_data_in_mprj[120] la_data_in_mprj[121] la_data_in_mprj[122] la_data_in_mprj[123]
++ la_data_in_mprj[124] la_data_in_mprj[125] la_data_in_mprj[126] la_data_in_mprj[127]
++ la_data_in_mprj[12] la_data_in_mprj[13] la_data_in_mprj[14] la_data_in_mprj[15]
++ la_data_in_mprj[16] la_data_in_mprj[17] la_data_in_mprj[18] la_data_in_mprj[19]
++ la_data_in_mprj[1] la_data_in_mprj[20] la_data_in_mprj[21] la_data_in_mprj[22] la_data_in_mprj[23]
++ la_data_in_mprj[24] la_data_in_mprj[25] la_data_in_mprj[26] la_data_in_mprj[27]
++ la_data_in_mprj[28] la_data_in_mprj[29] la_data_in_mprj[2] la_data_in_mprj[30] la_data_in_mprj[31]
++ la_data_in_mprj[32] la_data_in_mprj[33] la_data_in_mprj[34] la_data_in_mprj[35]
++ la_data_in_mprj[36] la_data_in_mprj[37] la_data_in_mprj[38] la_data_in_mprj[39]
++ la_data_in_mprj[3] la_data_in_mprj[40] la_data_in_mprj[41] la_data_in_mprj[42] la_data_in_mprj[43]
++ la_data_in_mprj[44] la_data_in_mprj[45] la_data_in_mprj[46] la_data_in_mprj[47]
++ la_data_in_mprj[48] la_data_in_mprj[49] la_data_in_mprj[4] la_data_in_mprj[50] la_data_in_mprj[51]
++ la_data_in_mprj[52] la_data_in_mprj[53] la_data_in_mprj[54] la_data_in_mprj[55]
++ la_data_in_mprj[56] la_data_in_mprj[57] la_data_in_mprj[58] la_data_in_mprj[59]
++ la_data_in_mprj[5] la_data_in_mprj[60] la_data_in_mprj[61] la_data_in_mprj[62] la_data_in_mprj[63]
++ la_data_in_mprj[64] la_data_in_mprj[65] la_data_in_mprj[66] la_data_in_mprj[67]
++ la_data_in_mprj[68] la_data_in_mprj[69] la_data_in_mprj[6] la_data_in_mprj[70] la_data_in_mprj[71]
++ la_data_in_mprj[72] la_data_in_mprj[73] la_data_in_mprj[74] la_data_in_mprj[75]
++ la_data_in_mprj[76] la_data_in_mprj[77] la_data_in_mprj[78] la_data_in_mprj[79]
++ la_data_in_mprj[7] la_data_in_mprj[80] la_data_in_mprj[81] la_data_in_mprj[82] la_data_in_mprj[83]
++ la_data_in_mprj[84] la_data_in_mprj[85] la_data_in_mprj[86] la_data_in_mprj[87]
++ la_data_in_mprj[88] la_data_in_mprj[89] la_data_in_mprj[8] la_data_in_mprj[90] la_data_in_mprj[91]
++ la_data_in_mprj[92] la_data_in_mprj[93] la_data_in_mprj[94] la_data_in_mprj[95]
++ la_data_in_mprj[96] la_data_in_mprj[97] la_data_in_mprj[98] la_data_in_mprj[99]
++ la_data_in_mprj[9] la_data_out_core[0] la_data_out_core[100] la_data_out_core[101]
++ la_data_out_core[102] la_data_out_core[103] la_data_out_core[104] la_data_out_core[105]
++ la_data_out_core[106] la_data_out_core[107] la_data_out_core[108] la_data_out_core[109]
++ la_data_out_core[10] la_data_out_core[110] la_data_out_core[111] la_data_out_core[112]
++ la_data_out_core[113] la_data_out_core[114] la_data_out_core[115] la_data_out_core[116]
++ la_data_out_core[117] la_data_out_core[118] la_data_out_core[119] la_data_out_core[11]
++ la_data_out_core[120] la_data_out_core[121] la_data_out_core[122] la_data_out_core[123]
++ la_data_out_core[124] la_data_out_core[125] la_data_out_core[126] la_data_out_core[127]
++ la_data_out_core[12] la_data_out_core[13] la_data_out_core[14] la_data_out_core[15]
++ la_data_out_core[16] la_data_out_core[17] la_data_out_core[18] la_data_out_core[19]
++ la_data_out_core[1] la_data_out_core[20] la_data_out_core[21] la_data_out_core[22]
++ la_data_out_core[23] la_data_out_core[24] la_data_out_core[25] la_data_out_core[26]
++ la_data_out_core[27] la_data_out_core[28] la_data_out_core[29] la_data_out_core[2]
++ la_data_out_core[30] la_data_out_core[31] la_data_out_core[32] la_data_out_core[33]
++ la_data_out_core[34] la_data_out_core[35] la_data_out_core[36] la_data_out_core[37]
++ la_data_out_core[38] la_data_out_core[39] la_data_out_core[3] la_data_out_core[40]
++ la_data_out_core[41] la_data_out_core[42] la_data_out_core[43] la_data_out_core[44]
++ la_data_out_core[45] la_data_out_core[46] la_data_out_core[47] la_data_out_core[48]
++ la_data_out_core[49] la_data_out_core[4] la_data_out_core[50] la_data_out_core[51]
++ la_data_out_core[52] la_data_out_core[53] la_data_out_core[54] la_data_out_core[55]
++ la_data_out_core[56] la_data_out_core[57] la_data_out_core[58] la_data_out_core[59]
++ la_data_out_core[5] la_data_out_core[60] la_data_out_core[61] la_data_out_core[62]
++ la_data_out_core[63] la_data_out_core[64] la_data_out_core[65] la_data_out_core[66]
++ la_data_out_core[67] la_data_out_core[68] la_data_out_core[69] la_data_out_core[6]
++ la_data_out_core[70] la_data_out_core[71] la_data_out_core[72] la_data_out_core[73]
++ la_data_out_core[74] la_data_out_core[75] la_data_out_core[76] la_data_out_core[77]
++ la_data_out_core[78] la_data_out_core[79] la_data_out_core[7] la_data_out_core[80]
++ la_data_out_core[81] la_data_out_core[82] la_data_out_core[83] la_data_out_core[84]
++ la_data_out_core[85] la_data_out_core[86] la_data_out_core[87] la_data_out_core[88]
++ la_data_out_core[89] la_data_out_core[8] la_data_out_core[90] la_data_out_core[91]
++ la_data_out_core[92] la_data_out_core[93] la_data_out_core[94] la_data_out_core[95]
++ la_data_out_core[96] la_data_out_core[97] la_data_out_core[98] la_data_out_core[99]
++ la_data_out_core[9] la_data_out_mprj[0] la_data_out_mprj[100] la_data_out_mprj[101]
++ la_data_out_mprj[102] la_data_out_mprj[103] la_data_out_mprj[104] la_data_out_mprj[105]
++ la_data_out_mprj[106] la_data_out_mprj[107] la_data_out_mprj[108] la_data_out_mprj[109]
++ la_data_out_mprj[10] la_data_out_mprj[110] la_data_out_mprj[111] la_data_out_mprj[112]
++ la_data_out_mprj[113] la_data_out_mprj[114] la_data_out_mprj[115] la_data_out_mprj[116]
++ la_data_out_mprj[117] la_data_out_mprj[118] la_data_out_mprj[119] la_data_out_mprj[11]
++ la_data_out_mprj[120] la_data_out_mprj[121] la_data_out_mprj[122] la_data_out_mprj[123]
++ la_data_out_mprj[124] la_data_out_mprj[125] la_data_out_mprj[126] la_data_out_mprj[127]
++ la_data_out_mprj[12] la_data_out_mprj[13] la_data_out_mprj[14] la_data_out_mprj[15]
++ la_data_out_mprj[16] la_data_out_mprj[17] la_data_out_mprj[18] la_data_out_mprj[19]
++ la_data_out_mprj[1] la_data_out_mprj[20] la_data_out_mprj[21] la_data_out_mprj[22]
++ la_data_out_mprj[23] la_data_out_mprj[24] la_data_out_mprj[25] la_data_out_mprj[26]
++ la_data_out_mprj[27] la_data_out_mprj[28] la_data_out_mprj[29] la_data_out_mprj[2]
++ la_data_out_mprj[30] la_data_out_mprj[31] la_data_out_mprj[32] la_data_out_mprj[33]
++ la_data_out_mprj[34] la_data_out_mprj[35] la_data_out_mprj[36] la_data_out_mprj[37]
++ la_data_out_mprj[38] la_data_out_mprj[39] la_data_out_mprj[3] la_data_out_mprj[40]
++ la_data_out_mprj[41] la_data_out_mprj[42] la_data_out_mprj[43] la_data_out_mprj[44]
++ la_data_out_mprj[45] la_data_out_mprj[46] la_data_out_mprj[47] la_data_out_mprj[48]
++ la_data_out_mprj[49] la_data_out_mprj[4] la_data_out_mprj[50] la_data_out_mprj[51]
++ la_data_out_mprj[52] la_data_out_mprj[53] la_data_out_mprj[54] la_data_out_mprj[55]
++ la_data_out_mprj[56] la_data_out_mprj[57] la_data_out_mprj[58] la_data_out_mprj[59]
++ la_data_out_mprj[5] la_data_out_mprj[60] la_data_out_mprj[61] la_data_out_mprj[62]
++ la_data_out_mprj[63] la_data_out_mprj[64] la_data_out_mprj[65] la_data_out_mprj[66]
++ la_data_out_mprj[67] la_data_out_mprj[68] la_data_out_mprj[69] la_data_out_mprj[6]
++ la_data_out_mprj[70] la_data_out_mprj[71] la_data_out_mprj[72] la_data_out_mprj[73]
++ la_data_out_mprj[74] la_data_out_mprj[75] la_data_out_mprj[76] la_data_out_mprj[77]
++ la_data_out_mprj[78] la_data_out_mprj[79] la_data_out_mprj[7] la_data_out_mprj[80]
++ la_data_out_mprj[81] la_data_out_mprj[82] la_data_out_mprj[83] la_data_out_mprj[84]
++ la_data_out_mprj[85] la_data_out_mprj[86] la_data_out_mprj[87] la_data_out_mprj[88]
++ la_data_out_mprj[89] la_data_out_mprj[8] la_data_out_mprj[90] la_data_out_mprj[91]
++ la_data_out_mprj[92] la_data_out_mprj[93] la_data_out_mprj[94] la_data_out_mprj[95]
++ la_data_out_mprj[96] la_data_out_mprj[97] la_data_out_mprj[98] la_data_out_mprj[99]
++ la_data_out_mprj[9] la_oen_core[0] la_oen_core[100] la_oen_core[101] la_oen_core[102]
++ la_oen_core[103] la_oen_core[104] la_oen_core[105] la_oen_core[106] la_oen_core[107]
++ la_oen_core[108] la_oen_core[109] la_oen_core[10] la_oen_core[110] la_oen_core[111]
++ la_oen_core[112] la_oen_core[113] la_oen_core[114] la_oen_core[115] la_oen_core[116]
++ la_oen_core[117] la_oen_core[118] la_oen_core[119] la_oen_core[11] la_oen_core[120]
++ la_oen_core[121] la_oen_core[122] la_oen_core[123] la_oen_core[124] la_oen_core[125]
++ la_oen_core[126] la_oen_core[127] la_oen_core[12] la_oen_core[13] la_oen_core[14]
++ la_oen_core[15] la_oen_core[16] la_oen_core[17] la_oen_core[18] la_oen_core[19]
++ la_oen_core[1] la_oen_core[20] la_oen_core[21] la_oen_core[22] la_oen_core[23] la_oen_core[24]
++ la_oen_core[25] la_oen_core[26] la_oen_core[27] la_oen_core[28] la_oen_core[29]
++ la_oen_core[2] la_oen_core[30] la_oen_core[31] la_oen_core[32] la_oen_core[33] la_oen_core[34]
++ la_oen_core[35] la_oen_core[36] la_oen_core[37] la_oen_core[38] la_oen_core[39]
++ la_oen_core[3] la_oen_core[40] la_oen_core[41] la_oen_core[42] la_oen_core[43] la_oen_core[44]
++ la_oen_core[45] la_oen_core[46] la_oen_core[47] la_oen_core[48] la_oen_core[49]
++ la_oen_core[4] la_oen_core[50] la_oen_core[51] la_oen_core[52] la_oen_core[53] la_oen_core[54]
++ la_oen_core[55] la_oen_core[56] la_oen_core[57] la_oen_core[58] la_oen_core[59]
++ la_oen_core[5] la_oen_core[60] la_oen_core[61] la_oen_core[62] la_oen_core[63] la_oen_core[64]
++ la_oen_core[65] la_oen_core[66] la_oen_core[67] la_oen_core[68] la_oen_core[69]
++ la_oen_core[6] la_oen_core[70] la_oen_core[71] la_oen_core[72] la_oen_core[73] la_oen_core[74]
++ la_oen_core[75] la_oen_core[76] la_oen_core[77] la_oen_core[78] la_oen_core[79]
++ la_oen_core[7] la_oen_core[80] la_oen_core[81] la_oen_core[82] la_oen_core[83] la_oen_core[84]
++ la_oen_core[85] la_oen_core[86] la_oen_core[87] la_oen_core[88] la_oen_core[89]
++ la_oen_core[8] la_oen_core[90] la_oen_core[91] la_oen_core[92] la_oen_core[93] la_oen_core[94]
++ la_oen_core[95] la_oen_core[96] la_oen_core[97] la_oen_core[98] la_oen_core[99]
++ la_oen_core[9] la_oen_mprj[0] la_oen_mprj[100] la_oen_mprj[101] la_oen_mprj[102]
++ la_oen_mprj[103] la_oen_mprj[104] la_oen_mprj[105] la_oen_mprj[106] la_oen_mprj[107]
++ la_oen_mprj[108] la_oen_mprj[109] la_oen_mprj[10] la_oen_mprj[110] la_oen_mprj[111]
++ la_oen_mprj[112] la_oen_mprj[113] la_oen_mprj[114] la_oen_mprj[115] la_oen_mprj[116]
++ la_oen_mprj[117] la_oen_mprj[118] la_oen_mprj[119] la_oen_mprj[11] la_oen_mprj[120]
++ la_oen_mprj[121] la_oen_mprj[122] la_oen_mprj[123] la_oen_mprj[124] la_oen_mprj[125]
++ la_oen_mprj[126] la_oen_mprj[127] la_oen_mprj[12] la_oen_mprj[13] la_oen_mprj[14]
++ la_oen_mprj[15] la_oen_mprj[16] la_oen_mprj[17] la_oen_mprj[18] la_oen_mprj[19]
++ la_oen_mprj[1] la_oen_mprj[20] la_oen_mprj[21] la_oen_mprj[22] la_oen_mprj[23] la_oen_mprj[24]
++ la_oen_mprj[25] la_oen_mprj[26] la_oen_mprj[27] la_oen_mprj[28] la_oen_mprj[29]
++ la_oen_mprj[2] la_oen_mprj[30] la_oen_mprj[31] la_oen_mprj[32] la_oen_mprj[33] la_oen_mprj[34]
++ la_oen_mprj[35] la_oen_mprj[36] la_oen_mprj[37] la_oen_mprj[38] la_oen_mprj[39]
++ la_oen_mprj[3] la_oen_mprj[40] la_oen_mprj[41] la_oen_mprj[42] la_oen_mprj[43] la_oen_mprj[44]
++ la_oen_mprj[45] la_oen_mprj[46] la_oen_mprj[47] la_oen_mprj[48] la_oen_mprj[49]
++ la_oen_mprj[4] la_oen_mprj[50] la_oen_mprj[51] la_oen_mprj[52] la_oen_mprj[53] la_oen_mprj[54]
++ la_oen_mprj[55] la_oen_mprj[56] la_oen_mprj[57] la_oen_mprj[58] la_oen_mprj[59]
++ la_oen_mprj[5] la_oen_mprj[60] la_oen_mprj[61] la_oen_mprj[62] la_oen_mprj[63] la_oen_mprj[64]
++ la_oen_mprj[65] la_oen_mprj[66] la_oen_mprj[67] la_oen_mprj[68] la_oen_mprj[69]
++ la_oen_mprj[6] la_oen_mprj[70] la_oen_mprj[71] la_oen_mprj[72] la_oen_mprj[73] la_oen_mprj[74]
++ la_oen_mprj[75] la_oen_mprj[76] la_oen_mprj[77] la_oen_mprj[78] la_oen_mprj[79]
++ la_oen_mprj[7] la_oen_mprj[80] la_oen_mprj[81] la_oen_mprj[82] la_oen_mprj[83] la_oen_mprj[84]
++ la_oen_mprj[85] la_oen_mprj[86] la_oen_mprj[87] la_oen_mprj[88] la_oen_mprj[89]
++ la_oen_mprj[8] la_oen_mprj[90] la_oen_mprj[91] la_oen_mprj[92] la_oen_mprj[93] la_oen_mprj[94]
++ la_oen_mprj[95] la_oen_mprj[96] la_oen_mprj[97] la_oen_mprj[98] la_oen_mprj[99]
++ la_oen_mprj[9] mprj_adr_o_core[0] mprj_adr_o_core[10] mprj_adr_o_core[11] mprj_adr_o_core[12]
++ mprj_adr_o_core[13] mprj_adr_o_core[14] mprj_adr_o_core[15] mprj_adr_o_core[16]
++ mprj_adr_o_core[17] mprj_adr_o_core[18] mprj_adr_o_core[19] mprj_adr_o_core[1] mprj_adr_o_core[20]
++ mprj_adr_o_core[21] mprj_adr_o_core[22] mprj_adr_o_core[23] mprj_adr_o_core[24]
++ mprj_adr_o_core[25] mprj_adr_o_core[26] mprj_adr_o_core[27] mprj_adr_o_core[28]
++ mprj_adr_o_core[29] mprj_adr_o_core[2] mprj_adr_o_core[30] mprj_adr_o_core[31] mprj_adr_o_core[3]
++ mprj_adr_o_core[4] mprj_adr_o_core[5] mprj_adr_o_core[6] mprj_adr_o_core[7] mprj_adr_o_core[8]
++ mprj_adr_o_core[9] mprj_adr_o_user[0] mprj_adr_o_user[10] mprj_adr_o_user[11] mprj_adr_o_user[12]
++ mprj_adr_o_user[13] mprj_adr_o_user[14] mprj_adr_o_user[15] mprj_adr_o_user[16]
++ mprj_adr_o_user[17] mprj_adr_o_user[18] mprj_adr_o_user[19] mprj_adr_o_user[1] mprj_adr_o_user[20]
++ mprj_adr_o_user[21] mprj_adr_o_user[22] mprj_adr_o_user[23] mprj_adr_o_user[24]
++ mprj_adr_o_user[25] mprj_adr_o_user[26] mprj_adr_o_user[27] mprj_adr_o_user[28]
++ mprj_adr_o_user[29] mprj_adr_o_user[2] mprj_adr_o_user[30] mprj_adr_o_user[31] mprj_adr_o_user[3]
++ mprj_adr_o_user[4] mprj_adr_o_user[5] mprj_adr_o_user[6] mprj_adr_o_user[7] mprj_adr_o_user[8]
++ mprj_adr_o_user[9] mprj_cyc_o_core mprj_cyc_o_user mprj_dat_o_core[0] mprj_dat_o_core[10]
++ mprj_dat_o_core[11] mprj_dat_o_core[12] mprj_dat_o_core[13] mprj_dat_o_core[14]
++ mprj_dat_o_core[15] mprj_dat_o_core[16] mprj_dat_o_core[17] mprj_dat_o_core[18]
++ mprj_dat_o_core[19] mprj_dat_o_core[1] mprj_dat_o_core[20] mprj_dat_o_core[21] mprj_dat_o_core[22]
++ mprj_dat_o_core[23] mprj_dat_o_core[24] mprj_dat_o_core[25] mprj_dat_o_core[26]
++ mprj_dat_o_core[27] mprj_dat_o_core[28] mprj_dat_o_core[29] mprj_dat_o_core[2] mprj_dat_o_core[30]
++ mprj_dat_o_core[31] mprj_dat_o_core[3] mprj_dat_o_core[4] mprj_dat_o_core[5] mprj_dat_o_core[6]
++ mprj_dat_o_core[7] mprj_dat_o_core[8] mprj_dat_o_core[9] mprj_dat_o_user[0] mprj_dat_o_user[10]
++ mprj_dat_o_user[11] mprj_dat_o_user[12] mprj_dat_o_user[13] mprj_dat_o_user[14]
++ mprj_dat_o_user[15] mprj_dat_o_user[16] mprj_dat_o_user[17] mprj_dat_o_user[18]
++ mprj_dat_o_user[19] mprj_dat_o_user[1] mprj_dat_o_user[20] mprj_dat_o_user[21] mprj_dat_o_user[22]
++ mprj_dat_o_user[23] mprj_dat_o_user[24] mprj_dat_o_user[25] mprj_dat_o_user[26]
++ mprj_dat_o_user[27] mprj_dat_o_user[28] mprj_dat_o_user[29] mprj_dat_o_user[2] mprj_dat_o_user[30]
++ mprj_dat_o_user[31] mprj_dat_o_user[3] mprj_dat_o_user[4] mprj_dat_o_user[5] mprj_dat_o_user[6]
++ mprj_dat_o_user[7] mprj_dat_o_user[8] mprj_dat_o_user[9] mprj_sel_o_core[0] mprj_sel_o_core[1]
++ mprj_sel_o_core[2] mprj_sel_o_core[3] mprj_sel_o_user[0] mprj_sel_o_user[1] mprj_sel_o_user[2]
++ mprj_sel_o_user[3] mprj_stb_o_core mprj_stb_o_user mprj_we_o_core mprj_we_o_user
++ user1_vcc_powergood user1_vdd_powergood user2_vcc_powergood user2_vdd_powergood
++ user_clock user_clock2 user_reset user_resetn vccd vssd vccd1 vssd1 vccd2 vssd2
++ vdda1 vssa1 vdda2 vssa2
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped abstract view
+.subckt sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped A X VPWR VGND LVPWR LVGND
+.ends
+
+* Black-box entry subcircuit for user_project_wrapper abstract view
+.subckt user_project_wrapper analog_io[0] analog_io[10] analog_io[11] analog_io[12]
++ analog_io[13] analog_io[14] analog_io[15] analog_io[16] analog_io[17] analog_io[18]
++ analog_io[19] analog_io[1] analog_io[20] analog_io[21] analog_io[22] analog_io[23]
++ analog_io[24] analog_io[25] analog_io[26] analog_io[27] analog_io[28] analog_io[29]
++ analog_io[2] analog_io[30] analog_io[3] analog_io[4] analog_io[5] analog_io[6] analog_io[7]
++ analog_io[8] analog_io[9] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
++ io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22]
++ io_in[23] io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30]
++ io_in[31] io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4]
++ io_in[5] io_in[6] io_in[7] io_in[8] io_in[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12]
++ io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1]
++ io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[27]
++ io_oeb[28] io_oeb[29] io_oeb[2] io_oeb[30] io_oeb[31] io_oeb[32] io_oeb[33] io_oeb[34]
++ io_oeb[35] io_oeb[36] io_oeb[37] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7]
++ io_oeb[8] io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14]
++ io_out[15] io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21]
++ io_out[22] io_out[23] io_out[24] io_out[25] io_out[26] io_out[27] io_out[28] io_out[29]
++ io_out[2] io_out[30] io_out[31] io_out[32] io_out[33] io_out[34] io_out[35] io_out[36]
++ io_out[37] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9]
++ la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103] la_data_in[104]
++ la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108] la_data_in[109]
++ la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113] la_data_in[114]
++ la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118] la_data_in[119]
++ la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123] la_data_in[124]
++ la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14]
++ la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1]
++ la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25]
++ la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30]
++ la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36]
++ la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41]
++ la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47]
++ la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52]
++ la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58]
++ la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63]
++ la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69]
++ la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74]
++ la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7]
++ la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85]
++ la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90]
++ la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96]
++ la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100]
++ la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104] la_data_out[105]
++ la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109] la_data_out[10]
++ la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113] la_data_out[114]
++ la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118] la_data_out[119]
++ la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122] la_data_out[123]
++ la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127] la_data_out[12]
++ la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16] la_data_out[17]
++ la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22]
++ la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26] la_data_out[27]
++ la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32]
++ la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36] la_data_out[37]
++ la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42]
++ la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46] la_data_out[47]
++ la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52]
++ la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56] la_data_out[57]
++ la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62]
++ la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67]
++ la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72]
++ la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76] la_data_out[77]
++ la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82]
++ la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86] la_data_out[87]
++ la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92]
++ la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96] la_data_out[97]
++ la_data_out[98] la_data_out[99] la_data_out[9] la_oen[0] la_oen[100] la_oen[101]
++ la_oen[102] la_oen[103] la_oen[104] la_oen[105] la_oen[106] la_oen[107] la_oen[108]
++ la_oen[109] la_oen[10] la_oen[110] la_oen[111] la_oen[112] la_oen[113] la_oen[114]
++ la_oen[115] la_oen[116] la_oen[117] la_oen[118] la_oen[119] la_oen[11] la_oen[120]
++ la_oen[121] la_oen[122] la_oen[123] la_oen[124] la_oen[125] la_oen[126] la_oen[127]
++ la_oen[12] la_oen[13] la_oen[14] la_oen[15] la_oen[16] la_oen[17] la_oen[18] la_oen[19]
++ la_oen[1] la_oen[20] la_oen[21] la_oen[22] la_oen[23] la_oen[24] la_oen[25] la_oen[26]
++ la_oen[27] la_oen[28] la_oen[29] la_oen[2] la_oen[30] la_oen[31] la_oen[32] la_oen[33]
++ la_oen[34] la_oen[35] la_oen[36] la_oen[37] la_oen[38] la_oen[39] la_oen[3] la_oen[40]
++ la_oen[41] la_oen[42] la_oen[43] la_oen[44] la_oen[45] la_oen[46] la_oen[47] la_oen[48]
++ la_oen[49] la_oen[4] la_oen[50] la_oen[51] la_oen[52] la_oen[53] la_oen[54] la_oen[55]
++ la_oen[56] la_oen[57] la_oen[58] la_oen[59] la_oen[5] la_oen[60] la_oen[61] la_oen[62]
++ la_oen[63] la_oen[64] la_oen[65] la_oen[66] la_oen[67] la_oen[68] la_oen[69] la_oen[6]
++ la_oen[70] la_oen[71] la_oen[72] la_oen[73] la_oen[74] la_oen[75] la_oen[76] la_oen[77]
++ la_oen[78] la_oen[79] la_oen[7] la_oen[80] la_oen[81] la_oen[82] la_oen[83] la_oen[84]
++ la_oen[85] la_oen[86] la_oen[87] la_oen[88] la_oen[89] la_oen[8] la_oen[90] la_oen[91]
++ la_oen[92] la_oen[93] la_oen[94] la_oen[95] la_oen[96] la_oen[97] la_oen[98] la_oen[99]
++ la_oen[9] user_clock2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
++ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
++ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
++ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
++ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
++ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
++ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
++ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
++ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
++ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
++ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
++ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
++ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
++ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
++ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
++ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
++ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
++ vccd1 vssd1 vccd2 vssd2 vdda1 vssa1 vdda2 vssa2
+.ends
+
+* Black-box entry subcircuit for copyright_block abstract view
+.subckt copyright_block VSUBS
+.ends
+
+* Black-box entry subcircuit for storage abstract view
+.subckt storage mgmt_addr[0] mgmt_addr[1] mgmt_addr[2] mgmt_addr[3] mgmt_addr[4] mgmt_addr[5]
++ mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0] mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3]
++ mgmt_addr_ro[4] mgmt_addr_ro[5] mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_clk mgmt_ena[0]
++ mgmt_ena[1] mgmt_ena_ro mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12]
++ mgmt_rdata[13] mgmt_rdata[14] mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18]
++ mgmt_rdata[19] mgmt_rdata[1] mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23]
++ mgmt_rdata[24] mgmt_rdata[25] mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29]
++ mgmt_rdata[2] mgmt_rdata[30] mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34]
++ mgmt_rdata[35] mgmt_rdata[36] mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3]
++ mgmt_rdata[40] mgmt_rdata[41] mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45]
++ mgmt_rdata[46] mgmt_rdata[47] mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50]
++ mgmt_rdata[51] mgmt_rdata[52] mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56]
++ mgmt_rdata[57] mgmt_rdata[58] mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61]
++ mgmt_rdata[62] mgmt_rdata[63] mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9]
++ mgmt_rdata_ro[0] mgmt_rdata_ro[10] mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13]
++ mgmt_rdata_ro[14] mgmt_rdata_ro[15] mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18]
++ mgmt_rdata_ro[19] mgmt_rdata_ro[1] mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22]
++ mgmt_rdata_ro[23] mgmt_rdata_ro[24] mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27]
++ mgmt_rdata_ro[28] mgmt_rdata_ro[29] mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31]
++ mgmt_rdata_ro[3] mgmt_rdata_ro[4] mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7]
++ mgmt_rdata_ro[8] mgmt_rdata_ro[9] mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12]
++ mgmt_wdata[13] mgmt_wdata[14] mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18]
++ mgmt_wdata[19] mgmt_wdata[1] mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23]
++ mgmt_wdata[24] mgmt_wdata[25] mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29]
++ mgmt_wdata[2] mgmt_wdata[30] mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5]
++ mgmt_wdata[6] mgmt_wdata[7] mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1]
++ mgmt_wen_mask[0] mgmt_wen_mask[1] mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4]
++ mgmt_wen_mask[5] mgmt_wen_mask[6] mgmt_wen_mask[7] VPWR VGND
+.ends
+
+.subckt caravel clock flash_clk flash_csb flash_io0 flash_io1 gpio mprj_io[0] mprj_io[10]
++ mprj_io[11] mprj_io[12] mprj_io[13] mprj_io[14] mprj_io[15] mprj_io[16] mprj_io[17]
++ mprj_io[18] mprj_io[19] mprj_io[1] mprj_io[20] mprj_io[21] mprj_io[22] mprj_io[23]
++ mprj_io[24] mprj_io[25] mprj_io[26] mprj_io[27] mprj_io[28] mprj_io[29] mprj_io[2]
++ mprj_io[30] mprj_io[31] mprj_io[32] mprj_io[33] mprj_io[34] mprj_io[35] mprj_io[36]
++ mprj_io[37] mprj_io[3] mprj_io[4] mprj_io[5] mprj_io[6] mprj_io[7] mprj_io[8] mprj_io[9]
++ resetb vccd1 vccd2 vdda vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 vddio vssio vssa vccd
++ vssd pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3]
+Xgpio_control_in\[28\] soc/mgmt_in_data[28] gpio_control_in\[28\]/one soc/mgmt_in_data[28]
++ gpio_control_in\[28\]/one padframe/mprj_io_analog_en[28] padframe/mprj_io_analog_pol[28]
++ padframe/mprj_io_analog_sel[28] padframe/mprj_io_dm[84] padframe/mprj_io_dm[85]
++ padframe/mprj_io_dm[86] padframe/mprj_io_holdover[28] padframe/mprj_io_ib_mode_sel[28]
++ padframe/mprj_io_in[28] padframe/mprj_io_inp_dis[28] padframe/mprj_io_out[28] padframe/mprj_io_oeb[28]
++ padframe/mprj_io_slow_sel[28] padframe/mprj_io_vtrip_sel[28] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[28\]/serial_data_in gpio_control_in\[29\]/serial_data_in
++ mprj/io_in[28] mprj/io_oeb[28] mprj/io_out[28] gpio_control_in\[28\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[10\] soc/mgmt_in_data[10] gpio_control_in\[10\]/one soc/mgmt_in_data[10]
++ gpio_control_in\[10\]/one padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10]
++ padframe/mprj_io_analog_sel[10] padframe/mprj_io_dm[30] padframe/mprj_io_dm[31]
++ padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10] padframe/mprj_io_ib_mode_sel[10]
++ padframe/mprj_io_in[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_out[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[9\]/serial_data_out gpio_control_in\[11\]/serial_data_in
++ mprj/io_in[10] mprj/io_oeb[10] mprj/io_out[10] gpio_control_in\[10\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xpadframe clock soc/clock por/por_l flash_clk soc/flash_clk soc/flash_clk_ieb soc/flash_clk_oeb
++ flash_csb soc/flash_csb soc/flash_csb_ieb soc/flash_csb_oeb flash_io0 soc/flash_io0_di
++ soc/flash_io0_do soc/flash_io0_ieb soc/flash_io0_oeb flash_io1 soc/flash_io1_di
++ soc/flash_io1_do soc/flash_io1_ieb soc/flash_io1_oeb gpio soc/gpio_in_pad soc/gpio_inenb_pad
++ soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad vccd
++ vdda vddio vssa vssd vssio mprj_io[0] padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0]
++ padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2]
++ por/porb_h vddio padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_oeb[0] padframe/mprj_io_out[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ padframe/mprj_io_in[0] mprj/analog_io[3] mprj_io[10] padframe/mprj_io_analog_en[10]
++ padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10] padframe/mprj_io_dm[30]
++ padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] por/porb_h vddio padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10]
++ padframe/mprj_io_in[10] mprj/analog_io[4] mprj_io[11] padframe/mprj_io_analog_en[11]
++ padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33]
++ padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] por/porb_h vddio padframe/mprj_io_holdover[11]
++ padframe/mprj_io_ib_mode_sel[11] padframe/mprj_io_inp_dis[11] padframe/mprj_io_oeb[11]
++ padframe/mprj_io_out[11] padframe/mprj_io_slow_sel[11] padframe/mprj_io_vtrip_sel[11]
++ padframe/mprj_io_in[11] mprj/analog_io[5] mprj_io[12] padframe/mprj_io_analog_en[12]
++ padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12] padframe/mprj_io_dm[36]
++ padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] por/porb_h vddio padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12]
++ padframe/mprj_io_in[12] mprj/analog_io[6] mprj_io[13] padframe/mprj_io_analog_en[13]
++ padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39]
++ padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] por/porb_h vddio padframe/mprj_io_holdover[13]
++ padframe/mprj_io_ib_mode_sel[13] padframe/mprj_io_inp_dis[13] padframe/mprj_io_oeb[13]
++ padframe/mprj_io_out[13] padframe/mprj_io_slow_sel[13] padframe/mprj_io_vtrip_sel[13]
++ padframe/mprj_io_in[13] mprj/analog_io[7] mprj_io[14] padframe/mprj_io_analog_en[14]
++ padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14] padframe/mprj_io_dm[42]
++ padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] por/porb_h vddio padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14]
++ padframe/mprj_io_in[14] mprj/analog_io[8] mprj_io[15] padframe/mprj_io_analog_en[15]
++ padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45]
++ padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] por/porb_h vddio padframe/mprj_io_holdover[15]
++ padframe/mprj_io_ib_mode_sel[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_out[15] padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15]
++ padframe/mprj_io_in[15] mprj/analog_io[9] mprj_io[16] padframe/mprj_io_analog_en[16]
++ padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16] padframe/mprj_io_dm[48]
++ padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] por/porb_h vddio padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16]
++ padframe/mprj_io_in[16] mprj/analog_io[10] mprj_io[17] padframe/mprj_io_analog_en[17]
++ padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51]
++ padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] por/porb_h vddio padframe/mprj_io_holdover[17]
++ padframe/mprj_io_ib_mode_sel[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_out[17] padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17]
++ padframe/mprj_io_in[17] mprj_io[1] padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1]
++ padframe/mprj_io_analog_sel[1] padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5]
++ por/porb_h vddio padframe/mprj_io_holdover[1] padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_oeb[1] padframe/mprj_io_out[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ padframe/mprj_io_in[1] mprj_io[2] padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ por/porb_h vddio padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_inp_dis[2]
++ padframe/mprj_io_oeb[2] padframe/mprj_io_out[2] padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2]
++ padframe/mprj_io_in[2] mprj_io[3] padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_dm[9]
++ por/porb_h vddio padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_inp_dis[3]
++ padframe/mprj_io_oeb[3] padframe/mprj_io_out[3] padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3]
++ padframe/mprj_io_in[3] mprj_io[4] padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ por/porb_h vddio padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_inp_dis[4]
++ padframe/mprj_io_oeb[4] padframe/mprj_io_out[4] padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4]
++ padframe/mprj_io_in[4] mprj_io[5] padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ por/porb_h vddio padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_inp_dis[5]
++ padframe/mprj_io_oeb[5] padframe/mprj_io_out[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ padframe/mprj_io_in[5] mprj_io[6] padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ por/porb_h vddio padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_inp_dis[6]
++ padframe/mprj_io_oeb[6] padframe/mprj_io_out[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ padframe/mprj_io_in[6] mprj/analog_io[0] mprj_io[7] padframe/mprj_io_analog_en[7]
++ padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21]
++ padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] por/porb_h vddio padframe/mprj_io_holdover[7]
++ padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_inp_dis[7] padframe/mprj_io_oeb[7]
++ padframe/mprj_io_out[7] padframe/mprj_io_slow_sel[7] padframe/mprj_io_vtrip_sel[7]
++ padframe/mprj_io_in[7] mprj/analog_io[1] mprj_io[8] padframe/mprj_io_analog_en[8]
++ padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8] padframe/mprj_io_dm[24]
++ padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] por/porb_h vddio padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_inp_dis[8] padframe/mprj_io_oeb[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ padframe/mprj_io_in[8] mprj/analog_io[2] mprj_io[9] padframe/mprj_io_analog_en[9]
++ padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27]
++ padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] por/porb_h vddio padframe/mprj_io_holdover[9]
++ padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_inp_dis[9] padframe/mprj_io_oeb[9]
++ padframe/mprj_io_out[9] padframe/mprj_io_slow_sel[9] padframe/mprj_io_vtrip_sel[9]
++ padframe/mprj_io_in[9] mprj/analog_io[11] mprj_io[18] padframe/mprj_io_analog_en[18]
++ padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18] padframe/mprj_io_dm[54]
++ padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] por/porb_h vddio padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18]
++ padframe/mprj_io_in[18] mprj/analog_io[21] mprj_io[28] padframe/mprj_io_analog_en[28]
++ padframe/mprj_io_analog_pol[28] padframe/mprj_io_analog_sel[28] padframe/mprj_io_dm[84]
++ padframe/mprj_io_dm[85] padframe/mprj_io_dm[86] por/porb_h vddio padframe/mprj_io_holdover[28]
++ padframe/mprj_io_ib_mode_sel[28] padframe/mprj_io_inp_dis[28] padframe/mprj_io_oeb[28]
++ padframe/mprj_io_out[28] padframe/mprj_io_slow_sel[28] padframe/mprj_io_vtrip_sel[28]
++ padframe/mprj_io_in[28] mprj/analog_io[22] mprj_io[29] padframe/mprj_io_analog_en[29]
++ padframe/mprj_io_analog_pol[29] padframe/mprj_io_analog_sel[29] padframe/mprj_io_dm[87]
++ padframe/mprj_io_dm[88] padframe/mprj_io_dm[89] por/porb_h vddio padframe/mprj_io_holdover[29]
++ padframe/mprj_io_ib_mode_sel[29] padframe/mprj_io_inp_dis[29] padframe/mprj_io_oeb[29]
++ padframe/mprj_io_out[29] padframe/mprj_io_slow_sel[29] padframe/mprj_io_vtrip_sel[29]
++ padframe/mprj_io_in[29] mprj/analog_io[23] mprj_io[30] padframe/mprj_io_analog_en[30]
++ padframe/mprj_io_analog_pol[30] padframe/mprj_io_analog_sel[30] padframe/mprj_io_dm[90]
++ padframe/mprj_io_dm[91] padframe/mprj_io_dm[92] por/porb_h vddio padframe/mprj_io_holdover[30]
++ padframe/mprj_io_ib_mode_sel[30] padframe/mprj_io_inp_dis[30] padframe/mprj_io_oeb[30]
++ padframe/mprj_io_out[30] padframe/mprj_io_slow_sel[30] padframe/mprj_io_vtrip_sel[30]
++ padframe/mprj_io_in[30] mprj/analog_io[24] mprj_io[31] padframe/mprj_io_analog_en[31]
++ padframe/mprj_io_analog_pol[31] padframe/mprj_io_analog_sel[31] padframe/mprj_io_dm[93]
++ padframe/mprj_io_dm[94] padframe/mprj_io_dm[95] por/porb_h vddio padframe/mprj_io_holdover[31]
++ padframe/mprj_io_ib_mode_sel[31] padframe/mprj_io_inp_dis[31] padframe/mprj_io_oeb[31]
++ padframe/mprj_io_out[31] padframe/mprj_io_slow_sel[31] padframe/mprj_io_vtrip_sel[31]
++ padframe/mprj_io_in[31] mprj/analog_io[25] mprj_io[32] padframe/mprj_io_analog_en[32]
++ padframe/mprj_io_analog_pol[32] padframe/mprj_io_analog_sel[32] padframe/mprj_io_dm[96]
++ padframe/mprj_io_dm[97] padframe/mprj_io_dm[98] por/porb_h vddio padframe/mprj_io_holdover[32]
++ padframe/mprj_io_ib_mode_sel[32] padframe/mprj_io_inp_dis[32] padframe/mprj_io_oeb[32]
++ padframe/mprj_io_out[32] padframe/mprj_io_slow_sel[32] padframe/mprj_io_vtrip_sel[32]
++ padframe/mprj_io_in[32] mprj/analog_io[26] mprj_io[33] padframe/mprj_io_analog_en[33]
++ padframe/mprj_io_analog_pol[33] padframe/mprj_io_analog_sel[33] padframe/mprj_io_dm[100]
++ padframe/mprj_io_dm[101] padframe/mprj_io_dm[99] por/porb_h vddio padframe/mprj_io_holdover[33]
++ padframe/mprj_io_ib_mode_sel[33] padframe/mprj_io_inp_dis[33] padframe/mprj_io_oeb[33]
++ padframe/mprj_io_out[33] padframe/mprj_io_slow_sel[33] padframe/mprj_io_vtrip_sel[33]
++ padframe/mprj_io_in[33] mprj/analog_io[27] mprj_io[34] padframe/mprj_io_analog_en[34]
++ padframe/mprj_io_analog_pol[34] padframe/mprj_io_analog_sel[34] padframe/mprj_io_dm[102]
++ padframe/mprj_io_dm[103] padframe/mprj_io_dm[104] por/porb_h vddio padframe/mprj_io_holdover[34]
++ padframe/mprj_io_ib_mode_sel[34] padframe/mprj_io_inp_dis[34] padframe/mprj_io_oeb[34]
++ padframe/mprj_io_out[34] padframe/mprj_io_slow_sel[34] padframe/mprj_io_vtrip_sel[34]
++ padframe/mprj_io_in[34] mprj/analog_io[28] mprj_io[35] padframe/mprj_io_analog_en[35]
++ padframe/mprj_io_analog_pol[35] padframe/mprj_io_analog_sel[35] padframe/mprj_io_dm[105]
++ padframe/mprj_io_dm[106] padframe/mprj_io_dm[107] por/porb_h vddio padframe/mprj_io_holdover[35]
++ padframe/mprj_io_ib_mode_sel[35] padframe/mprj_io_inp_dis[35] padframe/mprj_io_oeb[35]
++ padframe/mprj_io_out[35] padframe/mprj_io_slow_sel[35] padframe/mprj_io_vtrip_sel[35]
++ padframe/mprj_io_in[35] mprj/analog_io[29] mprj_io[36] padframe/mprj_io_analog_en[36]
++ padframe/mprj_io_analog_pol[36] padframe/mprj_io_analog_sel[36] padframe/mprj_io_dm[108]
++ padframe/mprj_io_dm[109] padframe/mprj_io_dm[110] por/porb_h vddio padframe/mprj_io_holdover[36]
++ padframe/mprj_io_ib_mode_sel[36] padframe/mprj_io_inp_dis[36] padframe/mprj_io_oeb[36]
++ padframe/mprj_io_out[36] padframe/mprj_io_slow_sel[36] padframe/mprj_io_vtrip_sel[36]
++ padframe/mprj_io_in[36] mprj/analog_io[30] mprj_io[37] padframe/mprj_io_analog_en[37]
++ padframe/mprj_io_analog_pol[37] padframe/mprj_io_analog_sel[37] padframe/mprj_io_dm[111]
++ padframe/mprj_io_dm[112] padframe/mprj_io_dm[113] por/porb_h vddio padframe/mprj_io_holdover[37]
++ padframe/mprj_io_ib_mode_sel[37] padframe/mprj_io_inp_dis[37] padframe/mprj_io_oeb[37]
++ padframe/mprj_io_out[37] padframe/mprj_io_slow_sel[37] padframe/mprj_io_vtrip_sel[37]
++ padframe/mprj_io_in[37] mprj/analog_io[12] mprj_io[19] padframe/mprj_io_analog_en[19]
++ padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19] padframe/mprj_io_dm[57]
++ padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] por/porb_h vddio padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19]
++ padframe/mprj_io_in[19] mprj/analog_io[13] mprj_io[20] padframe/mprj_io_analog_en[20]
++ padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60]
++ padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] por/porb_h vddio padframe/mprj_io_holdover[20]
++ padframe/mprj_io_ib_mode_sel[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_out[20] padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20]
++ padframe/mprj_io_in[20] mprj/analog_io[14] mprj_io[21] padframe/mprj_io_analog_en[21]
++ padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21] padframe/mprj_io_dm[63]
++ padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] por/porb_h vddio padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21]
++ padframe/mprj_io_in[21] mprj/analog_io[15] mprj_io[22] padframe/mprj_io_analog_en[22]
++ padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66]
++ padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] por/porb_h vddio padframe/mprj_io_holdover[22]
++ padframe/mprj_io_ib_mode_sel[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_out[22] padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22]
++ padframe/mprj_io_in[22] mprj/analog_io[16] mprj_io[23] padframe/mprj_io_analog_en[23]
++ padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23] padframe/mprj_io_dm[69]
++ padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] por/porb_h vddio padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23]
++ padframe/mprj_io_in[23] mprj/analog_io[17] mprj_io[24] padframe/mprj_io_analog_en[24]
++ padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72]
++ padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] por/porb_h vddio padframe/mprj_io_holdover[24]
++ padframe/mprj_io_ib_mode_sel[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_out[24] padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24]
++ padframe/mprj_io_in[24] mprj/analog_io[18] mprj_io[25] padframe/mprj_io_analog_en[25]
++ padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75]
++ padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] por/porb_h vddio padframe/mprj_io_holdover[25]
++ padframe/mprj_io_ib_mode_sel[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_out[25] padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25]
++ padframe/mprj_io_in[25] mprj/analog_io[19] mprj_io[26] padframe/mprj_io_analog_en[26]
++ padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78]
++ padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] por/porb_h vddio padframe/mprj_io_holdover[26]
++ padframe/mprj_io_ib_mode_sel[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_out[26] padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26]
++ padframe/mprj_io_in[26] mprj/analog_io[20] mprj_io[27] padframe/mprj_io_analog_en[27]
++ padframe/mprj_io_analog_pol[27] padframe/mprj_io_analog_sel[27] padframe/mprj_io_dm[81]
++ padframe/mprj_io_dm[82] padframe/mprj_io_dm[83] por/porb_h vddio padframe/mprj_io_holdover[27]
++ padframe/mprj_io_ib_mode_sel[27] padframe/mprj_io_inp_dis[27] padframe/mprj_io_oeb[27]
++ padframe/mprj_io_out[27] padframe/mprj_io_slow_sel[27] padframe/mprj_io_vtrip_sel[27]
++ padframe/mprj_io_in[27] por/porb_h resetb rstb_level/A vccd1 vdda1 vssa1 vssd1 vccd2
++ vdda2 vssa2 vssd2 chip_io
+Xgpio_control_in\[26\] soc/mgmt_in_data[26] gpio_control_in\[26\]/one soc/mgmt_in_data[26]
++ gpio_control_in\[26\]/one padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26]
++ padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78] padframe/mprj_io_dm[79]
++ padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26] padframe/mprj_io_ib_mode_sel[26]
++ padframe/mprj_io_in[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_out[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[26\]/serial_data_in gpio_control_in\[27\]/serial_data_in
++ mprj/io_in[26] mprj/io_oeb[26] mprj/io_out[26] gpio_control_in\[26\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[33\] soc/mgmt_in_data[33] gpio_control_in\[33\]/one soc/mgmt_in_data[33]
++ gpio_control_in\[33\]/one padframe/mprj_io_analog_en[33] padframe/mprj_io_analog_pol[33]
++ padframe/mprj_io_analog_sel[33] padframe/mprj_io_dm[99] padframe/mprj_io_dm[100]
++ padframe/mprj_io_dm[101] padframe/mprj_io_holdover[33] padframe/mprj_io_ib_mode_sel[33]
++ padframe/mprj_io_in[33] padframe/mprj_io_inp_dis[33] padframe/mprj_io_out[33] padframe/mprj_io_oeb[33]
++ padframe/mprj_io_slow_sel[33] padframe/mprj_io_vtrip_sel[33] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[33\]/serial_data_in gpio_control_in\[34\]/serial_data_in
++ mprj/io_in[33] mprj/io_oeb[33] mprj/io_out[33] gpio_control_in\[33\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xsoc soc/clock soc/core_clk soc/core_rstn soc/flash_clk soc/flash_clk_ieb soc/flash_clk_oeb
++ soc/flash_csb soc/flash_csb_ieb soc/flash_csb_oeb soc/flash_io0_di soc/flash_io0_do
++ soc/flash_io0_ieb soc/flash_io0_oeb soc/flash_io1_di soc/flash_io1_do soc/flash_io1_ieb
++ soc/flash_io1_oeb soc/gpio_in_pad soc/gpio_inenb_pad soc/gpio_mode0_pad soc/gpio_mode1_pad
++ soc/gpio_out_pad soc/gpio_outenb_pad soc/jtag_out soc/jtag_outenb soc/la_input[0]
++ soc/la_input[100] soc/la_input[101] soc/la_input[102] soc/la_input[103] soc/la_input[104]
++ soc/la_input[105] soc/la_input[106] soc/la_input[107] soc/la_input[108] soc/la_input[109]
++ soc/la_input[10] soc/la_input[110] soc/la_input[111] soc/la_input[112] soc/la_input[113]
++ soc/la_input[114] soc/la_input[115] soc/la_input[116] soc/la_input[117] soc/la_input[118]
++ soc/la_input[119] soc/la_input[11] soc/la_input[120] soc/la_input[121] soc/la_input[122]
++ soc/la_input[123] soc/la_input[124] soc/la_input[125] soc/la_input[126] soc/la_input[127]
++ soc/la_input[12] soc/la_input[13] soc/la_input[14] soc/la_input[15] soc/la_input[16]
++ soc/la_input[17] soc/la_input[18] soc/la_input[19] soc/la_input[1] soc/la_input[20]
++ soc/la_input[21] soc/la_input[22] soc/la_input[23] soc/la_input[24] soc/la_input[25]
++ soc/la_input[26] soc/la_input[27] soc/la_input[28] soc/la_input[29] soc/la_input[2]
++ soc/la_input[30] soc/la_input[31] soc/la_input[32] soc/la_input[33] soc/la_input[34]
++ soc/la_input[35] soc/la_input[36] soc/la_input[37] soc/la_input[38] soc/la_input[39]
++ soc/la_input[3] soc/la_input[40] soc/la_input[41] soc/la_input[42] soc/la_input[43]
++ soc/la_input[44] soc/la_input[45] soc/la_input[46] soc/la_input[47] soc/la_input[48]
++ soc/la_input[49] soc/la_input[4] soc/la_input[50] soc/la_input[51] soc/la_input[52]
++ soc/la_input[53] soc/la_input[54] soc/la_input[55] soc/la_input[56] soc/la_input[57]
++ soc/la_input[58] soc/la_input[59] soc/la_input[5] soc/la_input[60] soc/la_input[61]
++ soc/la_input[62] soc/la_input[63] soc/la_input[64] soc/la_input[65] soc/la_input[66]
++ soc/la_input[67] soc/la_input[68] soc/la_input[69] soc/la_input[6] soc/la_input[70]
++ soc/la_input[71] soc/la_input[72] soc/la_input[73] soc/la_input[74] soc/la_input[75]
++ soc/la_input[76] soc/la_input[77] soc/la_input[78] soc/la_input[79] soc/la_input[7]
++ soc/la_input[80] soc/la_input[81] soc/la_input[82] soc/la_input[83] soc/la_input[84]
++ soc/la_input[85] soc/la_input[86] soc/la_input[87] soc/la_input[88] soc/la_input[89]
++ soc/la_input[8] soc/la_input[90] soc/la_input[91] soc/la_input[92] soc/la_input[93]
++ soc/la_input[94] soc/la_input[95] soc/la_input[96] soc/la_input[97] soc/la_input[98]
++ soc/la_input[99] soc/la_input[9] soc/la_oen[0] soc/la_oen[100] soc/la_oen[101] soc/la_oen[102]
++ soc/la_oen[103] soc/la_oen[104] soc/la_oen[105] soc/la_oen[106] soc/la_oen[107]
++ soc/la_oen[108] soc/la_oen[109] soc/la_oen[10] soc/la_oen[110] soc/la_oen[111] soc/la_oen[112]
++ soc/la_oen[113] soc/la_oen[114] soc/la_oen[115] soc/la_oen[116] soc/la_oen[117]
++ soc/la_oen[118] soc/la_oen[119] soc/la_oen[11] soc/la_oen[120] soc/la_oen[121] soc/la_oen[122]
++ soc/la_oen[123] soc/la_oen[124] soc/la_oen[125] soc/la_oen[126] soc/la_oen[127]
++ soc/la_oen[12] soc/la_oen[13] soc/la_oen[14] soc/la_oen[15] soc/la_oen[16] soc/la_oen[17]
++ soc/la_oen[18] soc/la_oen[19] soc/la_oen[1] soc/la_oen[20] soc/la_oen[21] soc/la_oen[22]
++ soc/la_oen[23] soc/la_oen[24] soc/la_oen[25] soc/la_oen[26] soc/la_oen[27] soc/la_oen[28]
++ soc/la_oen[29] soc/la_oen[2] soc/la_oen[30] soc/la_oen[31] soc/la_oen[32] soc/la_oen[33]
++ soc/la_oen[34] soc/la_oen[35] soc/la_oen[36] soc/la_oen[37] soc/la_oen[38] soc/la_oen[39]
++ soc/la_oen[3] soc/la_oen[40] soc/la_oen[41] soc/la_oen[42] soc/la_oen[43] soc/la_oen[44]
++ soc/la_oen[45] soc/la_oen[46] soc/la_oen[47] soc/la_oen[48] soc/la_oen[49] soc/la_oen[4]
++ soc/la_oen[50] soc/la_oen[51] soc/la_oen[52] soc/la_oen[53] soc/la_oen[54] soc/la_oen[55]
++ soc/la_oen[56] soc/la_oen[57] soc/la_oen[58] soc/la_oen[59] soc/la_oen[5] soc/la_oen[60]
++ soc/la_oen[61] soc/la_oen[62] soc/la_oen[63] soc/la_oen[64] soc/la_oen[65] soc/la_oen[66]
++ soc/la_oen[67] soc/la_oen[68] soc/la_oen[69] soc/la_oen[6] soc/la_oen[70] soc/la_oen[71]
++ soc/la_oen[72] soc/la_oen[73] soc/la_oen[74] soc/la_oen[75] soc/la_oen[76] soc/la_oen[77]
++ soc/la_oen[78] soc/la_oen[79] soc/la_oen[7] soc/la_oen[80] soc/la_oen[81] soc/la_oen[82]
++ soc/la_oen[83] soc/la_oen[84] soc/la_oen[85] soc/la_oen[86] soc/la_oen[87] soc/la_oen[88]
++ soc/la_oen[89] soc/la_oen[8] soc/la_oen[90] soc/la_oen[91] soc/la_oen[92] soc/la_oen[93]
++ soc/la_oen[94] soc/la_oen[95] soc/la_oen[96] soc/la_oen[97] soc/la_oen[98] soc/la_oen[99]
++ soc/la_oen[9] soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102]
++ soc/la_output[103] soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107]
++ soc/la_output[108] soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111]
++ soc/la_output[112] soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116]
++ soc/la_output[117] soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120]
++ soc/la_output[121] soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125]
++ soc/la_output[126] soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14]
++ soc/la_output[15] soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19]
++ soc/la_output[1] soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23]
++ soc/la_output[24] soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28]
++ soc/la_output[29] soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32]
++ soc/la_output[33] soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37]
++ soc/la_output[38] soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41]
++ soc/la_output[42] soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46]
++ soc/la_output[47] soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50]
++ soc/la_output[51] soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55]
++ soc/la_output[56] soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5]
++ soc/la_output[60] soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64]
++ soc/la_output[65] soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69]
++ soc/la_output[6] soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73]
++ soc/la_output[74] soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78]
++ soc/la_output[79] soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82]
++ soc/la_output[83] soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87]
++ soc/la_output[88] soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91]
++ soc/la_output[92] soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96]
++ soc/la_output[97] soc/la_output[98] soc/la_output[99] soc/la_output[9] soc/mask_rev[0]
++ soc/mask_rev[10] soc/mask_rev[11] soc/mask_rev[12] soc/mask_rev[13] soc/mask_rev[14]
++ soc/mask_rev[15] soc/mask_rev[16] soc/mask_rev[17] soc/mask_rev[18] soc/mask_rev[19]
++ soc/mask_rev[1] soc/mask_rev[20] soc/mask_rev[21] soc/mask_rev[22] soc/mask_rev[23]
++ soc/mask_rev[24] soc/mask_rev[25] soc/mask_rev[26] soc/mask_rev[27] soc/mask_rev[28]
++ soc/mask_rev[29] soc/mask_rev[2] soc/mask_rev[30] soc/mask_rev[31] soc/mask_rev[3]
++ soc/mask_rev[4] soc/mask_rev[5] soc/mask_rev[6] soc/mask_rev[7] soc/mask_rev[8]
++ soc/mask_rev[9] soc/mgmt_addr[0] soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3]
++ soc/mgmt_addr[4] soc/mgmt_addr[5] soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0]
++ soc/mgmt_addr_ro[1] soc/mgmt_addr_ro[2] soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4]
++ soc/mgmt_addr_ro[5] soc/mgmt_addr_ro[6] soc/mgmt_addr_ro[7] soc/mgmt_ena[0] soc/mgmt_ena[1]
++ soc/mgmt_ena_ro soc/mgmt_in_data[0] soc/mgmt_in_data[10] soc/mgmt_in_data[11] soc/mgmt_in_data[12]
++ soc/mgmt_in_data[13] soc/mgmt_in_data[14] soc/mgmt_in_data[15] soc/mgmt_in_data[16]
++ soc/mgmt_in_data[17] soc/mgmt_in_data[18] soc/mgmt_in_data[19] soc/mgmt_in_data[1]
++ soc/mgmt_in_data[20] soc/mgmt_in_data[21] soc/mgmt_in_data[22] soc/mgmt_in_data[23]
++ soc/mgmt_in_data[24] soc/mgmt_in_data[25] soc/mgmt_in_data[26] soc/mgmt_in_data[27]
++ soc/mgmt_in_data[28] soc/mgmt_in_data[29] soc/mgmt_in_data[2] soc/mgmt_in_data[30]
++ soc/mgmt_in_data[31] soc/mgmt_in_data[32] soc/mgmt_in_data[33] soc/mgmt_in_data[34]
++ soc/mgmt_in_data[35] soc/mgmt_in_data[36] soc/mgmt_in_data[37] soc/mgmt_in_data[3]
++ soc/mgmt_in_data[4] soc/mgmt_in_data[5] soc/mgmt_in_data[6] soc/mgmt_in_data[7]
++ soc/mgmt_in_data[8] soc/mgmt_in_data[9] soc/mgmt_out_data[0] soc/mgmt_in_data[10]
++ soc/mgmt_in_data[11] soc/mgmt_in_data[12] soc/mgmt_in_data[13] soc/mgmt_in_data[14]
++ soc/mgmt_in_data[15] soc/mgmt_in_data[16] soc/mgmt_in_data[17] soc/mgmt_in_data[18]
++ soc/mgmt_in_data[19] soc/mgmt_out_data[1] soc/mgmt_in_data[20] soc/mgmt_in_data[21]
++ soc/mgmt_in_data[22] soc/mgmt_in_data[23] soc/mgmt_in_data[24] soc/mgmt_in_data[25]
++ soc/mgmt_in_data[26] soc/mgmt_in_data[27] soc/mgmt_in_data[28] soc/mgmt_in_data[29]
++ soc/mgmt_in_data[2] soc/mgmt_in_data[30] soc/mgmt_in_data[31] soc/mgmt_in_data[32]
++ soc/mgmt_in_data[33] soc/mgmt_in_data[34] soc/mgmt_in_data[35] soc/mgmt_in_data[36]
++ soc/mgmt_in_data[37] soc/mgmt_in_data[3] soc/mgmt_in_data[4] soc/mgmt_in_data[5]
++ soc/mgmt_in_data[6] soc/mgmt_in_data[7] soc/mgmt_in_data[8] soc/mgmt_in_data[9]
++ soc/mgmt_rdata[0] soc/mgmt_rdata[10] soc/mgmt_rdata[11] soc/mgmt_rdata[12] soc/mgmt_rdata[13]
++ soc/mgmt_rdata[14] soc/mgmt_rdata[15] soc/mgmt_rdata[16] soc/mgmt_rdata[17] soc/mgmt_rdata[18]
++ soc/mgmt_rdata[19] soc/mgmt_rdata[1] soc/mgmt_rdata[20] soc/mgmt_rdata[21] soc/mgmt_rdata[22]
++ soc/mgmt_rdata[23] soc/mgmt_rdata[24] soc/mgmt_rdata[25] soc/mgmt_rdata[26] soc/mgmt_rdata[27]
++ soc/mgmt_rdata[28] soc/mgmt_rdata[29] soc/mgmt_rdata[2] soc/mgmt_rdata[30] soc/mgmt_rdata[31]
++ soc/mgmt_rdata[32] soc/mgmt_rdata[33] soc/mgmt_rdata[34] soc/mgmt_rdata[35] soc/mgmt_rdata[36]
++ soc/mgmt_rdata[37] soc/mgmt_rdata[38] soc/mgmt_rdata[39] soc/mgmt_rdata[3] soc/mgmt_rdata[40]
++ soc/mgmt_rdata[41] soc/mgmt_rdata[42] soc/mgmt_rdata[43] soc/mgmt_rdata[44] soc/mgmt_rdata[45]
++ soc/mgmt_rdata[46] soc/mgmt_rdata[47] soc/mgmt_rdata[48] soc/mgmt_rdata[49] soc/mgmt_rdata[4]
++ soc/mgmt_rdata[50] soc/mgmt_rdata[51] soc/mgmt_rdata[52] soc/mgmt_rdata[53] soc/mgmt_rdata[54]
++ soc/mgmt_rdata[55] soc/mgmt_rdata[56] soc/mgmt_rdata[57] soc/mgmt_rdata[58] soc/mgmt_rdata[59]
++ soc/mgmt_rdata[5] soc/mgmt_rdata[60] soc/mgmt_rdata[61] soc/mgmt_rdata[62] soc/mgmt_rdata[63]
++ soc/mgmt_rdata[6] soc/mgmt_rdata[7] soc/mgmt_rdata[8] soc/mgmt_rdata[9] soc/mgmt_rdata_ro[0]
++ soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11] soc/mgmt_rdata_ro[12] soc/mgmt_rdata_ro[13]
++ soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15] soc/mgmt_rdata_ro[16] soc/mgmt_rdata_ro[17]
++ soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19] soc/mgmt_rdata_ro[1] soc/mgmt_rdata_ro[20]
++ soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22] soc/mgmt_rdata_ro[23] soc/mgmt_rdata_ro[24]
++ soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26] soc/mgmt_rdata_ro[27] soc/mgmt_rdata_ro[28]
++ soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2] soc/mgmt_rdata_ro[30] soc/mgmt_rdata_ro[31]
++ soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4] soc/mgmt_rdata_ro[5] soc/mgmt_rdata_ro[6]
++ soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8] soc/mgmt_rdata_ro[9] soc/mgmt_wdata[0]
++ soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12] soc/mgmt_wdata[13] soc/mgmt_wdata[14]
++ soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17] soc/mgmt_wdata[18] soc/mgmt_wdata[19]
++ soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21] soc/mgmt_wdata[22] soc/mgmt_wdata[23]
++ soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26] soc/mgmt_wdata[27] soc/mgmt_wdata[28]
++ soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30] soc/mgmt_wdata[31] soc/mgmt_wdata[3]
++ soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6] soc/mgmt_wdata[7] soc/mgmt_wdata[8]
++ soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1] soc/mgmt_wen_mask[0] soc/mgmt_wen_mask[1]
++ soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3] soc/mgmt_wen_mask[4] soc/mgmt_wen_mask[5]
++ soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7] soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood
++ soc/mprj_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11] soc/mprj_adr_o[12]
++ soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16] soc/mprj_adr_o[17]
++ soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20] soc/mprj_adr_o[21]
++ soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25] soc/mprj_adr_o[26]
++ soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2] soc/mprj_adr_o[30]
++ soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5] soc/mprj_adr_o[6]
++ soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] soc/mprj_cyc_o soc/mprj_dat_i[0]
++ soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12] soc/mprj_dat_i[13] soc/mprj_dat_i[14]
++ soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17] soc/mprj_dat_i[18] soc/mprj_dat_i[19]
++ soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21] soc/mprj_dat_i[22] soc/mprj_dat_i[23]
++ soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26] soc/mprj_dat_i[27] soc/mprj_dat_i[28]
++ soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30] soc/mprj_dat_i[31] soc/mprj_dat_i[3]
++ soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6] soc/mprj_dat_i[7] soc/mprj_dat_i[8]
++ soc/mprj_dat_i[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10] soc/mprj_dat_o[11] soc/mprj_dat_o[12]
++ soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15] soc/mprj_dat_o[16] soc/mprj_dat_o[17]
++ soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1] soc/mprj_dat_o[20] soc/mprj_dat_o[21]
++ soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24] soc/mprj_dat_o[25] soc/mprj_dat_o[26]
++ soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29] soc/mprj_dat_o[2] soc/mprj_dat_o[30]
++ soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4] soc/mprj_dat_o[5] soc/mprj_dat_o[6]
++ soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9] soc/mprj_io_loader_clock soc/mprj_io_loader_data
++ soc/mprj_io_loader_resetn soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2]
++ soc/mprj_sel_o[3] soc/mprj_stb_o soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood soc/mprj_we_o
++ soc/porb pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] soc/resetb
++ soc/sdo_out soc/sdo_outenb soc/user_clk vccd vssd mgmt_core
+Xgpio_control_in\[19\] soc/mgmt_in_data[19] gpio_control_in\[19\]/one soc/mgmt_in_data[19]
++ gpio_control_in\[19\]/one padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19]
++ padframe/mprj_io_analog_sel[19] padframe/mprj_io_dm[57] padframe/mprj_io_dm[58]
++ padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19] padframe/mprj_io_ib_mode_sel[19]
++ padframe/mprj_io_in[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_out[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[19\]/serial_data_in gpio_control_in\[20\]/serial_data_in
++ mprj/io_in[19] mprj/io_oeb[19] mprj/io_out[19] gpio_control_in\[19\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xuser_id_textblock_0 VSUBS user_id_textblock
+Xgpio_control_in\[31\] soc/mgmt_in_data[31] gpio_control_in\[31\]/one soc/mgmt_in_data[31]
++ gpio_control_in\[31\]/one padframe/mprj_io_analog_en[31] padframe/mprj_io_analog_pol[31]
++ padframe/mprj_io_analog_sel[31] padframe/mprj_io_dm[93] padframe/mprj_io_dm[94]
++ padframe/mprj_io_dm[95] padframe/mprj_io_holdover[31] padframe/mprj_io_ib_mode_sel[31]
++ padframe/mprj_io_in[31] padframe/mprj_io_inp_dis[31] padframe/mprj_io_out[31] padframe/mprj_io_oeb[31]
++ padframe/mprj_io_slow_sel[31] padframe/mprj_io_vtrip_sel[31] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[31\]/serial_data_in gpio_control_in\[32\]/serial_data_in
++ mprj/io_in[31] mprj/io_oeb[31] mprj/io_out[31] gpio_control_in\[31\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xpor vddio vccd vssio por/porb_h por/por_l soc/porb simple_por
+Xgpio_control_in\[24\] soc/mgmt_in_data[24] gpio_control_in\[24\]/one soc/mgmt_in_data[24]
++ gpio_control_in\[24\]/one padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24]
++ padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72] padframe/mprj_io_dm[73]
++ padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24] padframe/mprj_io_ib_mode_sel[24]
++ padframe/mprj_io_in[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_out[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[24\]/serial_data_in gpio_control_in\[25\]/serial_data_in
++ mprj/io_in[24] mprj/io_oeb[24] mprj/io_out[24] gpio_control_in\[24\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_bidir\[1\] soc/mgmt_in_data[1] soc/sdo_outenb soc/sdo_out gpio_control_bidir\[1\]/one
++ padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1]
++ padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1]
++ padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_in[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_out[1] padframe/mprj_io_oeb[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ soc/mprj_io_loader_resetn soc/mprj_io_loader_clock gpio_control_bidir\[1\]/serial_data_in
++ gpio_control_in\[2\]/serial_data_in mprj/io_in[1] mprj/io_oeb[1] mprj/io_out[1]
++ gpio_control_bidir\[1\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[17\] soc/mgmt_in_data[17] gpio_control_in\[17\]/one soc/mgmt_in_data[17]
++ gpio_control_in\[17\]/one padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17]
++ padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51] padframe/mprj_io_dm[52]
++ padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17] padframe/mprj_io_ib_mode_sel[17]
++ padframe/mprj_io_in[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_out[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[17\]/serial_data_in gpio_control_in\[18\]/serial_data_in
++ mprj/io_in[17] mprj/io_oeb[17] mprj/io_out[17] gpio_control_in\[17\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[22\] soc/mgmt_in_data[22] gpio_control_in\[22\]/one soc/mgmt_in_data[22]
++ gpio_control_in\[22\]/one padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22]
++ padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66] padframe/mprj_io_dm[67]
++ padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22] padframe/mprj_io_ib_mode_sel[22]
++ padframe/mprj_io_in[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_out[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[22\]/serial_data_in gpio_control_in\[23\]/serial_data_in
++ mprj/io_in[22] mprj/io_oeb[22] mprj/io_out[22] gpio_control_in\[22\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[8\] soc/mgmt_in_data[8] gpio_control_in\[8\]/one soc/mgmt_in_data[8]
++ gpio_control_in\[8\]/one padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8]
++ padframe/mprj_io_analog_sel[8] padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26]
++ padframe/mprj_io_holdover[8] padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_in[8]
++ padframe/mprj_io_inp_dis[8] padframe/mprj_io_out[8] padframe/mprj_io_oeb[8] padframe/mprj_io_slow_sel[8]
++ padframe/mprj_io_vtrip_sel[8] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[8\]/serial_data_in gpio_control_in\[9\]/serial_data_in mprj/io_in[8]
++ mprj/io_oeb[8] mprj/io_out[8] gpio_control_in\[8\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[15\] soc/mgmt_in_data[15] gpio_control_in\[15\]/one soc/mgmt_in_data[15]
++ gpio_control_in\[15\]/one padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15]
++ padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45] padframe/mprj_io_dm[46]
++ padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15] padframe/mprj_io_ib_mode_sel[15]
++ padframe/mprj_io_in[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_out[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[15\]/serial_data_in gpio_control_in\[16\]/serial_data_in
++ mprj/io_in[15] mprj/io_oeb[15] mprj/io_out[15] gpio_control_in\[15\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xuser_id_value soc/mask_rev[0] soc/mask_rev[10] soc/mask_rev[11] soc/mask_rev[12]
++ soc/mask_rev[13] soc/mask_rev[14] soc/mask_rev[15] soc/mask_rev[16] soc/mask_rev[17]
++ soc/mask_rev[18] soc/mask_rev[19] soc/mask_rev[1] soc/mask_rev[20] soc/mask_rev[21]
++ soc/mask_rev[22] soc/mask_rev[23] soc/mask_rev[24] soc/mask_rev[25] soc/mask_rev[26]
++ soc/mask_rev[27] soc/mask_rev[28] soc/mask_rev[29] soc/mask_rev[2] soc/mask_rev[30]
++ soc/mask_rev[31] soc/mask_rev[3] soc/mask_rev[4] soc/mask_rev[5] soc/mask_rev[6]
++ soc/mask_rev[7] soc/mask_rev[8] soc/mask_rev[9] vccd vssd user_id_programming
+Xgpio_control_in\[20\] soc/mgmt_in_data[20] gpio_control_in\[20\]/one soc/mgmt_in_data[20]
++ gpio_control_in\[20\]/one padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20]
++ padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60] padframe/mprj_io_dm[61]
++ padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20] padframe/mprj_io_ib_mode_sel[20]
++ padframe/mprj_io_in[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_out[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[20\]/serial_data_in gpio_control_in\[21\]/serial_data_in
++ mprj/io_in[20] mprj/io_oeb[20] mprj/io_out[20] gpio_control_in\[20\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[6\] soc/mgmt_in_data[6] gpio_control_in\[6\]/one soc/mgmt_in_data[6]
++ gpio_control_in\[6\]/one padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_in[6]
++ padframe/mprj_io_inp_dis[6] padframe/mprj_io_out[6] padframe/mprj_io_oeb[6] padframe/mprj_io_slow_sel[6]
++ padframe/mprj_io_vtrip_sel[6] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[6\]/serial_data_in gpio_control_in\[7\]/serial_data_in mprj/io_in[6]
++ mprj/io_oeb[6] mprj/io_out[6] gpio_control_in\[6\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[13\] soc/mgmt_in_data[13] gpio_control_in\[13\]/one soc/mgmt_in_data[13]
++ gpio_control_in\[13\]/one padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13]
++ padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39] padframe/mprj_io_dm[40]
++ padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_in[13] padframe/mprj_io_inp_dis[13] padframe/mprj_io_out[13] padframe/mprj_io_oeb[13]
++ padframe/mprj_io_slow_sel[13] padframe/mprj_io_vtrip_sel[13] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[13\]/serial_data_in gpio_control_in\[14\]/serial_data_in
++ mprj/io_in[13] mprj/io_oeb[13] mprj/io_out[13] gpio_control_in\[13\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xopen_source_0 VSUBS open_source
+Xgpio_control_in\[36\] soc/mgmt_in_data[36] gpio_control_in\[36\]/one soc/mgmt_in_data[36]
++ gpio_control_in\[36\]/one padframe/mprj_io_analog_en[36] padframe/mprj_io_analog_pol[36]
++ padframe/mprj_io_analog_sel[36] padframe/mprj_io_dm[108] padframe/mprj_io_dm[109]
++ padframe/mprj_io_dm[110] padframe/mprj_io_holdover[36] padframe/mprj_io_ib_mode_sel[36]
++ padframe/mprj_io_in[36] padframe/mprj_io_inp_dis[36] padframe/mprj_io_out[36] padframe/mprj_io_oeb[36]
++ padframe/mprj_io_slow_sel[36] padframe/mprj_io_vtrip_sel[36] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[36\]/serial_data_in gpio_control_in\[37\]/serial_data_in
++ mprj/io_in[36] mprj/io_oeb[36] mprj/io_out[36] gpio_control_in\[36\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[29\] soc/mgmt_in_data[29] gpio_control_in\[29\]/one soc/mgmt_in_data[29]
++ gpio_control_in\[29\]/one padframe/mprj_io_analog_en[29] padframe/mprj_io_analog_pol[29]
++ padframe/mprj_io_analog_sel[29] padframe/mprj_io_dm[87] padframe/mprj_io_dm[88]
++ padframe/mprj_io_dm[89] padframe/mprj_io_holdover[29] padframe/mprj_io_ib_mode_sel[29]
++ padframe/mprj_io_in[29] padframe/mprj_io_inp_dis[29] padframe/mprj_io_out[29] padframe/mprj_io_oeb[29]
++ padframe/mprj_io_slow_sel[29] padframe/mprj_io_vtrip_sel[29] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[29\]/serial_data_in gpio_control_in\[30\]/serial_data_in
++ mprj/io_in[29] mprj/io_oeb[29] mprj/io_out[29] gpio_control_in\[29\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[4\] soc/mgmt_in_data[4] gpio_control_in\[4\]/one soc/mgmt_in_data[4]
++ gpio_control_in\[4\]/one padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_in[4]
++ padframe/mprj_io_inp_dis[4] padframe/mprj_io_out[4] padframe/mprj_io_oeb[4] padframe/mprj_io_slow_sel[4]
++ padframe/mprj_io_vtrip_sel[4] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[4\]/serial_data_in gpio_control_in\[5\]/serial_data_in mprj/io_in[4]
++ mprj/io_oeb[4] mprj/io_out[4] gpio_control_in\[4\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[11\] soc/mgmt_in_data[11] gpio_control_in\[11\]/one soc/mgmt_in_data[11]
++ gpio_control_in\[11\]/one padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11]
++ padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33] padframe/mprj_io_dm[34]
++ padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_in[11] padframe/mprj_io_inp_dis[11] padframe/mprj_io_out[11] padframe/mprj_io_oeb[11]
++ padframe/mprj_io_slow_sel[11] padframe/mprj_io_vtrip_sel[11] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[11\]/serial_data_in gpio_control_in\[12\]/serial_data_in
++ mprj/io_in[11] mprj/io_oeb[11] mprj/io_out[11] gpio_control_in\[11\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[34\] soc/mgmt_in_data[34] gpio_control_in\[34\]/one soc/mgmt_in_data[34]
++ gpio_control_in\[34\]/one padframe/mprj_io_analog_en[34] padframe/mprj_io_analog_pol[34]
++ padframe/mprj_io_analog_sel[34] padframe/mprj_io_dm[102] padframe/mprj_io_dm[103]
++ padframe/mprj_io_dm[104] padframe/mprj_io_holdover[34] padframe/mprj_io_ib_mode_sel[34]
++ padframe/mprj_io_in[34] padframe/mprj_io_inp_dis[34] padframe/mprj_io_out[34] padframe/mprj_io_oeb[34]
++ padframe/mprj_io_slow_sel[34] padframe/mprj_io_vtrip_sel[34] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[34\]/serial_data_in gpio_control_in\[35\]/serial_data_in
++ mprj/io_in[34] mprj/io_oeb[34] mprj/io_out[34] gpio_control_in\[34\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xmgmt_buffers soc/core_clk soc/user_clk soc/core_rstn mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102]
++ mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106]
++ mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10]
++ mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113]
++ mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117]
++ mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120]
++ mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124]
++ mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12]
++ mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16]
++ mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1]
++ mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23]
++ mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27]
++ mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30]
++ mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34]
++ mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38]
++ mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41]
++ mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45]
++ mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49]
++ mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52]
++ mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56]
++ mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5]
++ mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63]
++ mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67]
++ mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70]
++ mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74]
++ mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78]
++ mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81]
++ mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85]
++ mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89]
++ mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92]
++ mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96]
++ mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9]
++ soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103]
++ soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108]
++ soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112]
++ soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117]
++ soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121]
++ soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126]
++ soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15]
++ soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1]
++ soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24]
++ soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29]
++ soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33]
++ soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38]
++ soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42]
++ soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47]
++ soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51]
++ soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56]
++ soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60]
++ soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65]
++ soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6]
++ soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74]
++ soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79]
++ soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83]
++ soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88]
++ soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92]
++ soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97]
++ soc/la_output[98] soc/la_output[99] soc/la_output[9] mprj/la_oen[0] mprj/la_oen[100]
++ mprj/la_oen[101] mprj/la_oen[102] mprj/la_oen[103] mprj/la_oen[104] mprj/la_oen[105]
++ mprj/la_oen[106] mprj/la_oen[107] mprj/la_oen[108] mprj/la_oen[109] mprj/la_oen[10]
++ mprj/la_oen[110] mprj/la_oen[111] mprj/la_oen[112] mprj/la_oen[113] mprj/la_oen[114]
++ mprj/la_oen[115] mprj/la_oen[116] mprj/la_oen[117] mprj/la_oen[118] mprj/la_oen[119]
++ mprj/la_oen[11] mprj/la_oen[120] mprj/la_oen[121] mprj/la_oen[122] mprj/la_oen[123]
++ mprj/la_oen[124] mprj/la_oen[125] mprj/la_oen[126] mprj/la_oen[127] mprj/la_oen[12]
++ mprj/la_oen[13] mprj/la_oen[14] mprj/la_oen[15] mprj/la_oen[16] mprj/la_oen[17]
++ mprj/la_oen[18] mprj/la_oen[19] mprj/la_oen[1] mprj/la_oen[20] mprj/la_oen[21] mprj/la_oen[22]
++ mprj/la_oen[23] mprj/la_oen[24] mprj/la_oen[25] mprj/la_oen[26] mprj/la_oen[27]
++ mprj/la_oen[28] mprj/la_oen[29] mprj/la_oen[2] mprj/la_oen[30] mprj/la_oen[31] mprj/la_oen[32]
++ mprj/la_oen[33] mprj/la_oen[34] mprj/la_oen[35] mprj/la_oen[36] mprj/la_oen[37]
++ mprj/la_oen[38] mprj/la_oen[39] mprj/la_oen[3] mprj/la_oen[40] mprj/la_oen[41] mprj/la_oen[42]
++ mprj/la_oen[43] mprj/la_oen[44] mprj/la_oen[45] mprj/la_oen[46] mprj/la_oen[47]
++ mprj/la_oen[48] mprj/la_oen[49] mprj/la_oen[4] mprj/la_oen[50] mprj/la_oen[51] mprj/la_oen[52]
++ mprj/la_oen[53] mprj/la_oen[54] mprj/la_oen[55] mprj/la_oen[56] mprj/la_oen[57]
++ mprj/la_oen[58] mprj/la_oen[59] mprj/la_oen[5] mprj/la_oen[60] mprj/la_oen[61] mprj/la_oen[62]
++ mprj/la_oen[63] mprj/la_oen[64] mprj/la_oen[65] mprj/la_oen[66] mprj/la_oen[67]
++ mprj/la_oen[68] mprj/la_oen[69] mprj/la_oen[6] mprj/la_oen[70] mprj/la_oen[71] mprj/la_oen[72]
++ mprj/la_oen[73] mprj/la_oen[74] mprj/la_oen[75] mprj/la_oen[76] mprj/la_oen[77]
++ mprj/la_oen[78] mprj/la_oen[79] mprj/la_oen[7] mprj/la_oen[80] mprj/la_oen[81] mprj/la_oen[82]
++ mprj/la_oen[83] mprj/la_oen[84] mprj/la_oen[85] mprj/la_oen[86] mprj/la_oen[87]
++ mprj/la_oen[88] mprj/la_oen[89] mprj/la_oen[8] mprj/la_oen[90] mprj/la_oen[91] mprj/la_oen[92]
++ mprj/la_oen[93] mprj/la_oen[94] mprj/la_oen[95] mprj/la_oen[96] mprj/la_oen[97]
++ mprj/la_oen[98] mprj/la_oen[99] mprj/la_oen[9] soc/la_oen[0] soc/la_oen[100] soc/la_oen[101]
++ soc/la_oen[102] soc/la_oen[103] soc/la_oen[104] soc/la_oen[105] soc/la_oen[106]
++ soc/la_oen[107] soc/la_oen[108] soc/la_oen[109] soc/la_oen[10] soc/la_oen[110] soc/la_oen[111]
++ soc/la_oen[112] soc/la_oen[113] soc/la_oen[114] soc/la_oen[115] soc/la_oen[116]
++ soc/la_oen[117] soc/la_oen[118] soc/la_oen[119] soc/la_oen[11] soc/la_oen[120] soc/la_oen[121]
++ soc/la_oen[122] soc/la_oen[123] soc/la_oen[124] soc/la_oen[125] soc/la_oen[126]
++ soc/la_oen[127] soc/la_oen[12] soc/la_oen[13] soc/la_oen[14] soc/la_oen[15] soc/la_oen[16]
++ soc/la_oen[17] soc/la_oen[18] soc/la_oen[19] soc/la_oen[1] soc/la_oen[20] soc/la_oen[21]
++ soc/la_oen[22] soc/la_oen[23] soc/la_oen[24] soc/la_oen[25] soc/la_oen[26] soc/la_oen[27]
++ soc/la_oen[28] soc/la_oen[29] soc/la_oen[2] soc/la_oen[30] soc/la_oen[31] soc/la_oen[32]
++ soc/la_oen[33] soc/la_oen[34] soc/la_oen[35] soc/la_oen[36] soc/la_oen[37] soc/la_oen[38]
++ soc/la_oen[39] soc/la_oen[3] soc/la_oen[40] soc/la_oen[41] soc/la_oen[42] soc/la_oen[43]
++ soc/la_oen[44] soc/la_oen[45] soc/la_oen[46] soc/la_oen[47] soc/la_oen[48] soc/la_oen[49]
++ soc/la_oen[4] soc/la_oen[50] soc/la_oen[51] soc/la_oen[52] soc/la_oen[53] soc/la_oen[54]
++ soc/la_oen[55] soc/la_oen[56] soc/la_oen[57] soc/la_oen[58] soc/la_oen[59] soc/la_oen[5]
++ soc/la_oen[60] soc/la_oen[61] soc/la_oen[62] soc/la_oen[63] soc/la_oen[64] soc/la_oen[65]
++ soc/la_oen[66] soc/la_oen[67] soc/la_oen[68] soc/la_oen[69] soc/la_oen[6] soc/la_oen[70]
++ soc/la_oen[71] soc/la_oen[72] soc/la_oen[73] soc/la_oen[74] soc/la_oen[75] soc/la_oen[76]
++ soc/la_oen[77] soc/la_oen[78] soc/la_oen[79] soc/la_oen[7] soc/la_oen[80] soc/la_oen[81]
++ soc/la_oen[82] soc/la_oen[83] soc/la_oen[84] soc/la_oen[85] soc/la_oen[86] soc/la_oen[87]
++ soc/la_oen[88] soc/la_oen[89] soc/la_oen[8] soc/la_oen[90] soc/la_oen[91] soc/la_oen[92]
++ soc/la_oen[93] soc/la_oen[94] soc/la_oen[95] soc/la_oen[96] soc/la_oen[97] soc/la_oen[98]
++ soc/la_oen[99] soc/la_oen[9] soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11]
++ soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16]
++ soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20]
++ soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25]
++ soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2]
++ soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5]
++ soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] mprj/wbs_adr_i[0]
++ mprj/wbs_adr_i[10] mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14]
++ mprj/wbs_adr_i[15] mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19]
++ mprj/wbs_adr_i[1] mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23]
++ mprj/wbs_adr_i[24] mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28]
++ mprj/wbs_adr_i[29] mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3]
++ mprj/wbs_adr_i[4] mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8]
++ mprj/wbs_adr_i[9] soc/mprj_cyc_o mprj/wbs_cyc_i soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2]
++ soc/mprj_sel_o[3] mprj/wbs_sel_i[0] mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3]
++ soc/mprj_stb_o mprj/wbs_stb_i soc/mprj_we_o mprj/wbs_we_i soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood
++ soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood mprj/wb_clk_i mprj/user_clock2 mprj/wb_rst_i
++ mgmt_buffers/user_resetn vccd vssd vccd1 vssd1 vccd2 vssd2 vdda1 vssa1 vdda2 vssa2
++ mgmt_protect
+Xrstb_level rstb_level/A soc/resetb vddio vssio vccd rstb_level/LVGND sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Xgpio_control_in\[27\] soc/mgmt_in_data[27] gpio_control_in\[27\]/one soc/mgmt_in_data[27]
++ gpio_control_in\[27\]/one padframe/mprj_io_analog_en[27] padframe/mprj_io_analog_pol[27]
++ padframe/mprj_io_analog_sel[27] padframe/mprj_io_dm[81] padframe/mprj_io_dm[82]
++ padframe/mprj_io_dm[83] padframe/mprj_io_holdover[27] padframe/mprj_io_ib_mode_sel[27]
++ padframe/mprj_io_in[27] padframe/mprj_io_inp_dis[27] padframe/mprj_io_out[27] padframe/mprj_io_oeb[27]
++ padframe/mprj_io_slow_sel[27] padframe/mprj_io_vtrip_sel[27] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[27\]/serial_data_in gpio_control_in\[28\]/serial_data_in
++ mprj/io_in[27] mprj/io_oeb[27] mprj/io_out[27] gpio_control_in\[27\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[2\] soc/mgmt_in_data[2] gpio_control_in\[2\]/one soc/mgmt_in_data[2]
++ gpio_control_in\[2\]/one padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_in[2]
++ padframe/mprj_io_inp_dis[2] padframe/mprj_io_out[2] padframe/mprj_io_oeb[2] padframe/mprj_io_slow_sel[2]
++ padframe/mprj_io_vtrip_sel[2] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[2\]/serial_data_in gpio_control_in\[3\]/serial_data_in mprj/io_in[2]
++ mprj/io_oeb[2] mprj/io_out[2] gpio_control_in\[2\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[32\] soc/mgmt_in_data[32] gpio_control_in\[32\]/one soc/mgmt_in_data[32]
++ gpio_control_in\[32\]/one padframe/mprj_io_analog_en[32] padframe/mprj_io_analog_pol[32]
++ padframe/mprj_io_analog_sel[32] padframe/mprj_io_dm[96] padframe/mprj_io_dm[97]
++ padframe/mprj_io_dm[98] padframe/mprj_io_holdover[32] padframe/mprj_io_ib_mode_sel[32]
++ padframe/mprj_io_in[32] padframe/mprj_io_inp_dis[32] padframe/mprj_io_out[32] padframe/mprj_io_oeb[32]
++ padframe/mprj_io_slow_sel[32] padframe/mprj_io_vtrip_sel[32] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[32\]/serial_data_in gpio_control_in\[33\]/serial_data_in
++ mprj/io_in[32] mprj/io_oeb[32] mprj/io_out[32] gpio_control_in\[32\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[25\] soc/mgmt_in_data[25] gpio_control_in\[25\]/one soc/mgmt_in_data[25]
++ gpio_control_in\[25\]/one padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25]
++ padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75] padframe/mprj_io_dm[76]
++ padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25] padframe/mprj_io_ib_mode_sel[25]
++ padframe/mprj_io_in[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_out[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[25\]/serial_data_in gpio_control_in\[26\]/serial_data_in
++ mprj/io_in[25] mprj/io_oeb[25] mprj/io_out[25] gpio_control_in\[25\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[18\] soc/mgmt_in_data[18] gpio_control_in\[18\]/one soc/mgmt_in_data[18]
++ gpio_control_in\[18\]/one padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18]
++ padframe/mprj_io_analog_sel[18] padframe/mprj_io_dm[54] padframe/mprj_io_dm[55]
++ padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18] padframe/mprj_io_ib_mode_sel[18]
++ padframe/mprj_io_in[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_out[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[18\]/serial_data_in gpio_control_in\[19\]/serial_data_in
++ mprj/io_in[18] mprj/io_oeb[18] mprj/io_out[18] gpio_control_in\[18\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[30\] soc/mgmt_in_data[30] gpio_control_in\[30\]/one soc/mgmt_in_data[30]
++ gpio_control_in\[30\]/one padframe/mprj_io_analog_en[30] padframe/mprj_io_analog_pol[30]
++ padframe/mprj_io_analog_sel[30] padframe/mprj_io_dm[90] padframe/mprj_io_dm[91]
++ padframe/mprj_io_dm[92] padframe/mprj_io_holdover[30] padframe/mprj_io_ib_mode_sel[30]
++ padframe/mprj_io_in[30] padframe/mprj_io_inp_dis[30] padframe/mprj_io_out[30] padframe/mprj_io_oeb[30]
++ padframe/mprj_io_slow_sel[30] padframe/mprj_io_vtrip_sel[30] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[30\]/serial_data_in gpio_control_in\[31\]/serial_data_in
++ mprj/io_in[30] mprj/io_oeb[30] mprj/io_out[30] gpio_control_in\[30\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[23\] soc/mgmt_in_data[23] gpio_control_in\[23\]/one soc/mgmt_in_data[23]
++ gpio_control_in\[23\]/one padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23]
++ padframe/mprj_io_analog_sel[23] padframe/mprj_io_dm[69] padframe/mprj_io_dm[70]
++ padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23] padframe/mprj_io_ib_mode_sel[23]
++ padframe/mprj_io_in[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_out[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[23\]/serial_data_in gpio_control_in\[24\]/serial_data_in
++ mprj/io_in[23] mprj/io_oeb[23] mprj/io_out[23] gpio_control_in\[23\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[9\] soc/mgmt_in_data[9] gpio_control_in\[9\]/one soc/mgmt_in_data[9]
++ gpio_control_in\[9\]/one padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9]
++ padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29]
++ padframe/mprj_io_holdover[9] padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_in[9]
++ padframe/mprj_io_inp_dis[9] padframe/mprj_io_out[9] padframe/mprj_io_oeb[9] padframe/mprj_io_slow_sel[9]
++ padframe/mprj_io_vtrip_sel[9] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[9\]/serial_data_in gpio_control_in\[9\]/serial_data_out mprj/io_in[9]
++ mprj/io_oeb[9] mprj/io_out[9] gpio_control_in\[9\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_bidir\[0\] soc/mgmt_in_data[0] soc/jtag_outenb soc/jtag_out gpio_control_bidir\[0\]/one
++ padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0]
++ padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0]
++ padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_in[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_out[0] padframe/mprj_io_oeb[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ soc/mprj_io_loader_resetn soc/mprj_io_loader_clock soc/mprj_io_loader_data gpio_control_bidir\[1\]/serial_data_in
++ mprj/io_in[0] mprj/io_oeb[0] mprj/io_out[0] gpio_control_bidir\[0\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[16\] soc/mgmt_in_data[16] gpio_control_in\[16\]/one soc/mgmt_in_data[16]
++ gpio_control_in\[16\]/one padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16]
++ padframe/mprj_io_analog_sel[16] padframe/mprj_io_dm[48] padframe/mprj_io_dm[49]
++ padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16] padframe/mprj_io_ib_mode_sel[16]
++ padframe/mprj_io_in[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_out[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[16\]/serial_data_in gpio_control_in\[17\]/serial_data_in
++ mprj/io_in[16] mprj/io_oeb[16] mprj/io_out[16] gpio_control_in\[16\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[21\] soc/mgmt_in_data[21] gpio_control_in\[21\]/one soc/mgmt_in_data[21]
++ gpio_control_in\[21\]/one padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21]
++ padframe/mprj_io_analog_sel[21] padframe/mprj_io_dm[63] padframe/mprj_io_dm[64]
++ padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21] padframe/mprj_io_ib_mode_sel[21]
++ padframe/mprj_io_in[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_out[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[21\]/serial_data_in gpio_control_in\[22\]/serial_data_in
++ mprj/io_in[21] mprj/io_oeb[21] mprj/io_out[21] gpio_control_in\[21\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xmprj mprj/analog_io[0] mprj/analog_io[10] mprj/analog_io[11] mprj/analog_io[12] mprj/analog_io[13]
++ mprj/analog_io[14] mprj/analog_io[15] mprj/analog_io[16] mprj/analog_io[17] mprj/analog_io[18]
++ mprj/analog_io[19] mprj/analog_io[1] mprj/analog_io[20] mprj/analog_io[21] mprj/analog_io[22]
++ mprj/analog_io[23] mprj/analog_io[24] mprj/analog_io[25] mprj/analog_io[26] mprj/analog_io[27]
++ mprj/analog_io[28] mprj/analog_io[29] mprj/analog_io[2] mprj/analog_io[30] mprj/analog_io[3]
++ mprj/analog_io[4] mprj/analog_io[5] mprj/analog_io[6] mprj/analog_io[7] mprj/analog_io[8]
++ mprj/analog_io[9] mprj/io_in[0] mprj/io_in[10] mprj/io_in[11] mprj/io_in[12] mprj/io_in[13]
++ mprj/io_in[14] mprj/io_in[15] mprj/io_in[16] mprj/io_in[17] mprj/io_in[18] mprj/io_in[19]
++ mprj/io_in[1] mprj/io_in[20] mprj/io_in[21] mprj/io_in[22] mprj/io_in[23] mprj/io_in[24]
++ mprj/io_in[25] mprj/io_in[26] mprj/io_in[27] mprj/io_in[28] mprj/io_in[29] mprj/io_in[2]
++ mprj/io_in[30] mprj/io_in[31] mprj/io_in[32] mprj/io_in[33] mprj/io_in[34] mprj/io_in[35]
++ mprj/io_in[36] mprj/io_in[37] mprj/io_in[3] mprj/io_in[4] mprj/io_in[5] mprj/io_in[6]
++ mprj/io_in[7] mprj/io_in[8] mprj/io_in[9] mprj/io_oeb[0] mprj/io_oeb[10] mprj/io_oeb[11]
++ mprj/io_oeb[12] mprj/io_oeb[13] mprj/io_oeb[14] mprj/io_oeb[15] mprj/io_oeb[16]
++ mprj/io_oeb[17] mprj/io_oeb[18] mprj/io_oeb[19] mprj/io_oeb[1] mprj/io_oeb[20] mprj/io_oeb[21]
++ mprj/io_oeb[22] mprj/io_oeb[23] mprj/io_oeb[24] mprj/io_oeb[25] mprj/io_oeb[26]
++ mprj/io_oeb[27] mprj/io_oeb[28] mprj/io_oeb[29] mprj/io_oeb[2] mprj/io_oeb[30] mprj/io_oeb[31]
++ mprj/io_oeb[32] mprj/io_oeb[33] mprj/io_oeb[34] mprj/io_oeb[35] mprj/io_oeb[36]
++ mprj/io_oeb[37] mprj/io_oeb[3] mprj/io_oeb[4] mprj/io_oeb[5] mprj/io_oeb[6] mprj/io_oeb[7]
++ mprj/io_oeb[8] mprj/io_oeb[9] mprj/io_out[0] mprj/io_out[10] mprj/io_out[11] mprj/io_out[12]
++ mprj/io_out[13] mprj/io_out[14] mprj/io_out[15] mprj/io_out[16] mprj/io_out[17]
++ mprj/io_out[18] mprj/io_out[19] mprj/io_out[1] mprj/io_out[20] mprj/io_out[21] mprj/io_out[22]
++ mprj/io_out[23] mprj/io_out[24] mprj/io_out[25] mprj/io_out[26] mprj/io_out[27]
++ mprj/io_out[28] mprj/io_out[29] mprj/io_out[2] mprj/io_out[30] mprj/io_out[31] mprj/io_out[32]
++ mprj/io_out[33] mprj/io_out[34] mprj/io_out[35] mprj/io_out[36] mprj/io_out[37]
++ mprj/io_out[3] mprj/io_out[4] mprj/io_out[5] mprj/io_out[6] mprj/io_out[7] mprj/io_out[8]
++ mprj/io_out[9] mprj/la_data_in[0] mprj/la_data_in[100] mprj/la_data_in[101] mprj/la_data_in[102]
++ mprj/la_data_in[103] mprj/la_data_in[104] mprj/la_data_in[105] mprj/la_data_in[106]
++ mprj/la_data_in[107] mprj/la_data_in[108] mprj/la_data_in[109] mprj/la_data_in[10]
++ mprj/la_data_in[110] mprj/la_data_in[111] mprj/la_data_in[112] mprj/la_data_in[113]
++ mprj/la_data_in[114] mprj/la_data_in[115] mprj/la_data_in[116] mprj/la_data_in[117]
++ mprj/la_data_in[118] mprj/la_data_in[119] mprj/la_data_in[11] mprj/la_data_in[120]
++ mprj/la_data_in[121] mprj/la_data_in[122] mprj/la_data_in[123] mprj/la_data_in[124]
++ mprj/la_data_in[125] mprj/la_data_in[126] mprj/la_data_in[127] mprj/la_data_in[12]
++ mprj/la_data_in[13] mprj/la_data_in[14] mprj/la_data_in[15] mprj/la_data_in[16]
++ mprj/la_data_in[17] mprj/la_data_in[18] mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20]
++ mprj/la_data_in[21] mprj/la_data_in[22] mprj/la_data_in[23] mprj/la_data_in[24]
++ mprj/la_data_in[25] mprj/la_data_in[26] mprj/la_data_in[27] mprj/la_data_in[28]
++ mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30] mprj/la_data_in[31] mprj/la_data_in[32]
++ mprj/la_data_in[33] mprj/la_data_in[34] mprj/la_data_in[35] mprj/la_data_in[36]
++ mprj/la_data_in[37] mprj/la_data_in[38] mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40]
++ mprj/la_data_in[41] mprj/la_data_in[42] mprj/la_data_in[43] mprj/la_data_in[44]
++ mprj/la_data_in[45] mprj/la_data_in[46] mprj/la_data_in[47] mprj/la_data_in[48]
++ mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50] mprj/la_data_in[51] mprj/la_data_in[52]
++ mprj/la_data_in[53] mprj/la_data_in[54] mprj/la_data_in[55] mprj/la_data_in[56]
++ mprj/la_data_in[57] mprj/la_data_in[58] mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60]
++ mprj/la_data_in[61] mprj/la_data_in[62] mprj/la_data_in[63] mprj/la_data_in[64]
++ mprj/la_data_in[65] mprj/la_data_in[66] mprj/la_data_in[67] mprj/la_data_in[68]
++ mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70] mprj/la_data_in[71] mprj/la_data_in[72]
++ mprj/la_data_in[73] mprj/la_data_in[74] mprj/la_data_in[75] mprj/la_data_in[76]
++ mprj/la_data_in[77] mprj/la_data_in[78] mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80]
++ mprj/la_data_in[81] mprj/la_data_in[82] mprj/la_data_in[83] mprj/la_data_in[84]
++ mprj/la_data_in[85] mprj/la_data_in[86] mprj/la_data_in[87] mprj/la_data_in[88]
++ mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90] mprj/la_data_in[91] mprj/la_data_in[92]
++ mprj/la_data_in[93] mprj/la_data_in[94] mprj/la_data_in[95] mprj/la_data_in[96]
++ mprj/la_data_in[97] mprj/la_data_in[98] mprj/la_data_in[99] mprj/la_data_in[9] mprj/la_data_out[0]
++ mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102] mprj/la_data_out[103]
++ mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106] mprj/la_data_out[107]
++ mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10] mprj/la_data_out[110]
++ mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113] mprj/la_data_out[114]
++ mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117] mprj/la_data_out[118]
++ mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120] mprj/la_data_out[121]
++ mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124] mprj/la_data_out[125]
++ mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12] mprj/la_data_out[13]
++ mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16] mprj/la_data_out[17]
++ mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1] mprj/la_data_out[20]
++ mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23] mprj/la_data_out[24]
++ mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27] mprj/la_data_out[28]
++ mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30] mprj/la_data_out[31]
++ mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34] mprj/la_data_out[35]
++ mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38] mprj/la_data_out[39]
++ mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41] mprj/la_data_out[42]
++ mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45] mprj/la_data_out[46]
++ mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49] mprj/la_data_out[4]
++ mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52] mprj/la_data_out[53]
++ mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56] mprj/la_data_out[57]
++ mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5] mprj/la_data_out[60]
++ mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63] mprj/la_data_out[64]
++ mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67] mprj/la_data_out[68]
++ mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70] mprj/la_data_out[71]
++ mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74] mprj/la_data_out[75]
++ mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78] mprj/la_data_out[79]
++ mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81] mprj/la_data_out[82]
++ mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85] mprj/la_data_out[86]
++ mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89] mprj/la_data_out[8]
++ mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92] mprj/la_data_out[93]
++ mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96] mprj/la_data_out[97]
++ mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9] mprj/la_oen[0] mprj/la_oen[100]
++ mprj/la_oen[101] mprj/la_oen[102] mprj/la_oen[103] mprj/la_oen[104] mprj/la_oen[105]
++ mprj/la_oen[106] mprj/la_oen[107] mprj/la_oen[108] mprj/la_oen[109] mprj/la_oen[10]
++ mprj/la_oen[110] mprj/la_oen[111] mprj/la_oen[112] mprj/la_oen[113] mprj/la_oen[114]
++ mprj/la_oen[115] mprj/la_oen[116] mprj/la_oen[117] mprj/la_oen[118] mprj/la_oen[119]
++ mprj/la_oen[11] mprj/la_oen[120] mprj/la_oen[121] mprj/la_oen[122] mprj/la_oen[123]
++ mprj/la_oen[124] mprj/la_oen[125] mprj/la_oen[126] mprj/la_oen[127] mprj/la_oen[12]
++ mprj/la_oen[13] mprj/la_oen[14] mprj/la_oen[15] mprj/la_oen[16] mprj/la_oen[17]
++ mprj/la_oen[18] mprj/la_oen[19] mprj/la_oen[1] mprj/la_oen[20] mprj/la_oen[21] mprj/la_oen[22]
++ mprj/la_oen[23] mprj/la_oen[24] mprj/la_oen[25] mprj/la_oen[26] mprj/la_oen[27]
++ mprj/la_oen[28] mprj/la_oen[29] mprj/la_oen[2] mprj/la_oen[30] mprj/la_oen[31] mprj/la_oen[32]
++ mprj/la_oen[33] mprj/la_oen[34] mprj/la_oen[35] mprj/la_oen[36] mprj/la_oen[37]
++ mprj/la_oen[38] mprj/la_oen[39] mprj/la_oen[3] mprj/la_oen[40] mprj/la_oen[41] mprj/la_oen[42]
++ mprj/la_oen[43] mprj/la_oen[44] mprj/la_oen[45] mprj/la_oen[46] mprj/la_oen[47]
++ mprj/la_oen[48] mprj/la_oen[49] mprj/la_oen[4] mprj/la_oen[50] mprj/la_oen[51] mprj/la_oen[52]
++ mprj/la_oen[53] mprj/la_oen[54] mprj/la_oen[55] mprj/la_oen[56] mprj/la_oen[57]
++ mprj/la_oen[58] mprj/la_oen[59] mprj/la_oen[5] mprj/la_oen[60] mprj/la_oen[61] mprj/la_oen[62]
++ mprj/la_oen[63] mprj/la_oen[64] mprj/la_oen[65] mprj/la_oen[66] mprj/la_oen[67]
++ mprj/la_oen[68] mprj/la_oen[69] mprj/la_oen[6] mprj/la_oen[70] mprj/la_oen[71] mprj/la_oen[72]
++ mprj/la_oen[73] mprj/la_oen[74] mprj/la_oen[75] mprj/la_oen[76] mprj/la_oen[77]
++ mprj/la_oen[78] mprj/la_oen[79] mprj/la_oen[7] mprj/la_oen[80] mprj/la_oen[81] mprj/la_oen[82]
++ mprj/la_oen[83] mprj/la_oen[84] mprj/la_oen[85] mprj/la_oen[86] mprj/la_oen[87]
++ mprj/la_oen[88] mprj/la_oen[89] mprj/la_oen[8] mprj/la_oen[90] mprj/la_oen[91] mprj/la_oen[92]
++ mprj/la_oen[93] mprj/la_oen[94] mprj/la_oen[95] mprj/la_oen[96] mprj/la_oen[97]
++ mprj/la_oen[98] mprj/la_oen[99] mprj/la_oen[9] mprj/user_clock2 mprj/wb_clk_i mprj/wb_rst_i
++ soc/mprj_ack_i mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11] mprj/wbs_adr_i[12]
++ mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16] mprj/wbs_adr_i[17]
++ mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20] mprj/wbs_adr_i[21]
++ mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25] mprj/wbs_adr_i[26]
++ mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2] mprj/wbs_adr_i[30]
++ mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5] mprj/wbs_adr_i[6]
++ mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] mprj/wbs_cyc_i mprj/wbs_dat_i[0]
++ mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13] mprj/wbs_dat_i[14]
++ mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18] mprj/wbs_dat_i[19]
++ mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22] mprj/wbs_dat_i[23]
++ mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27] mprj/wbs_dat_i[28]
++ mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31] mprj/wbs_dat_i[3]
++ mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7] mprj/wbs_dat_i[8]
++ mprj/wbs_dat_i[9] soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12]
++ soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17]
++ soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21]
++ soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26]
++ soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30]
++ soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6]
++ soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] mprj/wbs_sel_i[0] mprj/wbs_sel_i[1]
++ mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] mprj/wbs_stb_i mprj/wbs_we_i vccd1 vssd1 vccd2
++ vssd2 vdda1 vssa1 vdda2 vssa2 user_project_wrapper
+Xgpio_control_in\[14\] soc/mgmt_in_data[14] gpio_control_in\[14\]/one soc/mgmt_in_data[14]
++ gpio_control_in\[14\]/one padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14]
++ padframe/mprj_io_analog_sel[14] padframe/mprj_io_dm[42] padframe/mprj_io_dm[43]
++ padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14] padframe/mprj_io_ib_mode_sel[14]
++ padframe/mprj_io_in[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_out[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[14\]/serial_data_in gpio_control_in\[15\]/serial_data_in
++ mprj/io_in[14] mprj/io_oeb[14] mprj/io_out[14] gpio_control_in\[14\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[7\] soc/mgmt_in_data[7] gpio_control_in\[7\]/one soc/mgmt_in_data[7]
++ gpio_control_in\[7\]/one padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7]
++ padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23]
++ padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_in[7]
++ padframe/mprj_io_inp_dis[7] padframe/mprj_io_out[7] padframe/mprj_io_oeb[7] padframe/mprj_io_slow_sel[7]
++ padframe/mprj_io_vtrip_sel[7] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[7\]/serial_data_in gpio_control_in\[8\]/serial_data_in mprj/io_in[7]
++ mprj/io_oeb[7] mprj/io_out[7] gpio_control_in\[7\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xcopyright_block_0 VSUBS copyright_block
+Xgpio_control_in\[5\] soc/mgmt_in_data[5] gpio_control_in\[5\]/one soc/mgmt_in_data[5]
++ gpio_control_in\[5\]/one padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_in[5]
++ padframe/mprj_io_inp_dis[5] padframe/mprj_io_out[5] padframe/mprj_io_oeb[5] padframe/mprj_io_slow_sel[5]
++ padframe/mprj_io_vtrip_sel[5] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[5\]/serial_data_in gpio_control_in\[6\]/serial_data_in mprj/io_in[5]
++ mprj/io_oeb[5] mprj/io_out[5] gpio_control_in\[5\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[37\] soc/mgmt_in_data[37] gpio_control_in\[37\]/one soc/mgmt_in_data[37]
++ gpio_control_in\[37\]/one padframe/mprj_io_analog_en[37] padframe/mprj_io_analog_pol[37]
++ padframe/mprj_io_analog_sel[37] padframe/mprj_io_dm[111] padframe/mprj_io_dm[112]
++ padframe/mprj_io_dm[113] padframe/mprj_io_holdover[37] padframe/mprj_io_ib_mode_sel[37]
++ padframe/mprj_io_in[37] padframe/mprj_io_inp_dis[37] padframe/mprj_io_out[37] padframe/mprj_io_oeb[37]
++ padframe/mprj_io_slow_sel[37] padframe/mprj_io_vtrip_sel[37] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[37\]/serial_data_in gpio_control_in\[37\]/serial_data_out
++ mprj/io_in[37] mprj/io_oeb[37] mprj/io_out[37] gpio_control_in\[37\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[12\] soc/mgmt_in_data[12] gpio_control_in\[12\]/one soc/mgmt_in_data[12]
++ gpio_control_in\[12\]/one padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12]
++ padframe/mprj_io_analog_sel[12] padframe/mprj_io_dm[36] padframe/mprj_io_dm[37]
++ padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12] padframe/mprj_io_ib_mode_sel[12]
++ padframe/mprj_io_in[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_out[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[12\]/serial_data_in gpio_control_in\[13\]/serial_data_in
++ mprj/io_in[12] mprj/io_oeb[12] mprj/io_out[12] gpio_control_in\[12\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xstorage soc/mgmt_addr[0] soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3] soc/mgmt_addr[4]
++ soc/mgmt_addr[5] soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0] soc/mgmt_addr_ro[1]
++ soc/mgmt_addr_ro[2] soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4] soc/mgmt_addr_ro[5]
++ soc/mgmt_addr_ro[6] soc/mgmt_addr_ro[7] soc/core_clk soc/mgmt_ena[0] soc/mgmt_ena[1]
++ soc/mgmt_ena_ro soc/mgmt_rdata[0] soc/mgmt_rdata[10] soc/mgmt_rdata[11] soc/mgmt_rdata[12]
++ soc/mgmt_rdata[13] soc/mgmt_rdata[14] soc/mgmt_rdata[15] soc/mgmt_rdata[16] soc/mgmt_rdata[17]
++ soc/mgmt_rdata[18] soc/mgmt_rdata[19] soc/mgmt_rdata[1] soc/mgmt_rdata[20] soc/mgmt_rdata[21]
++ soc/mgmt_rdata[22] soc/mgmt_rdata[23] soc/mgmt_rdata[24] soc/mgmt_rdata[25] soc/mgmt_rdata[26]
++ soc/mgmt_rdata[27] soc/mgmt_rdata[28] soc/mgmt_rdata[29] soc/mgmt_rdata[2] soc/mgmt_rdata[30]
++ soc/mgmt_rdata[31] soc/mgmt_rdata[32] soc/mgmt_rdata[33] soc/mgmt_rdata[34] soc/mgmt_rdata[35]
++ soc/mgmt_rdata[36] soc/mgmt_rdata[37] soc/mgmt_rdata[38] soc/mgmt_rdata[39] soc/mgmt_rdata[3]
++ soc/mgmt_rdata[40] soc/mgmt_rdata[41] soc/mgmt_rdata[42] soc/mgmt_rdata[43] soc/mgmt_rdata[44]
++ soc/mgmt_rdata[45] soc/mgmt_rdata[46] soc/mgmt_rdata[47] soc/mgmt_rdata[48] soc/mgmt_rdata[49]
++ soc/mgmt_rdata[4] soc/mgmt_rdata[50] soc/mgmt_rdata[51] soc/mgmt_rdata[52] soc/mgmt_rdata[53]
++ soc/mgmt_rdata[54] soc/mgmt_rdata[55] soc/mgmt_rdata[56] soc/mgmt_rdata[57] soc/mgmt_rdata[58]
++ soc/mgmt_rdata[59] soc/mgmt_rdata[5] soc/mgmt_rdata[60] soc/mgmt_rdata[61] soc/mgmt_rdata[62]
++ soc/mgmt_rdata[63] soc/mgmt_rdata[6] soc/mgmt_rdata[7] soc/mgmt_rdata[8] soc/mgmt_rdata[9]
++ soc/mgmt_rdata_ro[0] soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11] soc/mgmt_rdata_ro[12]
++ soc/mgmt_rdata_ro[13] soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15] soc/mgmt_rdata_ro[16]
++ soc/mgmt_rdata_ro[17] soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19] soc/mgmt_rdata_ro[1]
++ soc/mgmt_rdata_ro[20] soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22] soc/mgmt_rdata_ro[23]
++ soc/mgmt_rdata_ro[24] soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26] soc/mgmt_rdata_ro[27]
++ soc/mgmt_rdata_ro[28] soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2] soc/mgmt_rdata_ro[30]
++ soc/mgmt_rdata_ro[31] soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4] soc/mgmt_rdata_ro[5]
++ soc/mgmt_rdata_ro[6] soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8] soc/mgmt_rdata_ro[9]
++ soc/mgmt_wdata[0] soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12] soc/mgmt_wdata[13]
++ soc/mgmt_wdata[14] soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17] soc/mgmt_wdata[18]
++ soc/mgmt_wdata[19] soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21] soc/mgmt_wdata[22]
++ soc/mgmt_wdata[23] soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26] soc/mgmt_wdata[27]
++ soc/mgmt_wdata[28] soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30] soc/mgmt_wdata[31]
++ soc/mgmt_wdata[3] soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6] soc/mgmt_wdata[7]
++ soc/mgmt_wdata[8] soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1] soc/mgmt_wen_mask[0]
++ soc/mgmt_wen_mask[1] soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3] soc/mgmt_wen_mask[4]
++ soc/mgmt_wen_mask[5] soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7] vccd vssd storage
+Xgpio_control_in\[35\] soc/mgmt_in_data[35] gpio_control_in\[35\]/one soc/mgmt_in_data[35]
++ gpio_control_in\[35\]/one padframe/mprj_io_analog_en[35] padframe/mprj_io_analog_pol[35]
++ padframe/mprj_io_analog_sel[35] padframe/mprj_io_dm[105] padframe/mprj_io_dm[106]
++ padframe/mprj_io_dm[107] padframe/mprj_io_holdover[35] padframe/mprj_io_ib_mode_sel[35]
++ padframe/mprj_io_in[35] padframe/mprj_io_inp_dis[35] padframe/mprj_io_out[35] padframe/mprj_io_oeb[35]
++ padframe/mprj_io_slow_sel[35] padframe/mprj_io_vtrip_sel[35] soc/mprj_io_loader_resetn
++ soc/mprj_io_loader_clock gpio_control_in\[35\]/serial_data_in gpio_control_in\[36\]/serial_data_in
++ mprj/io_in[35] mprj/io_oeb[35] mprj/io_out[35] gpio_control_in\[35\]/zero vccd vssd
++ vccd1 vssd1 gpio_control_block
+Xgpio_control_in\[3\] soc/mgmt_in_data[3] gpio_control_in\[3\]/one soc/mgmt_in_data[3]
++ gpio_control_in\[3\]/one padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[9] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11]
++ padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_in[3]
++ padframe/mprj_io_inp_dis[3] padframe/mprj_io_out[3] padframe/mprj_io_oeb[3] padframe/mprj_io_slow_sel[3]
++ padframe/mprj_io_vtrip_sel[3] soc/mprj_io_loader_resetn soc/mprj_io_loader_clock
++ gpio_control_in\[3\]/serial_data_in gpio_control_in\[4\]/serial_data_in mprj/io_in[3]
++ mprj/io_oeb[3] mprj/io_out[3] gpio_control_in\[3\]/zero vccd vssd vccd1 vssd1 gpio_control_block
+.ends
+
diff --git a/utils/utils/MAGIC.txt b/utils/utils/MAGIC.txt
new file mode 100644
index 0000000..78b4d56
--- /dev/null
+++ b/utils/utils/MAGIC.txt
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+####
+
+1) You must set the PDK_ROOT variable
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export PDKPATH=$PDK_ROOT/sky130A ;
+
+2) Useful misc utils
+
+
+
+load caravel -dereference
+drc style drc(full)
+drc why
+drc find 10 ; findbox zoom
diff --git a/utils/utils/README.txt b/utils/utils/README.txt
new file mode 100644
index 0000000..78b4d56
--- /dev/null
+++ b/utils/utils/README.txt
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+####
+
+1) You must set the PDK_ROOT variable
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export PDKPATH=$PDK_ROOT/sky130A ;
+
+2) Useful misc utils
+
+
+
+load caravel -dereference
+drc style drc(full)
+drc why
+drc find 10 ; findbox zoom
diff --git a/utils/utils/addmpwseal.tcl b/utils/utils/addmpwseal.tcl
new file mode 100644
index 0000000..b562f93
--- /dev/null
+++ b/utils/utils/addmpwseal.tcl
@@ -0,0 +1,25 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly true
+gds rescale false
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+load ./caravel.mag
+select top cell
+move origin -7.165um -7.120um
+box position 0 0
+getcell advSeal_6um_gen
+gds write caravel.mpw.gds
diff --git a/utils/utils/apply_caravel.sh b/utils/utils/apply_caravel.sh
new file mode 100755
index 0000000..1a922cf
--- /dev/null
+++ b/utils/utils/apply_caravel.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To use: sh apply_caravel.sh <target_project_path> <template_caravel_path>
+
+target_project=$1
+original_caravel=$2
+
+find $original_caravel/def/* -type f ! -name "user_project_wrapper.def" ! -name "user_proj_example.def" -exec cp {} $target_project/def \;
+find $original_caravel/lef/* -type f ! -name "user_project_wrapper.lef" ! -name "user_proj_example.lef" -exec cp {} $target_project/lef \;
+find $original_caravel/gds/* -type f ! -name "user_project_wrapper.gds.gz" ! -name "user_proj_example.gds.gz" ! -name "user_project_wrapper.gds" ! -name "user_proj_example.gds" -exec cp {} $target_project/gds \;
+find $original_caravel/mag/* -type f ! -name "user_project_wrapper.mag" ! -name "user_proj_example.mag" -exec cp {} $target_project/mag \;
+cp $original_caravel/mag/.magicrc $target_project/mag/
+mkdir -p $target_project/mag/hexdigits/
+mv $target_project/mag/alpha_*.mag $target_project/mag/hexdigits/
+cp $original_caravel/maglef/* $target_project/maglef
+cp -r $original_caravel/ngspice/digital_pll $target_project/ngspice/digital_pll
+cp -r $original_caravel/ngspice/simple_por $target_project/ngspice/simple_por
+cp -r $original_caravel/scripts $target_project/scripts
+find $original_caravel/spi/lvs/* -type f ! -name "user_project_wrapper.spice" ! -name "user_proj_example.spice" -exec cp {} $target_project/spi/lvs/ \;
+cp -r $original_caravel/utils $target_project/utils
+find $original_caravel/verilog/rtl/* -type f ! -name "user_project_wrapper.v" ! -name "user_proj_example.v" -exec cp {} $target_project/verilog/rtl/ \;
+find $original_caravel/verilog/gl/* -type f ! -name "user_project_wrapper.v" ! -name "user_proj_example.v" -exec cp {} $target_project/verilog/gl/ \;
+cp $original_caravel/verilog/stubs/*.v $target_project/verilog/stubs/
+cp -r $original_caravel/verilog/dv/caravel $target_project/verilog/dv/caravel
+cp -r $original_caravel/verilog/dv/wb_utests $target_project/verilog/dv/wb_utests
+cp $original_caravel/verilog/dv/dummy_slave.v $target_project/verilog/dv/dummy_slave.v
+
+echo "You'll have to manually copy the openlane/user_project_wrapper configs based on your preference."
+echo "You'll have to manually copy the openlane/Makefile based on your preference."
+echo "You'll have to manually copy the Makefile based on your preference."
\ No newline at end of file
diff --git a/utils/utils/core_scripts/README.md b/utils/utils/core_scripts/README.md
new file mode 100644
index 0000000..b14c1db
--- /dev/null
+++ b/utils/utils/core_scripts/README.md
@@ -0,0 +1,20 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+# What is this?
+
+Core scripts are doing the actual work, scripts under ../scripts are the ones that should be used.
\ No newline at end of file
diff --git a/utils/utils/core_scripts/magic-drc.sh b/utils/utils/core_scripts/magic-drc.sh
new file mode 100644
index 0000000..5f5068d
--- /dev/null
+++ b/utils/utils/core_scripts/magic-drc.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./magic-drc.sh <target_path> <design_name> <pdk-root> <target-type> <pdk-name> <output_path>
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export TARGET_TYPE=$4
+export PDK=$5
+export OUT_DIR=$6
+export TCL_CALL_PATH=${7:-$(pwd)}
+
+echo "Running Magic..."
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/sky130A.magicrc
+
+magic \
+ -noconsole \
+ -dnull \
+ -rcfile $MAGIC_MAGICRC \
+ $TCL_CALL_PATH/magic-drc.tcl \
+ </dev/null \
+ |& tee $OUT_DIR/magic_drc.log
+
+TEST=$OUT_DIR/$DESIGN_NAME.magic.drc
+
+crashSignal=$(find $TEST)
+if ! [[ $crashSignal ]]; then echo "DRC Check FAILED"; exit -1; fi
+
+
+Test_Magic_violations=$(grep "COUNT: " $TEST -s | tail -1 | sed -r 's/[^0-9]*//g')
+if ! [[ $Test_Magic_violations ]]; then Test_Magic_violations=-1; fi
+if [ $Test_Magic_violations -ne -1 ]; then Test_Magic_violations=$(((Test_Magic_violations+3)/4)); fi
+
+echo "Test # of DRC Violations:"
+echo $Test_Magic_violations
+
+if [ 0 -ne $Test_Magic_violations ]; then echo "DRC Check FAILED"; exit -1; fi
+
+echo "DRC Check Passed"
+exit 0
diff --git a/utils/utils/core_scripts/magic-drc.tcl b/utils/utils/core_scripts/magic-drc.tcl
new file mode 100755
index 0000000..6768d3c
--- /dev/null
+++ b/utils/utils/core_scripts/magic-drc.tcl
@@ -0,0 +1,74 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+if { $::env(TARGET_TYPE) == "gds"} {
+ gds read $::env(TARGET_DIR)/$::env(DESIGN_NAME).gds
+} else {
+ if { $::env(TARGET_TYPE) == "mag" } {
+ load $::env(TARGET_DIR)/$::env(DESIGN_NAME).mag
+ } else {
+ def read $::env(TARGET_DIR)/$::env(DESIGN_NAME).def
+ }
+}
+
+set fout [open $::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_NAME)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $cell_name\n"
+flush stdout
+load $cell_name
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+
+
+set count 0
+puts $fout "$cell_name"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE ($::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors($::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save $::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc.mag
+puts stdout "\[INFO\]: Saved"
+
+exit 0
diff --git a/utils/utils/core_scripts/magic-ext.sh b/utils/utils/core_scripts/magic-ext.sh
new file mode 100644
index 0000000..68bfc39
--- /dev/null
+++ b/utils/utils/core_scripts/magic-ext.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./magic-ext.sh <target_path> <design_name> <pdk-root> <target-type> <pdk-name> <output_path>
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export TARGET_TYPE=$4
+export PDK=$5
+export OUT_DIR=$6
+export TCL_CALL_PATH=${7:-$(pwd)}
+
+echo "Running Magic..."
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/sky130A.magicrc
+
+magic \
+ -noconsole \
+ -dnull \
+ -rcfile $MAGIC_MAGICRC \
+ $TCL_CALL_PATH/magic-ext.tcl \
+ </dev/null \
+ |& tee $OUT_DIR/magic_ext.log
diff --git a/utils/utils/core_scripts/magic-ext.tcl b/utils/utils/core_scripts/magic-ext.tcl
new file mode 100644
index 0000000..5a05dcb
--- /dev/null
+++ b/utils/utils/core_scripts/magic-ext.tcl
@@ -0,0 +1,44 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+puts "Performing Spice Extractions..."
+
+if { ![file isdirectory $::env(OUT_DIR)] } {
+ exec mkdir $::env(OUT_DIR)/
+}
+
+
+if { $::env(TARGET_TYPE) == "gds"} {
+ gds read $::env(TARGET_DIR)/$::env(DESIGN_NAME).gds
+} else {
+ if { $::env(TARGET_TYPE) == "mag" } {
+ load $::env(TARGET_DIR)/$::env(DESIGN_NAME).mag
+ } else {
+ def read $::env(TARGET_DIR)/$::env(DESIGN_NAME).def
+ }
+}
+
+load $::env(DESIGN_NAME) -dereference
+cd $::env(OUT_DIR)/
+extract do local
+# extract warn all
+extract
+ext2spice lvs
+ext2spice $::env(DESIGN_NAME).ext
+feedback save $::env(OUT_DIR)/magic_extraction_feedback.txt
+
+puts "Done!"
\ No newline at end of file
diff --git a/utils/utils/drc-def-sky130A.sh b/utils/utils/drc-def-sky130A.sh
new file mode 100644
index 0000000..671b14a
--- /dev/null
+++ b/utils/utils/drc-def-sky130A.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-def-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "def" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/drc-gds-sky130A.sh b/utils/utils/drc-gds-sky130A.sh
new file mode 100644
index 0000000..4c1d6d8
--- /dev/null
+++ b/utils/utils/drc-gds-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-gds-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "gds" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/drc-mag-sky130A.sh b/utils/utils/drc-mag-sky130A.sh
new file mode 100644
index 0000000..2bbecd3
--- /dev/null
+++ b/utils/utils/drc-mag-sky130A.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-mag-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "mag" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/erase_box.sh b/utils/utils/erase_box.sh
new file mode 100644
index 0000000..41ceb65
--- /dev/null
+++ b/utils/utils/erase_box.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+: ${1?"Usage: $0 file.gds llx lly urx ury"}
+: ${2?"Usage: $0 file.gds llx lly urx ury"}
+: ${3?"Usage: $0 file.gds llx lly urx ury"}
+: ${4?"Usage: $0 file.gds llx lly urx ury"}
+: ${5?"Usage: $0 file.gds llx lly urx ury"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+
+
+export PDK=sky130A
+
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
+
+MAGTYPE=mag magic -rcfile $MAGIC_MAGICRC -dnull -noconsole <<EOF
+echo $MAGTYPE
+tech unlock *
+gds read $1
+box $2um $3um $4um $5um
+erase
+select area
+delete
+#### REVISE THIS:
+select top cell
+erase labels
+####
+gds write ${1%.*}_erased.gds
+EOF
+ls ${1%.*}_erased.gds
diff --git a/utils/utils/examples/README.md b/utils/utils/examples/README.md
new file mode 100644
index 0000000..10f7a37
--- /dev/null
+++ b/utils/utils/examples/README.md
@@ -0,0 +1,19 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+This folder contains miscelleneous useful scripts
+THIS IS STILL WORK IN PROGRESSS - SUGGESTIONS ARE WELCOME THROUGH ISSUES
diff --git a/utils/utils/examples/addmpwseal.tcl b/utils/utils/examples/addmpwseal.tcl
new file mode 100644
index 0000000..79e4b9e
--- /dev/null
+++ b/utils/utils/examples/addmpwseal.tcl
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly true
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+load openram_tc_1kb.mag
+select top cell
+move origin -1015um -1272.5um
+box position 0 0
+getcell advSeal_6um_gen
+save
+gds write ../gds/openram_tc_1kb.gds
+
diff --git a/utils/utils/examples/create-project.sh b/utils/utils/examples/create-project.sh
new file mode 100755
index 0000000..5b5b69c
--- /dev/null
+++ b/utils/utils/examples/create-project.sh
@@ -0,0 +1,38 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+cat <<'EOT' > .gitignore
+.DS_Store
+*.vcd
+*.raw
+*.vvp
+a.out
+EOT
+mkdir scripts ; echo "This folder contains miscelleneous useful scripts" > scripts/README.md
+mkdir def ; echo "This folder contains *.def files related to this project" > def/README.md
+mkdir gds ; echo "This folder contains *.gds files related to this project" > gds/README.md
+mkdir verilog ; echo "This folder contains *.v files related to this project" > verilog/README.md
+mkdir mag ; echo "This folder contains *.mag files related to this project" > mag/README.md
+mkdir lef ; echo "This folder contains *.lef files related to this project" > lef/README.md
+mkdir macros ; echo "This folder contains subcell & macro files related to this project" > macros/README.md
+mkdir doc ; echo "This folder contains documents related to this project" > doc/README.md
+mkdir ngspice ; echo "This folder contains ngspice related files related to this project" > ngspice/README.md
+mkdir openlane ; echo "This folder contains openlane related files related to this project" > openlane/README.md
+mkdir pkg ; echo "This folder contains packaging-related files related to this project" > pkg/README.md
+mkdir test ; echo "This folder contains test-related files related to this project" > test/README.md
+mkdir xspice ; echo "This folder contains xspice files related to this project" > xspice/README.md
+mkdir spi ; echo "This folder contains *.spi files related to this project" > spi/README.md
+mkdir qflow ; echo "This folder contains qflow-related files related to this project" > qflow/README.md
diff --git a/utils/utils/examples/dot.magicrc b/utils/utils/examples/dot.magicrc
new file mode 100644
index 0000000..42f2fb2
--- /dev/null
+++ b/utils/utils/examples/dot.magicrc
@@ -0,0 +1,65 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+
+# default pdk
+# set SW_PDK_ROOT "/ef/tech/SW.2"
+set PDK "sky130A"
+set SCL_VARIANT "sky130_fd_sc_hd"
+set IO_VARIANT "sky130_fd_io"
+set PDKPATH "$::env(SW_PDK_ROOT)/$PDK"
+
+# loading technology
+tech load "$PDKPATH/libs.tech/magic/current/$PDK.tech"
+
+# load device generator
+source "$PDKPATH/libs.tech/magic/current/$PDK.tcl"
+
+
+# load bind keys (optional)
+source "$PDKPATH/libs.tech/magic/current/$PDK-BindKeys"
+
+# set units to lambda grid
+snap lambda
+
+# add path to reference cells
+set MAGPATH "$PDKPATH/libs.ref/$SCL_VARIANT/mag/*.mag"
+
+
+addpath "$PDKPATH/libs.ref/sky130_fd_pr_base/mag"
+addpath "$PDKPATH/libs.ref/$IO_VARIANT/mag"
+addpath "$PDKPATH/libs.ref/$SCL_VARIANT/mag"
+
+# addpath ${MAGPATH}/s8fmlt
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/utils/utils/examples/drc-mag.sh b/utils/utils/examples/drc-mag.sh
new file mode 100644
index 0000000..7229f45
--- /dev/null
+++ b/utils/utils/examples/drc-mag.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/drc-maglef.sh b/utils/utils/examples/drc-maglef.sh
new file mode 100644
index 0000000..42f622f
--- /dev/null
+++ b/utils/utils/examples/drc-maglef.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/drc.sh b/utils/utils/examples/drc.sh
new file mode 100755
index 0000000..7229f45
--- /dev/null
+++ b/utils/utils/examples/drc.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/edit.tcl b/utils/utils/examples/edit.tcl
new file mode 100644
index 0000000..f1766ad
--- /dev/null
+++ b/utils/utils/examples/edit.tcl
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+puts "Small delay..."
+set macro_mags "digital_pll.mag lvlshiftdown.mag striVe2_soc.mag striVe_clkrst.mag striVe_spi.mag"
+
+gds readonly yes
+gds rescale no
+gds read ../gds/sram_1rw1r_32_256_8_sky130.gds
+lef read ../lef/sram.abs.lef
+foreach ff $macro_mags { drc off; load $ff -dereference; after 1000; select top cell; property LEFview TRUE }
+load striVe2 -dereference
+select top cell
diff --git a/utils/utils/examples/ext-gds.sh b/utils/utils/examples/ext-gds.sh
new file mode 100644
index 0000000..c3efd7e
--- /dev/null
+++ b/utils/utils/examples/ext-gds.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber offS
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/ext-mag.sh b/utils/utils/examples/ext-mag.sh
new file mode 100644
index 0000000..a62a831
--- /dev/null
+++ b/utils/utils/examples/ext-mag.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber offS
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/ext.sh b/utils/utils/examples/ext.sh
new file mode 100644
index 0000000..b414e8b
--- /dev/null
+++ b/utils/utils/examples/ext.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber off
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/utils/utils/examples/extract.tcl b/utils/utils/examples/extract.tcl
new file mode 100644
index 0000000..a38c9cb
--- /dev/null
+++ b/utils/utils/examples/extract.tcl
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+lef read $::env(PDKPATH)/libs.ref/techLEF/scs8hd/scs8hd_tech.lef
+set macro_mags "openram_tc_core.mag"
+
+# lef read ../lef/sram_1rw1r_32_256_8_sky130_lp1.lef
+
+foreach ff $macro_mags { drc off; after 500; load $ff -dereference; select top cell; property LEFview TRUE }
+
+load openram_tc_1kb -dereference
+
+select top cell
+extract do local
+extract
+ext2spice lvs
+ext2spice openram_tc_1kb.ext
+feedback save extract.tcl.log
+exit
diff --git a/utils/utils/examples/lvs.sh b/utils/utils/examples/lvs.sh
new file mode 100755
index 0000000..3a5043e
--- /dev/null
+++ b/utils/utils/examples/lvs.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+/ef/apps/bin/netgen -noconsole << EOF
+readnet spice $1.spice
+readnet spice $1.sp
+lvs {$1.spice sram_2_16_sky130} {sram_2_16_sky130.sp sram_2_16_sky130} setup.tcl sram_2_16_sky130.lvs.report
+quit
+EOF
diff --git a/utils/utils/examples/mag2gds.tcl b/utils/utils/examples/mag2gds.tcl
new file mode 100644
index 0000000..8d7057d
--- /dev/null
+++ b/utils/utils/examples/mag2gds.tcl
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# assumes an /ef tree or at least a symlink
+drc off
+gds readonly true
+gds rescale false
+set ::env(MAGTYPE) mag
+
+# gds read <hard macros read as-is.gds>
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+
+load sram_1rw1r_32_256_8_sky130 -dereference
+load openram_tc_core -dereference
+load openram_tc_1kb -dereference
+
+select top cell
+
+cif *hier write disable
+
+gds write openram_tc_1kb.gds
diff --git a/utils/utils/examples/magic_drc.tcl b/utils/utils/examples/magic_drc.tcl
new file mode 100755
index 0000000..554a4c6
--- /dev/null
+++ b/utils/utils/examples/magic_drc.tcl
@@ -0,0 +1,71 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+set ::env(DESIGN_NAME) openram_tc_1kb
+drc off
+lef read ../lef/sram_1rw1r_32_256_8_sky130_lp1.lef
+load sram_1rw1r_32_256_8_sky130 -dereference
+load openram_tc_core -dereference
+load openram_tc_1kb -dereference
+
+drc style drc(full)
+drc euclidean on
+
+set fout [open drc.log w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_NAME)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $cell_name\n"
+flush stdout
+load $cell_name
+select top cell
+drc check
+set drcresult [drc listall why]
+
+
+set count 0
+puts $fout "$cell_name"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE ($::env(DESIGN_NAME).drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors($::env(DESIGN_NAME).drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save $::env(DESIGN_NAME).drc.mag
+puts stdout "\[INFO\]: Saved"
+
+exit 0
diff --git a/utils/utils/examples/pfg.sh b/utils/utils/examples/pfg.sh
new file mode 100755
index 0000000..9d8def1
--- /dev/null
+++ b/utils/utils/examples/pfg.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDKPATH=/home/mk/zooz/pdks/ef-skywater-s8/EFS8A
+export MAGTYPE=mag
+
+padring \
+-L $PDKPATH/libs.ref/lef/s8iom0s8/s8iom0s8.lef \
+-L $PDKPATH/libs.ref/lef/s8iom0s8/power_pads_lib.lef \
+--def padframe.def padframe.cfg
+
+magic -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc -noc -dnull <<EOF
+def read padframe.def
+save padframe
+select top cell
+lef write padframe.lef
+gds write padframe.gds
+exit
+EOF
+
+
+
+
+
diff --git a/utils/utils/examples/run_openram_tc_1kb.sh b/utils/utils/examples/run_openram_tc_1kb.sh
new file mode 100755
index 0000000..408ce96
--- /dev/null
+++ b/utils/utils/examples/run_openram_tc_1kb.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# Run netgen on striVe (top level)
+#
+
+NETGEN_SETUP=$PDK_ROOT/EFS8A/libs.tech/netgen/EFS8A_setup.tcl
+
+netgen -batch lvs "../spi/openram_tc_1kb.spice openram_tc_1kb" "../verilog/gl/openram_tc_1kb.synthesis.v openram_tc_1kb" ${NETGEN_SETUP} openram_tc_1kb_comp.out -json | tee openram_tc_1kb_comp_lvs.log
diff --git a/utils/utils/examples/setup.tcl b/utils/utils/examples/setup.tcl
new file mode 100644
index 0000000..193dd2f
--- /dev/null
+++ b/utils/utils/examples/setup.tcl
@@ -0,0 +1,27 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# We must flatten these because the ports are disconnected
+flatten class {-circuit1 dummy_cell_6t}
+flatten class {-circuit1 dummy_cell_1rw_1r}
+flatten class {-circuit1 dummy_cell_1w_1r}
+flatten class {-circuit1 bitcell_array_0}
+flatten class {-circuit1 pbitcell_0}
+flatten class {-circuit1 pbitcell_1}
+property {-circuit1 nshort} remove as ad ps pd
+property {-circuit1 pshort} remove as ad ps pd
+property {-circuit2 nshort} remove as ad ps pd
+property {-circuit2 pshort} remove as ad ps pd
+permute transistors
diff --git a/utils/utils/examples/wrap.tcl b/utils/utils/examples/wrap.tcl
new file mode 100644
index 0000000..fc2c87e
--- /dev/null
+++ b/utils/utils/examples/wrap.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly yes
+gds rescale no
+
+gds read ../macros/sram/riscv-sky130/sram_1rw1r_32_256_8_sky130.gds
+load sram_1rw1r_32_256_8_sky130
+
+select top cell
+property LEFview "TRUE"
+
+save pk_sram_1rw1r_32_256_8_sky130.mag
+
+# exec sed -i -E "/^.*GDS_END.*$/d" sram_1rw1r_32_256_8_sky130_original.mag
diff --git a/utils/utils/examples/wrap2.tcl b/utils/utils/examples/wrap2.tcl
new file mode 100644
index 0000000..db1db3c
--- /dev/null
+++ b/utils/utils/examples/wrap2.tcl
@@ -0,0 +1,36 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly yes
+gds rescale no
+
+lef read ../lef/sram.abs.con.lef
+load sram_1rw1r_32_256_8_sky130
+
+select top cell
+expand
+property LEFview ""
+property LEFsymmetry ""
+property LEFclass ""
+
+box position 5um 5um
+getcell pk_sram_1rw1r_32_256_8_sky130
+
+save sram_1rw1r_32_256_8_sky130.mag
+
+gds write output.gds
+
+save
diff --git a/utils/utils/examples/xor.drc b/utils/utils/examples/xor.drc
new file mode 100644
index 0000000..14896ee
--- /dev/null
+++ b/utils/utils/examples/xor.drc
@@ -0,0 +1,42 @@
+# A general XOR script
+# (https://www.klayout.de/forum/discussion/100/xor-vs-diff-tool)
+# This script uses KLayout's DRC language to implement a generic
+# XOR between two layouts. The name of the layouts is given
+# in $a and $b.
+
+# For layout-to-layout XOR with multiple cores, run this script with
+# ./klayout -r xor.drc -rd thr=NUM_CORES -rd top_cell=TOP_CELL_NAME -rd a=a.gds -rd b=b.gds -rd ol=xor.gds -zz
+# (replace NUM_CORES by the desired number of cores to utilize
+
+# enable timing output
+verbose
+
+# set up input a
+a = source($a, $top_cell)
+
+# set up input b
+b = source($b, $top_cell)
+
+$o && report("XOR #{$a} vs. #{$b}", $o)
+$ol && target($ol, $co || "XOR")
+
+$thr && threads($thr) || threads(2)
+
+# collect all common layers
+layers = {}
+[ a.layout, b.layout ].each do |ly|
+ ly.layer_indices.each do |li|
+ i = ly.get_info(li)
+ layers[i.to_s] = i
+ end
+end
+
+# perform the XOR's
+layers.keys.sort.each do |l|
+ i = layers[l]
+ info("--- Running XOR for #{l} ---")
+ x = a.input(l) ^ b.input(l)
+ info("XOR differences: #{x.data.size}")
+ $o && x.output(l, "XOR results for layer #{l}")
+ $ol && x.output(i.layer, i.datatype, i.name)
+end
diff --git a/utils/utils/examples/xor.sh b/utils/utils/examples/xor.sh
new file mode 100755
index 0000000..6911062
--- /dev/null
+++ b/utils/utils/examples/xor.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+: ${1?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+: ${2?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+: ${3?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+
+klayout -r $(dirname $0)/xor.drc -rd top_cell=$3 -rd a=$1 -rd b=$2 -rd thr=$(nproc) -rd ol=xor.gds -zz
diff --git a/utils/utils/ext-def-sky130A.sh b/utils/utils/ext-def-sky130A.sh
new file mode 100644
index 0000000..51ec955
--- /dev/null
+++ b/utils/utils/ext-def-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-def-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "def" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/ext-gds-sky130A.sh b/utils/utils/ext-gds-sky130A.sh
new file mode 100644
index 0000000..35071b8
--- /dev/null
+++ b/utils/utils/ext-gds-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-gds-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "gds" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/ext-mag-sky130A.sh b/utils/utils/ext-mag-sky130A.sh
new file mode 100644
index 0000000..b57ec31
--- /dev/null
+++ b/utils/utils/ext-mag-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-mag-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "mag" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/utils/utils/gds2mag-mag.local.sh b/utils/utils/gds2mag-mag.local.sh
new file mode 100755
index 0000000..110358b
--- /dev/null
+++ b/utils/utils/gds2mag-mag.local.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -dnull -noconsole << EOF
+#------------------------------------------------------
+drc off
+#---------------------------------gds polygon subcell true
+gds warning default
+gds readonly true
+gds rescale false
+#---------------------------------tech unlock *
+gds read $1
+load ${1%.gds}
+#---------------------------------readspice ${1%.gds}.sp
+cellname delete "(UNNAMED)"
+save ${1%.gds}.mag
+quit -noprompt
+EOF
diff --git a/utils/utils/gds2mag-mag.sh b/utils/utils/gds2mag-mag.sh
new file mode 100755
index 0000000..d53b156
--- /dev/null
+++ b/utils/utils/gds2mag-mag.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOF
+#------------------------------------------------------
+drc off
+#---------------------------------gds polygon subcell true
+gds warning default
+gds readonly true
+gds rescale false
+#---------------------------------tech unlock *
+gds read $1
+load ${1%.gds}
+#---------------------------------readspice ${1%.gds}.sp
+cellname delete "(UNNAMED)"
+save ${1%.gds}.mag
+quit -noprompt
+EOF
diff --git a/utils/utils/lef2maglef.sh b/utils/utils/lef2maglef.sh
new file mode 100755
index 0000000..455c4a6
--- /dev/null
+++ b/utils/utils/lef2maglef.sh
@@ -0,0 +1,60 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/utils/utils/mag2maglef-mag.sh b/utils/utils/mag2maglef-mag.sh
new file mode 100755
index 0000000..2934887
--- /dev/null
+++ b/utils/utils/mag2maglef-mag.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef -hide
+quit -noprompt
+EOF
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/utils/utils/mag2maglef-maglef.localrc.sh b/utils/utils/mag2maglef-maglef.localrc.sh
new file mode 100755
index 0000000..f167252
--- /dev/null
+++ b/utils/utils/mag2maglef-maglef.localrc.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=maglef ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef -hide
+quit -noprompt
+EOF
+
+$MAGIC -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/utils/utils/mag2maglef-maglef.sh b/utils/utils/mag2maglef-maglef.sh
new file mode 100755
index 0000000..e70fbd3
--- /dev/null
+++ b/utils/utils/mag2maglef-maglef.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=maglef ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef
+quit -noprompt
+EOF
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/utils/utils/magicDrc b/utils/utils/magicDrc
new file mode 100755
index 0000000..fa6f783
--- /dev/null
+++ b/utils/utils/magicDrc
@@ -0,0 +1,888 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2015, 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (C) 2015, 2020 efabless Corporation. All Rights Reserved.
+# filter out most options, so magic Natively sees/handles *only* -T <file>.
+# for-bash\
+ declare -a C ; declare -a N ; export _CE= _NE= _M0= ;\
+ for i in "$@" ; do _M0="$_M0${_M0:+ }\"${i//\"/\\\"}\""; done ;\
+ while getopts "NFT:S:l:P:" o; do \
+ : echo got "optchar $o, with optarg $OPTARG" ;\
+ case "$o" in S) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in P) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in F|N) \
+ C+=(-${o}) ;\
+ continue ; esac ;\
+ case "$o" in l) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in T) \
+ N+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ done ;\
+ shift $((OPTIND-1)) ;\
+ for i in "${C[@]}" ; do _CE="$_CE${_CE:+ }\"${i//\"/\\\"}\""; done ;\
+ for i in "${N[@]}" ; do _NE="$_NE${_NE:+ }\"${i//\"/\\\"}\""; done ;\
+ exec magic -dnull -noconsole "${N[@]}" <"$0"
+# for-magic:
+# magicDrc: run magic-DRC in batch on a .mag file, tabulate/pareto the error counts.
+#
+# magicDrc [-T <techfilePath>] [-S <drcStyleName>] [-P <N> ] [-l FILE_NAME] <magFileName>
+# -T name specific techfile (def .tech extension), passed to magic itself only, overrides tech implied by magFileName
+# -S if given, changes from techfile's default drc style (perhaps "drc(fast)") to named style, for example: -S "drc(full)"
+# -l if given, enumerates EVERY individual error bbox to the FILE_NAME
+# -N if given, do Not use -dereference option of load for topcell (not available in older magics)
+# -F flatten top cell in-memory only, not saved (experimental)
+# -P do crude drc performance measurement. At top-cell, do 'drc find' <N> times and report time per call.
+# Stdout will log a pareto of error type by count regardless.
+#
+# <magFileName>: names a .mag file, the toplevel of the hier. to DRC/pareto
+#
+# Normal magic init. files are STILL sourced: ~/.magicrc and either $CWD/.magicrc or $CWD/magic_setup.
+# (This would NOT happen if -rcfile magic cmd-line option were used).
+#
+# WARNING: Before 8.1.70, *.mag on cmd-line that was only found in cell search path set by .magicrc inits,
+# would FAIL to determine the default tech-file.
+#
+# rb@ef 2015-06-30 author
+# rb 2020-03-11 embed some library functions, to standalone from efabless-opengalaxy env, test via magic-8.2.194
+#
+# magic itself outputs following usage message though -rcfile doesn't appear to work (in some versions):
+# Usage: magic [-g gPort] [-d devType] [-m monType] [-i tabletPort] [-D] [-F objFile saveFile]
+# [-T technology] [-rcfile startupFile | -norcfile][-noconsole] [-nowindow] [-wrapper] [file]
+#
+set Prog "magicDrc"
+
+set argv [eval "list $env(_M0)"] ;# orig. mix of native plus custom args, for logging all args to script
+
+proc usage {args} {
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+ puts {usage: [ -T <techfilePath> ] [-S <drcStyleName>] [-N] [-l FILE_NAME] <magFileName>}
+ puts " -T name specific techfile, passed to magic itself only, overrides tech implied by magFileName"
+ puts " -S if given, changes from techfile's default drc style (perhaps \"drc(fast)\") to named style, for example: -S \"drc(full)\""
+ puts " -l if given, enumerates EVERY individual error bbox to the FILE_NAME"
+ puts " -N if given, do not use -dereference option of load for topcell (not available in older magics)"
+ puts " Stdout will log a pareto of error type by count regardless."
+ puts ""
+ puts " Recommend to run in dir with a ./.magicrc (or ./magic_setup) to configure magic's"
+ puts " cell search path, thru addpath statements, to locate all cells."
+}
+
+# optionally hardcode library proc-s (part of site-wide extensions - always available - in context of efabless/open-galaxy)
+# This is to make the script more standalone from efabless environment; but these capabilities should be native to magic.
+
+if {[info command scratchWritable] == {}} {
+ puts "${::Prog}: hardcoding library proc-s..."
+# Replacement for 'cellname list exists CELLNAME', to fix ambiguity for cell "0".
+# For cell "0" test for membership in 'cellname list allcells'.
+#
+# Instead of returning 0 for (non-existent) and cellname for exists,
+# returns regular 0/1 instead for non-existent/exists.
+#
+# Therefore NOT direct replacement for uses of 'cellname list exists CELL'.
+# Requires code changes.
+proc cellnameExists {cell} {
+ expr {$cell ne "0" && [cellname list exists $cell] eq $cell ||
+ $cell eq "0" && [lsearch -exact [cellname list allcells] $cell] > -1}
+}
+
+#
+# scratchWritable [-cleanup] [cellname1 ...] --
+#
+# Turn readonly cells writable in-memory, via redirect to scratch dir.
+# No cellname args: default is to process just all non-writable cells.
+# Explicit cellname arguments: ARE scatchified EVEN if ALREADY writable.
+# Limitation: Explicit named cell created in-mem, never saved, won't scratchify.
+# If just -cleanup: default is to only do cleanup: don't scratchify
+# any cells.
+#
+# -cleanup: Last scratch-dir, if any, and contents are deleted first.
+# No restoring old filepath of cells, save after cleanup will fail.
+#
+# Caller strongly recommended to first do: 'select top cell; expand'
+# to force whole hier. of a topcell to be loaded from disk into memory.
+#
+# This proc does not force expand cells. Before expanded, cells cannot be
+# checked whether writable, and cannot have filepath changed.
+#
+# For batch DRC, for 'drc listall count', every cell in-memory must
+# appear writable. This is the work-around (caller to 1st ensure
+# hier. is loaded): Reset filepath of readonly cells to a scratch dir,
+# make a dummy/empty .mag in scratch dir for each cell. Change cell's
+# writeable flag.
+#
+# Skipped cells:
+# In all cases, cells are skipped if
+# 'cellname filepath' matches ::scratchWritableDir (already scratchified),
+# This proc does NOT try and force expand; it presumes caller forced an expand
+# thus cells are skipped if:
+# 'cellname filepath' is "default" (can mean not expanded yet, or created never saved),
+# 'cellname filepath' is <CELLNAME>.mag, indicates failed expand (unbound).
+# Note: when filepath gives "default" or <CELLNAME>.mag, the writeable check not meaningful.
+#
+# How to scratchify all in-memory cells (still subject to internal skipping):
+# scratchWritable {*}[cellname list allcells]
+#
+# TODO: use a combo of filepath & flags likely can detect created in-mem,
+# and could redirect those too scratch dir if named explicitly.
+#
+# Side-effects:
+# Runs zero or one subprocess, '/bin/mktemp -d' to make a scratch dir.
+# Redirects where newly modified cells would be saved, if they ever are saved.
+# Make's a scratch dir that needs to be cleaned-up.
+# Leaves empty *.mag files in that scratch dir.
+#
+# Uses/requires proc cellnameExists.
+#
+# Same scratch-dir is reused if called multiple times, until next -cleanup.
+#
+# return value: list of cells not processed (skipped) for reasons cited above.
+# Non-existent cells are also skipped but not included in the return list.
+#
+if {![info exists ::scratchWritableDir]} {set ::scratchWritableDir {}}
+if {![info exists ::scratchWritableVerb]} {set ::scratchWritableVerb 0}
+proc scratchWritable {args} {
+ # parse -cleanup option
+ set clean [expr {[lindex $args 0] eq {-cleanup}}]
+ if {$clean} {
+ set args [lrange $args 1 end]
+ }
+
+ # If explicit cells given: don't limit to processing just readOnly cells.
+ set onlyReadonly [expr {$args == {}}]
+
+ # only if no -cleanup, does empty cell list imply all cells
+ set allcell [cellname list allcells]
+ if {!$clean && $args == {}} {
+ set args $allcell
+ }
+
+ # do cleanup
+ if {$clean} {
+ if {$::scratchWritableDir != {} && [file isdir $::scratchWritableDir]} {
+ set files [glob -dir $::scratchWritableDir -- {*.ext} {*.mag}]
+ lappend files $::scratchWritableDir
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: running, file delete $files"
+ }
+ eval {file delete} $files
+ set ::scratchWritableDir {}
+ }
+ }
+
+ # Filter out non-existent or unbound cells.
+ # Optionally filter already writable cells.
+ #
+ # Unbounds result from placements of cells that now don't exist:
+ # fail to expand. This proc does not try and force expand; it
+ # presumes a forced expand was already done by caller (if caller
+ # wished).
+ #
+ # Referenced/used cells are initially unexpanded, not yet even located
+ # located in the search path, 'cellname filepath' returns "default".
+ # If expand fails (not found in search path), then 'cellname filepath'
+ # returns <CELLNAME>.mag, if expand worked, the directory containing
+ # the cell.
+ #
+ # If cell was 'cellname create' made, but never saved also "default".
+ # Such a cell is writable. So filter "default" and <CELLNAME>.mag.
+ set skipped {}
+ set ercell1 {}
+ set docells {}
+ foreach cell $args {
+ # filter (without recording as skipped) non-existent cells.
+ if {![cellnameExists $cell]} { continue }
+
+ # filepath = "default": unexpanded (not loaded from disk),
+ # or created in-mem and never saved (is writable already
+ # though flags won't say so): skip both.
+ # TODO: use a combo of filepath & flags likely can detect created in-mem,
+ # and might be able to redirect them too to scratch dir if named explicitly.
+ set tmppath [cellname list filepath $cell]
+ if {$tmppath eq "default"} {
+ lappend skipped $cell
+ continue
+ }
+
+ # flags not meaningful, until expanded or expand attempted.
+ # After expand attempt (filepath != "default"), and flags
+ # can now be used to determine cell unbound: not available.
+ set flags [cellname list flags $cell]
+ if {[lsearch -exact $flags available] < 0} {
+ lappend ercell1 $cell
+ continue
+ }
+
+ if {$onlyReadonly &&
+ [cellname list writeable $cell] eq "writeable"} {
+ lappend skipped $cell
+ continue
+ }
+ lappend docells $cell
+ }
+
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: skipped cells: $skipped"
+ }
+
+ # don't make a scratch dir if no work to do
+ if {$docells == {}} {
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: scratch-directed 0 cells"
+ }
+ return $skipped
+ }
+
+ # make a scratch dir if needed
+ if {$::scratchWritableDir == {}} {
+ if {[catch {set dir [string trimright [exec /bin/mktemp -d]]} msg]} {
+ error "ERROR: scratchWritable, '/bin/mktemp -d' failed, $msg"
+ }
+ if {![file isdir $dir] || ![file writable $dir]} {
+ error "ERROR: scratchWritable, mktemp gave $dir, not a writable dir"
+ }
+ set ::scratchWritableDir $dir
+ }
+
+ set ercell2 {}
+ set okcell {}
+ set madef 0
+ foreach cell $docells {
+ # Relocate if needed: filepath doesn't already point to the scratch dir).
+ # 'cellname list filepath <cellNm>' -> appears to omit .mag extension,
+ # but disk-file needs the .mag in the path.
+ set trgr [file join $::scratchWritableDir "$cell"] ;# expected "lookup" path
+ set trgw [file join $::scratchWritableDir "$cell.mag"] ;# true "write" disk path
+ set src [cellname list filepath $cell]
+ if {[cellname list filepath $cell] ne $trgr && [cellname list filepath $cell] ne $trgw} {
+
+ # make empty .mag for the cell
+ if {[catch {set outmag [open $trgw w]} msg]} {
+ lappend ercell2 $cell
+ continue
+ }
+ incr madef
+ close $outmag
+
+ # relocate cell to new file
+ cellname list filepath $cell $::scratchWritableDir
+ }
+
+ # make cell writable
+ cellname list writeable $cell true
+ lappend okcell $cell
+ }
+
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: scratch-directed $madef cells"
+ }
+ if {$ercell1 != {} || $ercell2 != {}} {
+ set pre "ERROR: scratchWritable, "
+ set msg {}
+ if {$ercell1 != {}} {
+ lappend msg "$pre unbound cell(s): $ercell1"
+ }
+ if {$ercell2 != {}} {
+ lappend msg "$pre failed to make .mag for cell(s): $ercell2"
+ }
+ error [join $msg "\n"]
+ }
+ set skipped
+} ;# end proc scratchWritable
+}
+
+# without top-level proc around bulk of script, intermediate error statements don't abort script.
+proc main {argv} {
+
+# process name-value pair options, if any
+set nbrErr 0
+set ndx 0
+set max [llength $argv]
+set extTechOpt {} ;# -T ...
+set enumFilel {} ;# -l ... enum output file
+set variant {} ;# -S ... non-default drc style
+set flatten 0
+set perfN 0 ;# -P <N> do crude DRC perf. test
+set noderef 0 ;# -N disable dereference option of: 'load ... -dereference'
+
+while {$ndx < $max && [string match "-*" [lindex $argv $ndx]]} {
+ set opt [lindex $argv $ndx]
+ incr ndx
+ switch -exact -- $opt {
+ -T {
+ if {$ndx == $max} {
+ usage "missing tech-file argument for -T option"
+ exit 1
+ }
+ set extTechOpt [lindex $argv $ndx]
+ incr ndx
+ }
+ -S {
+ if {$ndx == $max} {
+ usage "missing drcStyle argument for -S option"
+ exit 1
+ }
+ set variant [lindex $argv $ndx]
+ incr ndx
+ }
+ -P {
+ if {$ndx == $max} {
+ usage "missing count argument for -P option"
+ exit 1
+ }
+ set perfN [lindex $argv $ndx]
+ incr ndx
+ }
+ -F {
+ set flatten 1
+ }
+ -N {
+ set noderef 1
+ }
+ -l {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -l option"
+ exit 1
+ }
+ set enumFilel [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOut [open $enumFilel w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFilel' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFilel"
+ }
+ default {
+ usage "unknown option: $opt"
+ exit 1
+ }
+ }
+}
+
+if {$ndx == $max} {
+ usage "missing magFileName argument, the topcell"
+ exit 1
+}
+
+# get cmd-line topcell, minus dir-path; and minus extension IFF ext is .mag
+set topc [file tail [lindex $argv $ndx]] ; incr ndx
+if {[file extension $topc] eq ".mag"} {
+ set topc [file rootname $topc]
+}
+set topcStr $topc
+
+# abort if user supplies extra args.
+if {$ndx != $max} {
+ usage "extra/unspported arg past magFileName, '[lindex $argv $ndx]'"
+ exit 1
+}
+
+# load the techfile
+if {$extTechOpt != ""} {
+ if {![file readable $extTechOpt]} {
+ error "ERROR: ${::Prog}: tech-file \"$extTechOpt\" is not readable."
+ }
+
+ tech load $extTechOpt
+
+ # Verify the cmd-line -T option (if any) is still the current 'tech filename'. If we didn't
+ # explicitly 'tech load' ourselves, the .magicrc or magic.setup might 'tech load' something else.
+ # The 'file join [pwd] ...' makes relative path absolute, but without resolving
+ # all symlinks (which 'file normalize' would do).
+ set techf2 [file join [pwd] [tech filename]]
+ set techf1 [file join [pwd] $extTechOpt]
+ if {$techf1 != $techf2} {
+ error "ERROR: ${::Prog}: failed tech-load \"$techf1\" (tech-filename=\"$techf2\" not a match)"
+ }
+}
+
+# if mag-cell were passed natively on magic cmd-line, this is too late:
+if {$noderef} {
+ load $topc
+} else {
+ load $topc -dereference
+}
+
+# error checks: ensure (1st) cmd-line cellname now in-memory, and is now the current cell
+
+set topcells [cellname list top]
+# filter (UNNAMED)
+set topcells [lsearch -exact -not -all -inline $topcells "(UNNAMED)"]
+# puts "cellname-list-top is: $topcells"
+
+# could use [cellname list flags $topc] and ensure non-null result (list with available),
+# but if it fails (cell not found), it generates unwanted stdout.
+if {[lsearch -exact [cellname list allcells] $topc] < 0} {
+ error "ERROR: ${::Prog}: cmd-line topcell \"$topc\" not in magic's list of allcells."
+}
+
+if {[lsearch -exact $topcells $topc] < 0} {
+ puts "WARNING: ${::Prog}: cmd-line topcell \"$topc\" not in magic's list of topcells: $topcells"
+}
+
+# crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+# WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+set topcw [cellname list window]
+if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: cmd-line topcell, $topc, is not the current cell, 'cellname list window'=$topcw"
+}
+
+# for topcell, filepath==default doesn't change by expand,
+# indicates unknown cell created in-memory by magic's startup sequence.
+if {[cellnameExists $topc] &&
+ [cellname list filepath $topc] eq "default"} {
+ puts "Search path for cells is \"[path search]\""
+ error "ERROR: ${::Prog}: cmd-line topcell, $topc, auto-created in-memory: not found in cell search path"
+}
+
+if {$flatten} {
+ # delete (UNNAMED) if any.
+ set trg "(UNNAMED)"
+ if {[cellnameExists $trg]} {cellname delete $trg}
+
+ # rename top cell to (UNNAMED)
+ cellname rename $topc $trg
+
+ # now Edit Cell contents are original top cell, but under name (UNNAMED)
+ # flatten Edit-Cell into original top cell name
+ puts "${::Prog}: flattening..."
+ flatten $topc
+
+ # load and edit new version of top cell. This is from in-memory, just making it current-cell.
+ # (So with or without -dereference is expected would have discernable effect by now;
+ # and since it's flattened there are no subcell instances either).
+ if {$noderef} {
+ load $topc
+ } else {
+ load $topc -dereference
+ }
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: assertion failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ }
+
+ # should not be necessary:
+ select top cell
+ edit
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: assertion-2 failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ }
+}
+
+# todo: Need a check for non-existent topcell (though magic reported not-found and auto-created it).
+# todo: We should locate fullpath to topcell on disk to record this in the log.
+#
+# WARNING, magic junkCell, or magic junkDir/junkCell (passing paths to cells that don't exist),
+# generate startup error messages (could not open cell), but magic creates the new cell in memory.
+# No simple way to detect this after the fact. Can walk the cell search path to verify it's on disk.
+# For the non-existent cell, magic also discards the dirpath from the cmd-line arg.
+# If it did exist at that path, magic opens it successfully, despite that dir not in search path.
+# A proper check for implicit create of non-existent cell should account for this effect too.
+
+# write a line with timestamp and all arguments to stdout (log)
+# (magic renames the TCL clock command)
+set clockp clock
+if {[info command $clockp] == {} && [info command orig_clock] != {}} {
+ set clockp orig_clock
+}
+set nowSec [$clockp seconds]
+set timestamp [$clockp format $nowSec -format "%Y-%m-%d.%T.%Z"]
+# Show quoted logged argv here so it's machine readable for replay purposes.
+puts "${::Prog}: timestamp: $timestamp, arguments: $::env(_M0)"
+
+puts "${::Prog}: running drc on topcell: $topcStr"
+puts "${::Prog}: tech-name: [tech name] -version: [tech version] -filename: [tech filename] -lambda [tech lambda]"
+
+# log the cell search path for this run. Emulates format output by plain "path" (but which prints more than one the cell search path).
+puts "Search path for cells is \"[path search]\""
+
+set res {}
+if {$variant != {}} {
+ if {[catch {set res [drc list style $variant]} msg]} {
+ puts "ERROR: ${::Prog}: but CONTINUING, 'drc style $variant' threw error, $msg"
+ }
+} else {
+ if {[catch {set res [drc list style]} msg]} {
+ puts "ERROR: ${::Prog}: but CONTINUING, 'drc list style' threw error, $msg"
+ }
+}
+if {$res != {}} {
+ puts "drc style reports:\n$res"
+}
+
+# just Manhattan is default, turn on euclidean, and log new mode
+drc euclidean on
+drc euclidean
+
+# 1st "select top cell": without it drc-list-count is blank, and error count reduced.
+# May be unnecessary in some cases.
+# WARNING: if topcell locked by another process, default box is NOT set to full top cell without this (as of 8.1.70 or earlier)
+select top cell
+# expand cell cells: scratchify step requires this up front else can't force all cells writable.
+expand
+
+# The expand triggered load of all subcells. Till then allcells may be incomplete.
+set allcells [cellname list allcells]
+# filter (UNNAMED)
+set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+set nbrAllCells [llength $allcells]
+# puts "DEBUG: cellname-list-allcells are: $allcells"
+
+# TODO: do explicit separate unbound check here (don't rely on scratchWritable for this)
+
+# make allcells writable. Can error out:
+# if are unbounds, or couldn't make scratch dir or .mag files.
+set scratch [expr {!$flatten}]
+if {$scratch && [catch {scratchWritable} msg]} {
+ puts stderr "ERROR: ${::Prog}: aborting at scratchWritable due error(s):"
+ error $msg
+}
+
+# Erase all preexisting *.drtcl first. Else when cell transitions from
+# dirty in previous run (leaving *.drtcl), to clean, the old *.drtcl
+# remains.
+# TODO: only delete *.drtcl of cells in 'cellname list allcells'?
+# TODO: move this up, before scratchWritable?
+set files [glob -nocomplain -types {f} -- ./*.drtcl]
+if {$files != {}} {
+ # TODO: detect/report failure details better here?
+ puts "${::Prog}: deleting preexisting *.drtcl"
+ set msg {}
+ set delfail [catch {eval {file delete} $files} msg]
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$delfail || $files != {}} {
+ puts "ERROR: ${::Prog}: failed to clean old ./*.drtcl files. $msg"
+ incr nbrErr
+ }
+}
+
+edit ;# Fails if topcell not writable, should not be not needed post scratchWritable
+
+set outScale [cif scale out]
+
+# "select top cell" and box [view bbox] should be equivalent in
+# placing a box around whole cell extent.
+# The box cmd ALSO prints lambda and micron user-friendly box data,
+# but it prints microns with not enough resolution,
+# (and no option to disable that flawed print out).
+#
+# todo: emulate box output in full, except for higher resolution,
+# here we only scale/print the overall bbox in microns.
+# select top cell ;# paranoid, reset the box to data extents post-expand
+# set bbox [view bbox]
+# set bbs {}
+# foreach oord $bbox {
+# lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+# }
+# puts "outScale: $outScale, view-bbox: $bbox"
+# puts "Root cell box2: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+
+# shouldn't need:
+# drc on
+
+# Want to use 'drc list count' to tell us which cells have errors, so we can
+# run 'drc listall why' on just those cells to enumerate details (which reruns
+# drc again unfortunately).
+
+# For accurate DRC (as of 8.1.70), specifically 'drc list count', need:
+# all-writable cells, then run: 'drc check' & 'drc catchup'.
+# Now we have all writable cells.
+set timeRepeat 1
+if {$perfN > 0} {
+ set timeRepeat $perfN
+}
+set timeres [time {
+ set drcCheckTime1 [time {drc check}]
+ set drcCheckTime2 [time {drc catchup}] } $timeRepeat]
+
+if {$perfN > 0} {
+ puts "perf: ${perfN}X 'drc check','drc catchup': $timeres"
+ puts "perf: last 'drc check' time: $drcCheckTime1"
+ puts "perf: last 'drc catchup' time: $drcCheckTime2"
+ drc statistics
+ drc rulestats
+}
+
+# todo: this 2nd select was in GDS version, test if needed in mag version:
+# 2nd select top cell needed else error count may be reduced (why? bbox does not change due to DRC)
+select top cell
+set outScale [cif scale out]
+set bbox [view bbox]
+set bbs {}
+foreach oord $bbox {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+}
+puts "outScale(ostyle=[cif list ostyle]): $outScale, view-bbox: $bbox"
+puts "Root cell box: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+# print several native bbox representations:
+box
+
+# listall vs list appear same as of 8.1.70 or earlier.
+# warning: celllist order is not stable, not repeatable; run to run on same data.
+# puts "DEBUG: (drc listall count total) is $drcListCountTot"
+set celllist [drc listall count]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist "(UNNAMED)"]
+# puts "DEBUG: (drc listall count) is [drc listall count]"
+set drcListCountTot [drc list count total]
+set nbrErrCells [llength $celllist]
+
+# TODO: major problem: 'drc listall why' repeated an every cell, will do subcells
+# multiple times, as many times as their depth in the hier.
+
+# canonicalize order of celllist, move topc to last (if present whatsoever).
+# force our own artificial entry for topc (zero errors) if not present (was clean)
+# puts "DEBUG: celllist before: $celllist"
+set topcPair [lsearch -inline -index 0 -exact $celllist $topc]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist $topc]
+set celllist [lsort -index 0 -dictionary $celllist]
+if {$topcPair == {}} {
+ # puts "DEBUG: $topc clean, forcing celllist entry for it"
+ set topcPair [list $topc 0]
+}
+lappend celllist $topcPair
+# puts "DEBUG: celllist after: $celllist"
+# puts "DEBUG: adjusted celllist(drc list count) is $celllist"
+
+# loop over celllist
+set doFeedback 1 ;# TODO: add cmd-line option to control this
+
+# collect 'dry listall why' for the cells in 'cell list count' with non-zero errors
+# If 'drc listall why' does report zero (shouldn't since we're only processing cells
+# with non-zero counts), it unavoidably writes to console a No drc errors found message.
+# We don't want such polluting our list of per-cell pareto's, so don't risk running
+# drc why in-line, in-between per-cell paretos.
+array set cell2why [list $topc {}] ;# default at least empty topcell why list
+foreach pair $celllist {
+ if {[lindex $pair 1] < 1} {continue} ;# only happens for topcell if topcell clean
+ set acell [lindex $pair 0]
+
+ # TODO: magic needs a useful error checkable load command.
+ # The 'load' writes errors to console/stdout, but never throws an error,
+ # nor gives a useful return value. i.e. These catch never catch.
+ if {$noderef} {
+ if {[catch {set res [load $acell]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell' threw error, $msg"
+ exit 1
+ }
+ } else {
+ if {[catch {set res [load $acell -dereference]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell -dereference' threw error, $msg"
+ exit 1
+ }
+ }
+ select top cell ;# paranoid, that without it, drc's are reduced
+
+ # optionally do crude DRC perf. analysis here. Only for top-cell, only if -P <N> option given.
+ set timeRepeat 1
+ if {$perfN > 0 && $topc eq $acell} {
+ set timeRepeat $perfN
+ }
+ set timeres [time {set cell2why($acell) [drc listall why]} $timeRepeat]
+ if {$perfN > 0 && $topc eq $acell} {
+ puts "perf: ${::Prog}: for '$acell', ${perfN}X 'drc listall why': $timeres"
+ }
+}
+
+# done with all magic-specifics here. Shouldn't need scratch dir any longer.
+# If this prints something (generally does), don't want it after the pareto table.
+
+# clean/remove the tmp scratch dir and contents
+# TODO: all fatal errors need to call a cleanup proc that includes this before abort
+if {$scratch && [catch {scratchWritable -cleanup} msg]} {
+ puts "ERROR: ${::Prog}: 'scratchWritable -cleanup' threw error, $msg"
+ incr nbrErr
+}
+
+set gtotal 0
+set gcells 0
+foreach pair $celllist {
+ puts ""
+ set acell [lindex $pair 0]
+ if {![info exists cell2why($acell)]} {
+ puts "ERROR: ${::Prog}: cell: $acell, assertion failed, no drc-why list for 'drc list count' pair: $pair"
+ # exit 1
+ continue
+ }
+ set whys $cell2why($acell)
+
+ # enumerate errors under box, plain "drc why" only reports unique types, no quantities
+ # as-yet-undocumented "drc listall why" gives: {errStr1 {errBox1 ...} errStr2 {errBox1 ...} ... }
+ set pareto {}
+ set total 0
+ set enumTotal 0
+ set types 0
+ set typeDup 0
+ set dups 0
+
+ set fbOut {}
+ # file path for feedback, keep in CWD
+ if {$doFeedback && $fbOut == {}} {
+ set fbOut "./$acell.drtcl"
+ if {![file writable $fbOut] &&
+ ([file exists $fbOut] || ![file writable [file dir $fbOut]])} {
+ puts stderr "ERROR: ${::Prog}: feedback output not writable, $fbOut"
+ incr nbrErr
+ set fbOut {}
+ } elseif {[catch {set outfb [open $fbOut w]} msg]} {
+ puts stderr "ERROR: ${::Prog}: failed to truncate previous feedback output, $fbOut : $msg"
+ incr nbrErr
+ set fbOut {}
+ }
+ }
+ foreach {str boxes} $whys {
+ # sort errors
+ set boxes [lsort -dictionary $boxes]
+
+ # for our pareto, gather data
+ set this [llength $boxes]
+ incr total $this
+ incr types
+ lappend pareto [list $this $str]
+
+ # for enumOut, emulate formatting of $CAD_ROOT/magic/tcl/drc.tcl, which is
+ # not tk pure: fails with complaint about winfo
+ # note: we walk these errors also in order to count/report stats on duplicates, even if not outputing enumerations
+ if {[info exists enumOut]} {
+ if {$types == 1} {
+ puts $enumOut "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOut "${str}\n----------------------------------------"
+ }
+ set lastq {}
+ set thisDup 0
+ foreach quad $boxes {
+ set quadUM {}
+ foreach coord $quad {
+ set valum [expr {$coord * $outScale}]
+ set valumf [format "%.3f" $valum]
+ lappend quadUM "${valumf}um"
+ }
+ set dup [expr {$quad == $lastq}]
+ incr thisDup $dup
+ set line $quadUM
+ if {[info exists enumOut]} {
+ if {$dup} {
+ puts $enumOut "[join $line] #dup"
+ } else {
+ puts $enumOut [join $line]
+ }
+ }
+ if {$fbOut != {}} {
+ set line [join $quadUM]
+ regsub -all -- "(\[\[\"\$\\\\])" $str {\\\1} strdq
+ puts $outfb "[concat box $line]" nonewline
+ puts $outfb " ; feedback add \"$strdq\" medium" nonewline
+ if {$dup} {
+ puts $outfb " ;#dup"
+ } else {
+ puts $outfb ""
+ }
+ }
+
+ incr enumTotal
+ set lastq $quad
+ }
+ if {$thisDup} {
+ incr typeDup
+ incr dups $thisDup
+ }
+ if {[info exists enumOut]} {
+ puts $enumOut "----------------------------------------\n"
+ }
+ }
+
+ if {$fbOut != {}} {
+ close $outfb
+ set outfb {}
+ }
+
+ set pareto [lsort -integer -decreasing -index 0 $pareto]
+ if {$total > 0} {
+ puts "--- #err|description, table for cell: $acell"
+ }
+ foreach pair $pareto {
+ puts "[format {%8d} [lindex $pair 0]] [lindex $pair 1]"
+ }
+ if {$typeDup} {
+ puts "[format {%8d} $dups] total duplicate error(s) among $typeDup error type(s), cell: $acell"
+ }
+ puts "[format {%8d} $total] total error(s) among $types error type(s), cell: $acell"
+ # add to grand-totals
+ incr gcells
+ incr gtotal $total
+
+ # always compare the total from the enum to the pareto as error check
+ if {$total != $enumTotal} {
+ puts "ERROR: ${::Prog}: cell: $acell, assertion failed, pareto vs enum count mismatch: $total != $enumTotal"
+ incr nbrErr
+ }
+}
+
+# TODO: in the summary echo also techfile-full-path and drc-style name?
+# grand totals
+puts "[format {%8d} $nbrErrCells] of $nbrAllCells cell(s) report error(s)"
+puts "[format {%8d} $gtotal] grand-total error(s) across $gcells cell(s)"
+
+# wish to compare the drc-list-count-total to the pareto total.
+# Per te 2014-08-27 : it is not an error.
+# if {$total != $drcListCountTot} {
+# puts "info: ${::Prog}: drc-list-count-total vs drc-listall-why mismatch {drc list count total} gave $drcListCountTot, but {drc listall why} gave $total"
+# }
+
+if {[info exists enumOut]} {
+ close $enumOut
+}
+
+# set celllist4 [drc list count]
+# puts "DEBUG: drc list count0: $celllist0"
+# puts "DEBUG: drc list count1: $celllist1"
+# puts "DEBUG: drc list count2: $celllist2"
+# puts "DEBUG: drc list count3: $celllist3"
+# puts "DEBUG: native (drc list count) is $celllistn"
+# puts "DEBUG: drc list count4: $celllist4"
+
+# todo: implement super-pareto, ranked table of SUM of all DRC errs/counts from ALL cells.
+# (It still would not reflect as-if-flat hierarchical expansion due to repetition of instances).
+
+set nbrErr
+}
+
+# non-zero exit-status on errors, either if thrown by main, or counted and returned by main
+set nbrErr 0
+if {[catch {set nbrErr [main $argv]} msg]} {
+ puts stderr $msg
+ set nbrErr 1
+} elseif {$nbrErr > 0} {
+ puts "ERROR: ${::Prog}: script terminated with errors reported above."
+}
+exit $nbrErr
+
+# for emacs syntax-mode:
+# Local Variables:
+# mode:tcl
+# End:
diff --git a/utils/utils/magicGdrc b/utils/utils/magicGdrc
new file mode 100755
index 0000000..88280ee
--- /dev/null
+++ b/utils/utils/magicGdrc
@@ -0,0 +1,911 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2014, 2015, 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (C) 2014, 2015, 2020 efabless Corporation. All Rights Reserved.
+# send a very-first -T FILE to magic's startup, hide all other args from magic-startup
+# for-bash\
+ export _M0= ;\
+ for i in "$@" ; do _M0="$_M0${_M0:+ }\"${i//\"/\\\"}\""; done ;\
+ case "$1" in -T) tch="$2"; shift; shift; _MARGS="$*" exec magic -dnull -noconsole -T "$tch" <"$0" ;; esac
+# hide next line from magic(tclsh):\
+_MARGS="$*" exec magic -dnull -noconsole <"$0"
+#
+# magicDRC: run magic-DRC in batch on a GDS file, tabulate/pareto the error counts.
+#
+# rb@ef 2014-08-28 author
+# rb 2020-02-19 embed some library functions, to standalone from efabless-opengalaxy env, test via magic-8.2.188
+#
+# todo: support "-" as GDS file arg, to mean GDS from stdin
+#
+
+set ::Prog "magicGdrc"
+set argv [eval "list $env(_M0)"] ;# orig. mix of native plus custom args, for logging all args to script
+# set argv [split $env(_MARGS)] ;# (currently unused)
+
+proc usage {args} {
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+ puts {usage: [ -T techfilePath ] [-S <drcStyleName>] [-I <cifIStyleName>] [-km FILE_NAME] [-l FILE_NAME] [-L FILE_NAME] gdsFileName [topCellName]}
+ puts " -T if given, must be very first"
+ puts " -S if given, changes from techfile's default/1st drc style (perhaps \"drc(fast)\") to named style, for example: -S \"drc(full)\""
+ puts " -I if given, changes from techfile's default/1st cifinput style (perhaps \"vendorimport\" or \"import(exact)\") to named style, for example: -I \"import(magic)\""
+ puts " -path-sub do 'gds path subcell yes' (default:no). Make unique subcell for each path: cut #tiles cost of angles."
+ puts " -poly-sub do 'gds polygon subcell yes' (default:no). Make unique subcell for each polygon: cut #tiles cost of angles."
+# gds polygon subcell [yes|no]
+ puts " -pps Short hand, equivalent to giving both: -path-sub -poly-sub"
+ puts ""
+ puts " Error tabulation: By default (slowest, most detail): Report table of counts-by-errorString for all cells."
+ puts " Stdout logs a pareto of error-type by count unless disabled for some/all cells by below; topcell last."
+ puts " -tt Table of counts-by-errorString for ONLY topcell; and just lumped total error count per subcell."
+ puts " -tc Just lumped error counts per cell including topcell (fastest, least detail)."
+ puts " Cells NOT tabulating count-by-errorString can't appear in other output error files: feedback(*.drtcl), -l, -km."
+ puts " For lumped error counts, overlapped error shapes from unique error-types are merged further reducing count."
+ puts ""
+ puts " cell-type +-- (default) --+-- option -tt --+-- option -tc"
+ puts " subcell | count-by-errorString | lumped-error-count | lumped-error-count"
+ puts " topcell | count-by-errorString | count-by-errorString | lumped-error-count"
+ puts ""
+ puts " -km if given, write to FILE_NAME EVERY individual error bbox (MICRONS) in klayout Marker database(XML) format (suggest *.lyrdb)"
+ puts " -l if given, enumerates EVERY individual error bbox (MICRONS) to FILE_NAME, emulates $::CAD_ROOT/magic/tcl/drc.tcl"
+ puts " -L same as -l above, but outputs bbox-es in LAMBDA coordinates, not microns"
+ puts " -nf Do NOT write *.drtcl per-cell feedback files. Can be source-ed in magic and step thru: feedback find."
+ puts ""
+ puts " NOTES: Without explicit tech-file option: the ./.magicrc or ./magic_setup and ~/.magicrc may load a default tech-file."
+ puts " Therefore the tech-file used CAN depend on whether your CWD is ~/design/<CURRENT_DESIGN>/mag when running this script."
+ puts " Since no *.mag are loaded by this script: the cell search path defined by any init files has no impact."
+ puts " Since about 8.3.68, magic may generate error-type \"See error definition in the subcell\". There typically are"
+ puts " redundancies of errors across the hierarchy anyway (but with tech-file err-strings), this seems another form."
+ puts ""
+ puts "example, just list all styles: by causing an error which provokes usage report:"
+ puts " magicGdrc -T /ef/tech/XFAB/EFXH035B/libs.tech/magic/current/EFXH035B.tech"
+ puts "example, same but run in a ~/design/*/mag/ dir, so techfile set by ./.magicrc (else magic's builtin minimum.tech):"
+ puts " magicGdrc"
+ puts "example, run GDS drc, explicit: tech, cif-istyle, drc-style:"
+ puts " magicGdrc -T /ef/tech/SW/EFS8A/libs.tech/magic/current/EFS8A.tech -I vendorimport -S 'drc(full)' /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, default tech & styles, write klayout marker database, no per-cell *.drtcl feedback files:"
+ puts " magicGdrc -km /tmp/mytop.lyrdb -nf /tmp/mytop.gds mytopcell"
+ puts "example, same but make subcells for paths & polygons"
+ puts " magicGdrc -km /tmp/mytop.lyrdb -nf -pps /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, no feedback (*.drtcl), only lumped/merged err-count for all cells"
+ puts " magicGdrc -tc /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, no feedback (*.drtcl), lumped/merged err-count for subcells, detail errors for topcell"
+ puts " magicGdrc -nf -tt /tmp/mytop.gds mytopcell"
+ puts ""
+
+ reportTechFile
+ reportAllStyles
+ puts ""
+
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+}
+proc gdsChk {file} {
+ foreach suffix {"" ".gds" ".gds2" ".strm"} {
+ if {[file readable "${file}${suffix}"]} {return 1}
+ }
+ puts "ERROR: ${::Prog}: Cannot open (as-is or with .gds, .gds2, or .strm) to read GDS-II stream from: $file"
+ exit 1
+}
+
+proc reportTechFile {} {
+ puts "${::Prog}: tech-name: [tech name] -version: [tech version] -filename: [tech filename] -lambda [tech lambda]"
+}
+
+# query currently loaded tech-file for styles the user might need for -I -S options
+# Suggest a bad tech-file if none are found or errors thrown.
+# Used after finding error in -I -S options, and probably should add it to the usage.
+proc reportAllStyles {} {
+ set errs {}
+ if {[catch {set allstyle [cif listall istyle]} msg]} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? failed to 'cif listall istyle', $msg"
+ } elseif {$allstyle == {}} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? no cifinput styles found by 'cif listall istyle'"
+ } else {
+ puts "info: ${::Prog}: cifinput styles available: $allstyle"
+ }
+ if {[catch {set allstyle [drc listall style]} msg]} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? failed to 'drc listall style', $msg"
+ } elseif {$allstyle == {}} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? no drc styles found by 'drc listall style'"
+ } else {
+ puts "info: ${::Prog}: drc styles available: $allstyle"
+ }
+ if {$errs != {}} {
+
+ }
+ return [llength $errs]
+}
+
+# optionally hardcode library proc-s (part of site-wide extensions - always available - in context of efabless/open-galaxy)
+# This is to make the script more standalone from efabless environment; but these capabilities should be native to magic.
+
+if {[info command unbounds] == {}} {
+ puts "${::Prog}: hardcoding library proc-s..."
+# Replacement for 'cellname list exists CELLNAME', to fix ambiguity for cell "0".
+# For cell "0" test for membership in 'cellname list allcells'.
+#
+# Instead of returning 0 for (non-existent) and cellname for exists,
+# returns regular 0/1 instead for non-existent/exists.
+#
+# Therefore NOT direct replacement for uses of 'cellname list exists CELL'.
+# Requires code changes.
+proc cellnameExists {cell} {
+ expr {$cell ne "0" && [cellname list exists $cell] eq $cell ||
+ $cell eq "0" && [lsearch -exact [cellname list allcells] $cell] > -1}
+}
+
+# Walk allcells to get/return list of cellNames that are unbound.
+# Only use this after: 'select top cell; expand' to expand whole hierarchy.
+#
+# foreach CELL in 'cellname list allcells':
+# if flags says available : it's Bound, goto next cell.
+# if filepath is "default", try to expand the cell.
+# if still "default"**: cell made by "cellname create", never saved, goto next.
+# if filepath is CELL.mag, check for "available" flags, if none: Unbound.
+# else cell is bound.
+# **: should never get there
+proc unbounds {} {
+ set allcells [cellname list allcells]
+ # filter (UNNAMED)
+ set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+ # set nbrAllCells [llength $allcells]
+ set ercell {}
+ foreach cell $allcells {
+ # filter (without recording as skipped) non-existent cells.
+ if {![cellnameExists $cell]} { continue }
+
+ # filepath = "default": unexpanded (not loaded from disk),
+ # or created in-mem and never saved (is writable already
+ # though flags won't say so): skip both.
+ # TODO: use a combo of filepath & flags likely can detect created in-mem
+ set tmppath [cellname list filepath $cell]
+ if {$tmppath eq "default"} {
+ lappend skipped $cell
+ continue
+ }
+
+ # flags not meaningful, until expanded or expand attempted.
+ # After expand attempt (filepath != "default"), and flags
+ # can now be used to determine cell unbound: not available.
+ set flags [cellname list flags $cell]
+ if {[lsearch -exact $flags available] < 0} {
+ lappend ercell $cell
+ continue
+ }
+ }
+ set ercell ;# return list of unbound cells, if any
+}
+}
+
+# without top-level proc around bulk of script, intermediate error statements don't abort script.
+proc main {argv} {
+
+set mlen [llength $argv]
+
+# process name-value pair options, if any
+set nbrErr 0
+set ndx 0
+set max [llength $argv]
+set extTechOpt {} ;# -T ... but not used here
+set enumFilel {} ;# -l ... enum output file
+set enumFileL {} ;# -L ... enum output file
+set enumFileKm {} ;# -km ... enum output file
+set variant {} ;# -S ... non-default drc style
+set istyle {} ;# -I ... non-default cifinput style
+set doFeedback 1 ;# -nf sets to 0: Do not write *.drtcl per-cell feedback files.
+set pathSub 0 ;# -path-sub ... do 'gds path subcell yes'
+set polySub 0 ;# -poly-sub ... do 'gds polygon subcell yes'
+set subcellTab 1 ;# -tt, -tc both turn OFF subcell count-by-error report
+set topcellTab 1 ;# -tc turns OFF topcell count-by-error report
+set flatten 0
+while {$ndx < $max && [string match "-*" [lindex $argv $ndx]]} {
+ set opt [lindex $argv $ndx]
+ incr ndx
+ switch -exact -- $opt {
+ -T {
+ if {$ndx != 1} {
+ usage "-T option must very 1st (here was #$ndx)"
+ exit 1
+ }
+ if {$ndx == $max} {
+ usage "missing tech-file argument for -T option"
+ exit 1
+ }
+ set extTechOpt [lindex $argv $ndx] ;# unused
+ incr ndx
+ }
+ -S {
+ if {$ndx == $max} {
+ usage "missing drcStyle argument for -S option"
+ exit 1
+ }
+ set variant [lindex $argv $ndx]
+ incr ndx
+ }
+ -I {
+ if {$ndx == $max} {
+ usage "missing cifinput-style argument for -I option"
+ exit 1
+ }
+ set istyle [lindex $argv $ndx]
+ incr ndx
+ }
+ -F { set flatten 1}
+ -nf { set doFeedback 0 }
+ -path-sub { set pathSub 1}
+ -poly-sub { set polySub 1}
+ -pps { set pathSub 1; set polySub 1}
+ -tt { set subcellTab 0 ; set topcellTab 1}
+ -tc { set subcellTab 0 ; set topcellTab 0 }
+ -km {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -km option"
+ exit 1
+ }
+ set enumFileKm [lindex $argv $ndx]
+ incr ndx
+ }
+ -l {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -l option"
+ exit 1
+ }
+ set enumFilel [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOut [open $enumFilel w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFilel' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFilel"
+ }
+ -L {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -L option"
+ exit 1
+ }
+ set enumFileL [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOutL [open $enumFileL w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFileL' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFileL"
+ }
+ default {
+ usage "unknown option: $opt"
+ exit 1
+ }
+ }
+}
+
+if {$ndx == $max} {
+ usage {Insufficient number of arguments, need gdsFileName [topCellName]}
+ exit 1
+}
+
+set gdsf [lindex $argv $ndx] ; incr ndx
+set topc {}
+set topcStr "(AUTO)"
+if {$ndx < $max} {
+ set topc [lindex $argv $ndx] ; incr ndx
+ set topcStr $topc
+}
+# error if extra options (not understood, something is wrong):
+if {$ndx < $max} {
+ error "ERROR: ${::Prog}: after gdsFile=\"$gdsf\", topcell=\"$topc\" found unsupported extra arguments: [lrange $argv $ndx end]"
+}
+# ndx no longer used for argv position from here
+
+gdsChk $gdsf
+
+# warning on combo of -tc & -km. If -km ok, open its output file.
+if {$enumFileKm ne {}} {
+ if {! $topcellTab} {
+ puts "WARNING: ${::Prog}: with -tc cannot (-km) write klayout-marker-db"
+ } else {
+ if {[catch {set enumOutKm [open $enumFileKm w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFileKm' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFileKm"
+ }
+}
+
+# write a line with timestamp and all arguments to stdout (log)
+# (magic renames the TCL clock command)
+set clockp clock
+if {[info command $clockp] == {} && [info command orig_clock] != {}} {
+ set clockp orig_clock
+}
+set nowSec [$clockp seconds]
+set timestamp [$clockp format $nowSec -format "%Y-%m-%d.%T.%Z"]
+# TODO: quote logged argv here as needed so it's machine readable for replay purposes.
+puts "${::Prog}: timestamp: $timestamp, arguments: $argv"
+
+# just Manhattan is default, turn on euclidean, and log new mode
+drc euclidean on
+drc euclidean
+
+# 8.1.83 this worked:
+# drc off; gds drccheck no; gds read ... ; load topcell; select top cell; expand; drc check; drc update; drc listall count
+# By 8.2.64, that fails, the 'drc listall count' reports errors only in the top-cell, no subcells.
+# 8.1.83 & 8.2.193 this works (gds drccheck defaults to on anyway):
+# drc off; gds drccheck yes; gds read ... ; load topcell; select top cell; expand; drc check; drc update; drc listall count
+#
+# But are we properly avoiding redundant drc runs?
+#
+# turn off background checker. We'll invoke checks explicitly.
+drc off
+gds drccheck yes
+puts "drc status (whether background checking enabled) is: [drc status]"
+puts "gds drccheck (whether gds-read marks new cells as need-drc) is: [gds drccheck]"
+
+# set user's drc style; set user's cifinput istyle
+# These are back-to-back without intervening status messages.
+# If both wrong their errors are back-to-back.
+set res {}
+set res [drc list style]
+if {$variant != {}} {
+ set allstyle [drc listall style]
+ set ndx [lsearch -exact $allstyle $variant]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: drc style '$variant' not one of those available: $allstyle"
+ incr nbrErr
+ } else {
+ set res [drc list style $variant]
+ }
+}
+set res2 [cif list istyle]
+if {$istyle != {}} {
+ set allstyle [cif listall istyle]
+ set ndx [lsearch -exact $allstyle $istyle]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: istyle '$istyle' not one of those available: $allstyle"
+ incr nbrErr
+ } else {
+ set res2 [cif istyle $istyle]
+ }
+}
+if {$res != {}} {
+ puts "drc style reports:\n$res"
+}
+if {$res2 != {}} {
+ puts "cif istyle reports:\n$res2"
+}
+
+# gds {path,polygon} subcell yes
+if {$pathSub != 0} { gds path subcells yes }
+puts "gds path subcells: [gds path subcells]"
+if {$polySub != 0} { gds polygon subcells yes }
+puts "gds polygon subcells: [gds polygon subcells]"
+
+# todo: this catch never happens. Need nicer error check of 'gds read' somehow. Can check for zero-sized file?
+# if use /dev/null for example, it prints its own error message, but no throw, no useful return value.
+puts "doing: gds read $gdsf ..."
+if {[catch {set res [gds read $gdsf]} msg]} {
+ puts "ERROR: ${::Prog}: 'gds read $gdsf' threw error, $msg"
+ incr nbrErr
+}
+# nothing useful:
+# puts "gds-read res: $res"
+
+set topcells [cellname list top]
+set allcells [cellname list allcells]
+# puts "cellname-list-top from GDS is: $topcells"
+# puts "cellname-list-allcells from GDS are: $allcells"
+# filter (UNNAMED)
+set topcells [lsearch -exact -not -all -inline $topcells "(UNNAMED)"]
+set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+set nbrAllCells [llength $allcells]
+
+if {$topcells == {}} {
+ puts "ERROR: ${::Prog}: GDS-read did not report any useful cell name(s) found."
+ incr nbrErr
+}
+
+if {$nbrErr > 0} {
+ return $nbrErr ;# outside of main, we print termination with errors message
+}
+
+if {$topc == {}} {
+ # try and infer topcell from cellname-list-top.
+ # presume its list of cells not placed anywhere else.
+ # todo: test with "library" GDS having more than one topcell
+ # here we just take the last entry
+ set topc [lindex $topcells end]
+ set topcStr $topc
+ puts "WARNING: auto-picked top-cell \"$topc\"; the topcells inferred from GDS are: $topcells"
+} else {
+ # verify input topc argument exists in GDS read result
+ set ndx [lsearch -exact $allcells $topc]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: top-cell name: $topc, not found in GDS"
+ puts "info: top cells inferred from GDS are: $topcells"
+ puts "info: all cells inferred from GDS are: $allcells"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+}
+
+puts "${::Prog}: running drc on -gds: $gdsf -topcell: $topcStr"
+reportTechFile
+
+# todo: need to error check load command somehow (no useful return value).
+# it can fail with error message (in log) like:
+# File dne.mag couldn't be found
+# Creating new cell
+if {[catch {set res [load $topc]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $topc' threw error (maybe cellName not found in GDS?), $msg"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+}
+# nothing useful:
+# puts "load $topc res: $res"
+
+if {$flatten} {
+ # delete (UNNAMED) if any.
+ set trg "(UNNAMED)"
+ if {[cellnameExists $trg]} {cellname delete $trg}
+
+ # rename top cell to (UNNAMED)
+ cellname rename $topc $trg
+
+ # now Edit Cell contents are original top cell, but under name (UNNAMED)
+ # flatten Edit-Cell into original top cell name
+ puts "${::Prog}: flattening..."
+ flatten $topc
+
+ # load and edit new version of top cell
+ load $topc
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ puts "ERROR: ${::Prog}: assertion failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+
+ # should not be necessary:
+ select top cell
+ edit
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ puts "ERROR: ${::Prog}: assertion-2 failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+}
+
+# Erase all preexisting *.drtcl first. Else when cell transitions from
+# dirty in previous run (leaving *.drtcl), to clean, the old *.drtcl
+# remains.
+# TODO: only delete *.drtcl of cells in 'cellname list allcells'?
+if {$doFeedback} {
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$flatten} {
+ # only delete topcell's .drtcl in flatten mode, if there is one
+ set files [lsearch -all -inline -exact $files ./$topc.drtcl]
+ }
+ if {$files != {}} {
+ # TODO: detect/report failure details better here?
+ puts "${::Prog}: deleting preexisting *.drtcl"
+ set msg {}
+ set delfail [catch {eval {file delete} $files} msg]
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$delfail || $files != {}} {
+ puts "ERROR: ${::Prog}: failed to clean old ./*.drtcl files. $msg"
+ incr nbrErr
+ }
+ }
+}
+
+# 1st "select top cell": without it drc-list-count is blank, and error count reduced.
+select top cell
+
+set bbox0 [view bbox]
+set outScale [cif scale out]
+
+# set bbox1 [view bbox]
+
+# "select top cell" and box [view bbox] should be equivalent in
+# placing a box around whole cell extent.
+# The box cmd ALSO prints lambda and micron user-friendly box data,
+# but it prints microns with not enough resolution,
+# (and no option to disable that flawed print out).
+#
+# todo: emulate box output in full, except for higher resolution,
+# here we only scale/print the overall bbox in microns.
+set bbs {}
+foreach oord $bbox0 {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+}
+puts "info: outScale: [format "%.6f" $outScale], view-bbox: $bbox0"
+puts "info: Root cell box: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+
+drc check
+drc catchup
+drc statistics
+drc rulestats
+# puts "doing plain: drc count"
+drc count
+
+# 2nd select top cell needed else error count may be reduced (why? bbox does not change due to DRC)
+select top cell
+
+set celllist [drc listall count]
+set drcListCountTot [drc list count total]
+# puts stdout "(drc listall count) is << " nonewline; puts stdout [list $celllist] nonewline; puts " >>"
+# puts stdout "(drc list count) is << " nonewline; puts stdout [list [drc list count]] nonewline; puts " >>"
+# puts stdout "(drc list count total) is << " nonewline; puts stdout [list $drcListCountTot] nonewline; puts " >>"
+# puts stdout "(drc listall count total) is << " nonewline; puts stdout [list [drc listall count total]] nonewline; puts " >>"
+# puts stdout "(drc list why) is << " nonewline; puts stdout [list [drc list why]] nonewline; puts " >>"
+# puts stdout "(drc listall why) is << " nonewline; puts stdout [list [drc listall why]] nonewline; puts " >>"
+
+set bbox2 [view bbox]
+if {$bbox2 != $bbox0} {
+ set bbs {}
+ foreach oord $bbox2 {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+ }
+ puts "info: outScale: [format "%.6f" $outScale], view-bbox: $bbox2"
+ puts "info: Root cell box2: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+}
+
+
+# canonicalize order of celllist, move topc to last (if present whatsoever).
+# force our own artificial entry for topc (zero errors) if not present (was clean)
+# puts "celllist before: $celllist"
+set nbrErrCells [llength $celllist]
+set topcPair [lsearch -inline -index 0 -exact $celllist $topc]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist $topc]
+set celllist [lsort -index 0 -dictionary $celllist]
+if {$topcPair == {}} {
+ # puts "info: ${::Prog}: $topc clean, forcing celllist entry for it"
+ set topcPair [list $topc 0]
+}
+lappend celllist $topcPair
+# puts stdout "adjusted celllist(drc list count) is << " nonewline; puts stdout $celllist nonewline; puts " >>"
+
+array set kmErr2catNm {}
+array set kmErr2catDesc {}
+array set kmCell2item {}
+if {$celllist != {} && [info exists enumOutKm]} {
+ # Header example of .lyrdb klayout Marker format
+ # <?xml version="1.0" encoding="utf-8"?>
+ # <report-database>
+ # <description>Diff of 'x.gds, Cell RINGO' vs. 'x.gds[1], Cell INV2'</description>
+ # <original-file/>
+ # <generator/>
+ # <top-cell>RINGO</top-cell>
+ # <tags>
+ # <tag>
+ # <name>red</name>
+ # <description>Red flag</description>
+ # </tag>
+ # ...
+ # </tags>
+
+ puts $enumOutKm {<?xml version="1.0" encoding="utf-8"?><report-database>}
+ puts $enumOutKm "<description>$topc DRC timestamp: $timestamp, arguments: $argv</description>"
+ puts $enumOutKm {<original-file/><generator/>}
+ puts $enumOutKm "<top-cell>$topc</top-cell>"
+ puts $enumOutKm {<tags/>}
+ puts $enumOutKm {<cells>}
+
+ # multiple <cells>...</cells> sections do accumulate, but cells and categories need
+ # to be defined before use in an item (specific error), and we know cell names here,
+ # so declare all cells to klayout here.
+ #
+ # Cell-specific header of klayout marker file
+ # <cell>
+ # <name>CELLNAME1</name>
+ # <variant>1</variant> (don't need)
+ # </cell>
+ #
+ foreach pair $celllist {
+ set acell [lindex $pair 0]
+
+ # for -tt, no subcell error-detail: don't write subcells in <cells>...</cells> section.
+ if {$acell ne $topc && ! $subcellTab} { continue }
+
+ puts $enumOutKm " <cell><name>$acell</name></cell>"
+ set kmCell2item($acell) {}
+ }
+ puts $enumOutKm {</cells>}
+}
+
+# loop over celllist
+set gtotal 0
+set gcells 0
+set lumpedHeader 0
+foreach pair $celllist {
+ set acell [lindex $pair 0]
+ set acount [lindex $pair 1]
+
+ if {$acell ne $topc && ! $subcellTab} {
+ if {! $lumpedHeader} {
+ puts "--- #err|cell, lumped total counts"
+ set lumpedHeader 1
+ }
+ puts "[format {%8d} $acount] $acell"
+ incr gcells
+ incr gtotal $acount
+ continue
+ }
+ if {$acell eq $topc && ! $topcellTab} {
+ if {! $lumpedHeader} {
+ puts "--- #err|cell, lumped total counts"
+ set lumpedHeader 1
+ }
+ puts "[format {%8d} $acount] $acell"
+ incr gcells
+ incr gtotal $acount
+ continue
+ }
+ puts ""
+
+ # todo: need useful error check of load command
+ if {[catch {set res [load $acell]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell' threw error, $msg"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+
+ # instead use quiet version for per-cell selects
+ select top cell
+
+ set drcListCountTot [drc listall count total]
+
+ # enumerate errors under box, plain "drc why" only reports unique types, no quantities
+ # as-yet-undocumented "drc listall why" will give: {errStr1 {errBox1 ...} errStr2 {errBox1 ...} ... }
+ set pareto {}
+ set total 0
+ set enumTotal 0
+ set types 0
+ set typeDup 0
+ set dups 0
+
+ set fbOut {}
+ if {$acount != 0} {
+ # file path for feedback, keep in CWD
+ if {$doFeedback && $fbOut == {}} {
+ set fbOut "./$acell.drtcl"
+ if {![file writable $fbOut] &&
+ ([file exists $fbOut] || ![file writable [file dir $fbOut]])} {
+ puts stderr "ERROR: ${::Prog}: feedback output not writable, $fbOut"
+ incr nbrErr
+ set fbOut {}
+ } elseif {[catch {set outfb [open $fbOut w]} msg]} {
+ puts stderr "ERROR: ${::Prog}: failed to truncate previous feedback output, $fbOut : $msg"
+ incr nbrErr
+ set fbOut {}
+ }
+ }
+
+ foreach {str boxes} [drc listall why] {
+ # sort errors
+ set boxes [lsort -dictionary $boxes]
+ # for our pareto, gather data
+ set this [llength $boxes]
+ incr total $this
+ incr types
+ lappend pareto [list $this $str]
+
+ # for enumOut, emulate formatting of $CAD_ROOT/magic/tcl/drc.tcl, which is
+ # not tk pure: fails with complaint about winfo
+ # note: we walk these errors also in order to count/report stats on duplicates, even if not outputing enumerations
+ if {[info exists enumOut]} {
+ if {$types == 1} {
+ puts $enumOut "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOut "${str}\n----------------------------------------"
+ }
+ if {[info exists enumOutL]} {
+ if {$types == 1} {
+ puts $enumOutL "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOutL "${str}\n----------------------------------------"
+ }
+ if {[info exists enumOutKm]} {
+ # category names must be declared all together up front before use in items
+ # so we only store their names (error strings) and error detail (items)
+ # to dump after all cells and errors are processed.
+ # TODO: Only quote catName in item if embeds dot, instead of full-time
+ # TODO: test klayout handles literal (non-entity) single-quote in double-quoted name
+ set strKmNm $str
+ set strKmDesc $str
+ regsub -all -- {&} $strKmDesc {\&} strKmDesc ;# perhaps not needed; just in case
+ regsub -all -- {<} $strKmDesc {\<} strKmDesc ;# description does not have such bug, so use correct entity
+ regsub -all -- {>} $strKmDesc {\>} strKmDesc ;# perhaps not needed; just in case
+ regsub -all -- {&} $strKmNm {-and-} strKmNm ;# perhaps not needed; just in case
+ regsub -all -- {>} $strKmNm {-gt-} strKmNm ;# perhaps not needed; just in case
+ regsub -all -- {<} $strKmNm {-lt-} strKmNm ;# catName klayout bug: info win truncates at '<' as < entity
+ regsub -all -- "\"" $strKmNm {'} strKmNm ;# we dqoute each catNm in item, so change embedded double to single
+ set kmErr2catNm($str) $strKmNm
+ set kmErr2catDesc($str) $strKmDesc
+ #
+ # example klayout Marker format, header of one item (one error instance)
+ # <item>
+ # <tags/> (don't need?)
+ # <image/> (don't need?)
+ # <category>'DRC-MSG-STR'</category> (cat1.cat2 path delimit by dot: names with dot need single|double quotes)
+ # <cell>RINGO:1</cell> (don't need :N variant suffix)
+ # <visited>false</visited> (optional? start with false?)
+ # <multiplicity>1</multiplicity> (not boolean, if error "represents" more that are NOT enumerated)
+ # <values> ... </values>
+ # </item>
+
+ set itemStr "<item><category>\"$strKmNm\"</category><cell>$acell</cell><values>"
+ }
+ set lastq {}
+ set thisDup 0
+ foreach quad $boxes {
+ set quadUM {}
+ set kmBoxUM {}
+ foreach coord $quad {
+ set valum [expr {$coord * $outScale}]
+ set valumf [format "%.3f" $valum]
+ lappend quadUM "${valumf}um"
+ lappend kmBoxUM ${valumf}
+ }
+ set dup [expr {$quad == $lastq}]
+ incr thisDup $dup
+ set line $quadUM
+ if {[info exists enumOut]} {
+ if {$dup} {
+ puts $enumOut "[join $line] #dup"
+ } else {
+ puts $enumOut [join $line]
+ }
+ }
+ if {[info exists enumOutL]} {
+ if {$dup} {
+ puts $enumOutL "$quad #dup"
+ } else {
+ puts $enumOutL $quad
+ }
+ }
+ if {[info exists enumOutKm]} {
+ # <value>text: 'item: polygon'</value> (text is optional? Repeat the box coordinates here in um?)
+ # <value>polygon: (1.4,1.8;-1.4,1.8;-1.4,3.8;1.4,3.8)</value>
+ # <value>box: (1.4,1.8;-1.4,3.8)</value>
+ # </values>
+ set kmItem $itemStr
+ append kmItem " <value>box: ([lindex $kmBoxUM 0],[lindex $kmBoxUM 1];[lindex $kmBoxUM 2],[lindex $kmBoxUM 3])</value>"
+ if {$dup} {
+ append kmItem " <value>text: 'dup'</value>"
+ }
+ append kmItem " </values></item>"
+ lappend kmCell2item($acell) $kmItem
+ }
+ if {$fbOut != {}} {
+ set line [join $quadUM]
+ regsub -all -- "(\[\[\"\$\\\\])" $str {\\\1} strdq
+ puts $outfb "[concat box $line]" nonewline
+ puts $outfb " ; feedback add \"$strdq\" medium" nonewline
+ if {$dup} {
+ puts $outfb " ;#dup"
+ } else {
+ puts $outfb ""
+ }
+ }
+
+ incr enumTotal
+ set lastq $quad
+ }
+ if {$thisDup} {
+ incr typeDup
+ incr dups $thisDup
+ }
+ if {[info exists enumOut]} {
+ puts $enumOut "----------------------------------------\n"
+ }
+ if {[info exists enumOutL]} {
+ puts $enumOutL "----------------------------------------\n"
+ }
+ }
+ }
+
+ if {$fbOut != {}} {
+ close $outfb
+ set outfb {}
+ }
+
+ set pareto [lsort -integer -decreasing -index 0 $pareto]
+ if {$total > 0} {
+ puts "--- #err|description, table for cell: $acell"
+ }
+ foreach pair $pareto {
+ puts "[format {%8d} [lindex $pair 0]] [lindex $pair 1]"
+ }
+ if {$typeDup} {
+ puts "[format {%8d} $dups] total duplicate error(s) among $typeDup error type(s), cell: $acell"
+ }
+ puts "[format {%8d} $total] total error(s) among $types error type(s), cell: $acell"
+ # add to grand-totals
+ incr gcells
+ incr gtotal $total
+
+ # always compare the total from the enum to the pareto as error check
+ if {$total != $enumTotal} {
+ puts "ERROR: ${::Prog}: cell: $acell, internal error, pareto vs enum count mismatch: $total != $enumTotal"
+ incr nbrErr
+ }
+ # wish to compare the drc-list-count-total to the pareto total.
+ # Per te 2014-08-27 : it is not an error.
+ if {$total != $drcListCountTot} {
+ # puts "info: ${::Prog}: cell: $acell, drc-list-count-total vs drc-listall-why mismatch {drc list count total} gave $drcListCountTot, but {drc listall why} gave $total"
+ }
+}
+
+# grand totals
+puts "[format {%8d} $nbrErrCells] of $nbrAllCells cell(s) report error(s)"
+puts "[format {%8d} $gtotal] grand-total error(s) across $gcells cell(s)"
+
+if {[info exists enumOut]} {
+ close $enumOut
+}
+if {[info exists enumOutL]} {
+ close $enumOutL
+}
+if {[info exists enumOutKm]} {
+ # declare all category names and descriptions, note '<' in name vs description are represented differently
+ #
+ # <categories><category><name>layerN width -lt- 1.0um</name>
+ # <description>layerN width < 1.0um</description></category>
+ # <category> ... </category></categories>
+ #
+ puts $enumOutKm "<categories>"
+ foreach errStr [array names kmErr2catNm] {
+ set nm $kmErr2catNm($errStr)
+ set desc $kmErr2catDesc($errStr)
+ puts $enumOutKm " <category><name>$nm</name><description>$desc</description></category>"
+ }
+ puts $enumOutKm "</categories>"
+
+ # dump all items (after all cells and all categories have been defined up front)
+ puts $enumOutKm "<items>"
+ foreach {acell items} [array get kmCell2item] {
+ foreach item $items {
+ puts $enumOutKm $item
+ }
+ }
+ puts $enumOutKm "</items>"
+
+ # footer example .lyrdb klayout Marker file
+ # </report-database>
+ puts $enumOutKm {</report-database>}
+ close $enumOutKm
+}
+# todo: implement super-pareto, ranked table of SUM of all DRC errs/counts from ALL cells.
+# (It still would not reflect as-if-flat hierarchical expansion due to repetition of instances).
+
+set nbrErr ;# return value
+} ;# end main
+
+# non-zero exit-status on errors, either if thrown by main, or counted and returned by main
+set nbrErr 0
+if {[catch {set nbrErr [main $argv]} msg]} {
+ puts stderr $msg
+ set nbrErr 1
+} elseif {$nbrErr > 0} {
+ puts "ERROR: ${::Prog}: script terminated with errors reported above."
+}
+exit $nbrErr
+
+# for emacs syntax-mode:
+# Local Variables:
+# mode:tcl
+# End:
diff --git a/utils/utils/parse_klayout_xor_log.py b/utils/utils/parse_klayout_xor_log.py
new file mode 100644
index 0000000..842b484
--- /dev/null
+++ b/utils/utils/parse_klayout_xor_log.py
@@ -0,0 +1,42 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import re
+
+parser = argparse.ArgumentParser(
+ description='extracts the total xor differnces from an xor log')
+
+parser.add_argument('--log_file', '-l',required=True,
+ help='log file')
+
+parser.add_argument('--output', '-o', required=True,
+ help='output file to store results')
+
+args = parser.parse_args()
+log_file_name = args.log_file
+out_file_name = args.output
+
+string = "XOR differences:"
+pattern = re.compile(r'\s*%s\s*([\d+]+)' % string)
+tot_cnt = 0
+with open(log_file_name, "r") as f:
+ for line in f:
+ m = pattern.match(line)
+ if m:
+ tot_cnt += int(m.group(1))
+
+outFileOpener = open(out_file_name, "w")
+outFileOpener.write("Total XOR differences = "+ str(tot_cnt))
+outFileOpener.close()
diff --git a/utils/utils/scrotLayout.py b/utils/utils/scrotLayout.py
new file mode 100644
index 0000000..5469d19
--- /dev/null
+++ b/utils/utils/scrotLayout.py
@@ -0,0 +1,58 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import pya
+import re
+import os
+
+WIDTH = 2048
+HEIGHT = 2048
+
+app = pya.Application.instance()
+win = app.main_window()
+
+# Load technology file
+print('[INFO] Reading tech file: ' + str(tech_file))
+tech = pya.Technology()
+tech.load(tech_file)
+
+layoutOptions = tech.load_layout_options
+
+# Load def file in the main window
+print('[INFO] Reading Layout file: ' + str(input_layout))
+cell_view = win.load_layout(input_layout, layoutOptions, 0)
+layout_view = cell_view.view()
+
+layout_view.load_layer_props(os.path.splitext(tech_file)[0]+'.lyp')
+
+layout_view.max_hier()
+# layout_view.clear_layers()
+
+# Hide layers with these purposes
+hidden_purposes = [0, 4, 5]
+
+li = layout_view.begin_layers()
+while not li.at_end():
+ lp = li.current()
+ if lp.source_datatype in hidden_purposes:
+ new_lp = lp.dup()
+ new_lp.visible = False
+ layout_view.set_layer_properties(li, new_lp)
+
+ li.next()
+
+print("[INFO] Writing out PNG screenshot '{0}'".format(input_layout+".png"))
+layout_view.save_image(input_layout+".png", WIDTH, HEIGHT)
+print("Done")
+app.exit(0)
diff --git a/utils/utils/scrotLayout.sh b/utils/utils/scrotLayout.sh
new file mode 100644
index 0000000..d833783
--- /dev/null
+++ b/utils/utils/scrotLayout.sh
@@ -0,0 +1,31 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set -e
+
+: ${1?"Usage: $0 tech_file input"}
+: ${2?"Usage: $0 tech_file input"}
+
+echo "Using Techfile: $1"
+echo "Using layout file: $2"
+
+# The -a here is necessary to handle race conditions.
+# This limits the max number of possible jobs to 100.
+xvfb-run -a klayout -z \
+ -rd input_layout=$2 \
+ -rd tech_file=$1 \
+ -rm $(dirname $0)/scrotLayout.py
+
+exit 0
diff --git a/utils/utils/xor.drc b/utils/utils/xor.drc
new file mode 100644
index 0000000..6caee91
--- /dev/null
+++ b/utils/utils/xor.drc
@@ -0,0 +1,42 @@
+# A general XOR script
+# (https://www.klayout.de/forum/discussion/100/xor-vs-diff-tool)
+# This script uses KLayout's DRC language to implement a generic
+# XOR between two layouts. The name of the layouts is given
+# in $a and $b.
+
+# For layout-to-layout XOR with multiple cores, run this script with
+# ./klayout -r xor.drc -rd thr=NUM_CORES -rd top_cell=TOP_CELL_NAME -rd a=a.gds -rd b=b.gds -rd ol=xor.gds -zz
+# (replace NUM_CORES by the desired number of cores to utilize
+
+# enable timing output
+verbose
+
+# set up input a
+a = source($a, $top_cell)
+
+# set up input b
+b = source($b, $top_cell)
+
+$o && $ext != "gds" && report("XOR #{$a} vs. #{$b}", $o)
+$ol && $ext == "gds" && target($ol, $co || "XOR")
+
+$thr && threads($thr) || threads(2)
+
+# collect all common layers
+layers = {}
+[ a.layout, b.layout ].each do |ly|
+ ly.layer_indices.each do |li|
+ i = ly.get_info(li)
+ layers[i.to_s] = i
+ end
+end
+
+# perform the XOR's
+layers.keys.sort.each do |l|
+ i = layers[l]
+ info("--- Running XOR for #{l} ---")
+ x = a.input(l) ^ b.input(l)
+ info("XOR differences: #{x.data.size}")
+ $o && $ext != "gds" && x.output(l, "XOR results for layer #{l} #{i.name}")
+ $ol && $ext == "gds" && x.output(i.layer, i.datatype, i.name)
+end
diff --git a/utils/utils/xor.sh b/utils/utils/xor.sh
new file mode 100644
index 0000000..3ea5176
--- /dev/null
+++ b/utils/utils/xor.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+: ${1?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${2?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${3?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${4?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+
+
+echo "First Layout: $1"
+echo "Second Layout: $2"
+echo "Design Name: $3"
+echo "Output GDS will be: $4"
+
+xvfb-run -a klayout -r $(dirname $0)/xor.drc \
+ -rd top_cell=$3 \
+ -rd a=$1 \
+ -rd b=$2 \
+ -rd thr=$(nproc) \
+ -rd ol=$4 \
+ -rd o=$4 \
+ -rd ext=${4##*.} \
+ -zz
diff --git a/verilog/dv/caravel/caravel/defs.h b/verilog/dv/caravel/caravel/defs.h
new file mode 100644
index 0000000..59d4369
--- /dev/null
+++ b/verilog/dv/caravel/caravel/defs.h
@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
+#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
+#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
+#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0 0x00000001
+#define FLASH_BITBANG_IO1 0x00000002
+#define FLASH_BITBANG_CLK 0x00000010
+#define FLASH_BITBANG_CSB 0x00000020
+#define FLASH_BITBANG_OEB0 0x00000100
+#define FLASH_BITBANG_OEB1 0x00000200
+#define FLASH_ENABLE 0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE 0x01
+#define TIMER_ONESHOT 0x02
+#define TIMER_UPCOUNT 0x04
+#define TIMER_CHAIN 0x08
+#define TIMER_IRQ_ENABLE 0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK 0x00ff
+#define SPI_MASTER_MLB 0x0100
+#define SPI_MASTER_INV_CSB 0x0200
+#define SPI_MASTER_INV_CLK 0x0400
+#define SPI_MASTER_MODE_1 0x0800
+#define SPI_MASTER_STREAM 0x1000
+#define SPI_MASTER_ENABLE 0x2000
+#define SPI_MASTER_IRQ_ENABLE 0x4000
+#define SPI_HOUSEKEEPING_CONN 0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE 0x0001
+#define OUTPUT_DISABLE 0x0002
+#define HOLD_OVERRIDE 0x0004
+#define INPUT_DISABLE 0x0008
+#define MODE_SELECT 0x0010
+#define ANALOG_ENABLE 0x0020
+#define ANALOG_SELECT 0x0040
+#define ANALOG_POLARITY 0x0080
+#define SLOW_SLEW_MODE 0x0100
+#define TRIPPOINT_SEL 0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802
+#define GPIO_MODE_USER_STD_ANALOG 0x000a
+
+// --------------------------------------------------------
+#endif
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/Makefile
new file mode 100644
index 0000000..c7fd2d9
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/Makefile
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio mem uart perf hkspi sysctrl mprj_ctrl pass_thru timer timer2 pll storage
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/gpio/Makefile
new file mode 100644
index 0000000..5724f98
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/gpio/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/gpio/README b/verilog/dv/caravel/caravel/mgmt_soc/gpio/README
new file mode 100644
index 0000000..baadc1f
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/gpio/README
@@ -0,0 +1,44 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio testbench
+------------------------------------------------
+
+This testbench exercises the fundamental use of the Caravel
+management SoC to drive the I/O in the user area as general
+purpose I/O on startup.
+
+On startup, all GPIO are configured as input to the management
+region (so as to be high impedence to the external world) and
+decoupled from the user project area.
+
+To configure any GPIO as output, the appropriate memory-mapped
+location for the I/O must be properly configured. Since the
+I/O configuration is stored in two places, in the SoC, but
+also locally at each I/O pad, the "transfer" bit must be
+applied, which initiates a transfer of the configuration data
+around the padframe.
+
+The testbench takes 16 pins from the user area and checks
+functionality by applying input values on 8 of these pins from
+the testbench verilog, detecting them in the C program, then
+copying the values to the other 8 pins, and detecting those
+values in the testbench verilog.
+
+If any of that does not work, then the testbench will fail.
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio.c
new file mode 100644
index 0000000..73dd397
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio.c
@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xab000000;
+
+ while (1){
+ int x = (reg_mprj_datal & 0xff0000) >> 16;
+ reg_mprj_datal = (x+1) << 24;
+ }
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio_tb.v
new file mode 100644
index 0000000..de2aaac
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -0,0 +1,195 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("gpio.vcd");
+ $dumpvars(0, gpio_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ checkbits_lo <= {8{1'bz}};
+ wait(checkbits_hi == 8'hA0);
+ checkbits_lo <= 8'hF0;
+ wait(checkbits_hi == 8'h0B);
+ checkbits_lo <= 8'h0F;
+ wait(checkbits_hi == 8'hAB);
+ checkbits_lo <= 8'h0;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h1;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h3;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 8'hA0);
+ wait(checkbits[7:0] == 8'hF0);
+ wait(checkbits_hi == 8'h0B);
+ wait(checkbits[7:0] == 8'h0F);
+ wait(checkbits_hi == 8'hAB);
+ wait(checkbits[7:0] == 8'h00);
+ wait(checkbits_hi == 8'h01);
+ wait(checkbits[7:0] == 8'h01);
+ wait(checkbits_hi == 8'h02);
+ wait(checkbits[7:0] == 8'h03);
+ wait(checkbits_hi == 8'h04);
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/Makefile
new file mode 100644
index 0000000..1695a45
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = hkspi
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi.c b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi.c
new file mode 100644
index 0000000..3bfac32
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed, to show that the
+ // processor is interrupted only when the reset is applied
+ // through the SPI.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test message
+ print("\n");
+ print(" ____ _ ____ ____\n");
+ print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
+ print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+ print(" | __/| | (_| (_) |__) | (_) | |___\n");
+ print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi_tb.v
new file mode 100644
index 0000000..a0176fa
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -0,0 +1,430 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ StriVe housekeeping SPI testbench.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("hkspi.vcd");
+ $dumpvars(0, hkspi_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ // Delay, then bring chip out of reset
+ #1000;
+ RSTB <= 1'b1;
+ #2000;
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+
+ // Toggle external reset
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h07); // Address (register 7 = external reset)
+ write_byte(8'h01); // Data = 0x01 (apply external reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h07); // Address (register 7 = external reset)
+ write_byte(8'h00); // Data = 0x00 (release external reset)
+ end_csb();
+
+ // Read all registers (0 to 18)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h00); // Address (register 3 = product ID)
+ read_byte(tbdata);
+
+ $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+ if(tbdata !== 8'h56) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
+ if(tbdata !== 8'h02) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+ if(tbdata !== 8'hef) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+ if(tbdata !== 8'h03) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+ if(tbdata !== 8'h12) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("hkspi.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/mem/Makefile
new file mode 100644
index 0000000..2be8c42
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mem/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/caravel/mgmt_soc/mem/mem.c
new file mode 100644
index 0000000..a3b6fcc
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mem/mem.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Memory Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[10];
+unsigned short shorts[10];
+unsigned char bytes[10];
+
+void main()
+{
+ int i;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Word R/W
+ for (i=0; i<10; i++)
+ ints[i] = i*5000 + 10000;
+
+ for (i=0; i<10; i++)
+ if ((i*5000+10000) != ints[i])
+ reg_mprj_datal = 0xAB400000;
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Half Word R/W
+ reg_mprj_datal = 0xA0200000;
+ for (i=0; i<10; i++)
+ shorts[i] = i*500 + 100;
+
+ for(i=0; i<10; i++)
+ if((i*500+100) != shorts[i])
+ reg_mprj_datal = 0xAB200000;
+
+ reg_mprj_datal = 0xAB210000;
+
+ // Test byte R/W
+ reg_mprj_datal = 0xA0100000;
+ for(i=0; i<10; i++)
+ bytes[i] = i*5 + 10;
+
+ for(i=0; i<10; i++)
+ if((i*5+10) != bytes[i])
+ reg_mprj_datal = 0xAB100000;
+
+ reg_mprj_datal = 0xAB110000;
+}
\ No newline at end of file
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/mem/mem_tb.v
new file mode 100644
index 0000000..9abcf76
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mem/mem_tb.v
@@ -0,0 +1,202 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mem_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mem.vcd");
+ $dumpvars(0, mem_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test MEM (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test MEM (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ $display("Mem Test (word rw) started");
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ $display("Mem Test (short rw) started");
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA010) begin
+ $display("Mem Test (byte rw) started");
+ end
+ else if(checkbits == 16'hAB10) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB11) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] passed");
+ `endif
+ $finish;
+ end
+
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mem.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..64e99ed
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..1d7a140
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * User Project IO Control Test
+ */
+
+void main()
+{
+ /* All GPIO pins are configured to be output */
+ /* The lower 28 bits are connected to the user */
+ /* project to output the counter result, and the */
+ /* upper 4 bits are connected to the management */
+ /* SoC to apply values that can be flagged by the */
+ /* testbench for specific benchmark tests. */
+
+ /* GPIOs 31 to 16 are connected to the management SoC */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* GPIOs 27 to 0 are connected to the user area */
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0x50000000;
+
+ // Write to IO Control
+ reg_mprj_io_0 = 0x004F;
+ if (reg_mprj_io_0 != 0x004F)
+ reg_mprj_datal = 0x60000000;
+ else
+ reg_mprj_datal = 0x70000000;
+
+ // Write to IO Control
+ reg_mprj_io_1 = 0x005F;
+ if (reg_mprj_io_1 != 0x005F)
+ reg_mprj_datal = 0x80000000;
+ else
+ reg_mprj_datal = 0x90000000;
+
+ // Write to IO Control
+ reg_mprj_io_2 = 0x006F;
+ if (reg_mprj_io_2 != 0x006F)
+ reg_mprj_datal = 0xA0000000;
+ else
+ reg_mprj_datal = 0xb0000000;
+
+ // Write to IO Control (NOTE: Only 13 bits are valid)
+ reg_mprj_io_3 = 0xF0F5;
+ if (reg_mprj_io_3 != 0x10F5)
+ reg_mprj_datal = 0xc0000000;
+ else
+ reg_mprj_datal = 0xd0000000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..cc619dd
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,175 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mprj_ctrl_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] user_io;
+ wire SDO;
+
+ wire [3:0] checkbits;
+
+ assign checkbits = user_io[31:28];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_ctrl.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test User Project (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test User Project (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 4'h5) begin
+ $display("User Project control Test started");
+ end else if(checkbits == 4'h6) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: IO control R/W failed (check 6)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h7) begin
+ $display("Monitor: IO control R/W passed (check 7)");
+ end else if(checkbits == 4'h8) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 8)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h9) begin
+ $display("Monitor: power control R/W passed (check 9)");
+ end else if(checkbits == 4'ha) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 10)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hb) begin
+ $display("Monitor: power control R/W passed (check 11)");
+ end else if(checkbits == 4'hc) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 12)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hd) begin
+
+ $display("Monitor: power control R/W passed (check 13)");
+ `ifdef GL
+ $display("Monitor: User Project control (GL) test passed.");
+ `else
+ $display("Monitor: User Project control (RTL) test passed.");
+ `endif
+ $finish;
+ end
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(gpio) begin
+ #1 $display("GPIO state = %b ", gpio);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign user_io[3] = 1'b1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (user_io),
+ .flash_csb (flash_csb),
+ .flash_clk (flash_clk),
+ .flash_io0 (flash_io0),
+ .flash_io1 (flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mprj_ctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/Makefile
new file mode 100644
index 0000000..3129a90
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_stimulus
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus.c b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus.c
new file mode 100644
index 0000000..24088d2
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus.c
@@ -0,0 +1,146 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+// #include "../../stub.c"
+// #include "../../fpga_top.h"
+
+// --------------------------------------------------------
+
+/*
+ MPRJ Logic Analyzer Test:
+ - Observes counter value through LA probes [31:0]
+ - Sets counter initial value through LA probes [63:32]
+ - Flags when counter value exceeds 500 through the management SoC gpio
+ - Outputs message to the UART when the test concludes successfuly
+*/
+
+
+void main()
+{
+ // The upper GPIO pins are configured to be output
+ // and accessble to the management SoC.
+ // Used to flad the start/end of a test
+ // The lower GPIO pins are configured to be output
+ // and accessible to the user project. They show
+ // the project count value, although this test is
+ // designed to read the project count through the
+ // logic analyzer probes.
+ // I/O 6 is configured for the UART Tx line
+ // BitStreamLength 78765
+ uint32_t bitNo = 0x0000;
+ uint32_t testval;
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set UART clock to 64 kbaud (enable before I/O configuration)
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* TEST: Recast channels 37 to 34 to allow input to user project */
+ /* This is done locally only: Do not run reg_mprj_xfer! */
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [63:32] as outputs from the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0x00000000; // [63:32]
+ reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB400000;
+
+ // Set Counter value to zero through LA probes [63:32]
+ reg_la1_data = 0x00000000;
+
+ // Configure LA probes from [63:32] as inputs to disable counter write
+ reg_la1_ena = 0xFFFFFFFF;
+
+ reg_mprj_datal = 0xAB410000;
+ reg_mprj_datah = 0x00000000;
+
+ // Test ability to force data on channel 37
+ // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
+ reg_mprj_datah = 0xffffff28;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0f14;
+ reg_mprj_datah = 0x00000000;
+
+ // Test ability to read back data generated by the user project
+ // on the "monitored" outputs. Read from the lower 16 bits and
+ // copy the value to the upper 16 bits.
+
+ testval = reg_mprj_datal;
+ reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
+
+ // Flag end of the test
+ reg_mprj_datal = 0xAB510000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus_tb.v
new file mode 100644
index 0000000..24ff402
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/mprj_stimulus/mprj_stimulus_tb.v
@@ -0,0 +1,156 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_stimulus_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire [3:0] status;
+
+ // Signals Assignment
+ assign checkbits = mprj_io[31:16];
+ assign status = mprj_io[37:34];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_stimulus.vcd");
+ $dumpvars(0, mprj_stimulus_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(checkbits == 16'hAB40);
+ $display("Monitor: mprj_stimulus test started");
+ wait(status == 4'ha);
+ wait(status == 4'h5);
+ // Value 0009 reflects copying user-controlled outputs to memory and back
+ // to management-controlled outputs.
+ wait(checkbits == 16'h0009);
+ wait(checkbits == 16'hAB51);
+ $display("Monitor: mprj_stimulus test passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_stimulus.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/Makefile
new file mode 100644
index 0000000..2fba759
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pass_thru
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru.c b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru.c
new file mode 100644
index 0000000..33a981d
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru.c
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed. to show that the
+ // processor is halted while the SPI is accessing the
+ // flash SPI in pass-through mode.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test in progress
+ reg_mprj_datal = 0xa5000000;
+
+ // Test message
+ print("Test message\n");
+
+ // End test
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
new file mode 100644
index 0000000..6b5bc38
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -0,0 +1,349 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module pass_thru_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("pass_thru.vcd");
+ $dumpvars(0, pass_thru_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ #2000;
+
+ RSTB <= 1'b1;
+
+ // Wait on start of program execution
+ wait(checkbits == 16'hA000);
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ start_csb();
+ write_byte(8'hc4); // Pass-thru mode
+ write_byte(8'h03); // Command 03 (read values w/3-byte address
+ write_byte(8'h00); // Address is next three bytes (0x000000)
+ write_byte(8'h00);
+ write_byte(8'h00);
+
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ // Wait for processor to restart
+ wait(checkbits == 16'hA000);
+
+ // Read product ID register again
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pass_thru.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/perf/Makefile
new file mode 100644
index 0000000..ed26dce
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/perf/Makefile
@@ -0,0 +1,70 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = perf
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/perf/perf.c b/verilog/dv/caravel/caravel/mgmt_soc/perf/perf.c
new file mode 100644
index 0000000..5a17ba2
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/perf/perf.c
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Performance Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[50];
+unsigned short shorts[50];
+unsigned char bytes[50];
+
+int main()
+{
+ int i;
+ int sum = 0;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0xA0000000;
+
+ for (i=0; i<100; i++)
+ sum += (sum + i);
+
+ reg_mprj_datal = 0xAB000000;
+
+ return sum;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/perf/perf_tb.v
new file mode 100644
index 0000000..08d9401
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/perf/perf_tb.v
@@ -0,0 +1,158 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module perf_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ reg [31:0] kcycles;
+
+ initial begin
+ $dumpfile("perf.vcd");
+ $dumpvars(0, perf_tb);
+
+ kcycles = 0;
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ kcycles <= kcycles + 1;
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Performance (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Performance (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ //#1 $display("GPIO state = %X ", gpio);
+ if(checkbits == 16'hA000) begin
+ kcycles = 0;
+ $display("Performance Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ //$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
+ `ifdef GL
+ $display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+ `else
+ $display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("perf.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/pll/Makefile
new file mode 100644
index 0000000..5946dd5
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pll/Makefile
@@ -0,0 +1,62 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pll
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pll/pll.c b/verilog/dv/caravel/caravel/mgmt_soc/pll/pll.c
new file mode 100644
index 0000000..81a1fc6
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pll/pll.c
@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * PLL Test (self-switching)
+ * - Enables SPI master
+ * - Uses SPI master to internally access the housekeeping SPI
+ * - Switches PLL bypass
+ * - Changes PLL divider
+ *
+ * Tesbench mostly copied from sysctrl
+ */
+void main()
+{
+ int i;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Enable SPI master
+ // SPI master configuration bits:
+ // bits 7-0: Clock prescaler value (default 2)
+ // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
+ // bit 9: CSB sense (0 = inverted, 1 = noninverted)
+ // bit 10: SCK sense (0 = noninverted, 1 = inverted)
+ // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
+ // bit 12: stream (1 = CSB ends transmission)
+ // bit 13: enable (1 = enabled)
+ // bit 14: IRQ enable (1 = enabled)
+ // bit 15: Connect to housekeeping SPI (1 = connected)
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Apply stream read (0x40 + 0x03) and read back one byte
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x08; // Write 0x18 (start address)
+ reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x11; // Write 0x11 (start address)
+ reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x09; // Write 0x09 (start address)
+ reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0410000;
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x12; // Write 0x12 (start address)
+ reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0420000;
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x11; // Write 0x11 (start address)
+ reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0x2102; // Release housekeeping SPI
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/pll/pll_tb.v
new file mode 100644
index 0000000..58b70ea
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/pll/pll_tb.v
@@ -0,0 +1,157 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module pll_tb;
+ reg clock;
+ reg power1;
+ reg power2;
+ reg RSTB;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("pll.vcd");
+ $dumpvars(0, pll_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test PLL (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+
+ $display("Monitor: Test PLL (RTL) Started");
+
+ wait(checkbits == 16'hA041);
+ // $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ // if(spivalue !== 32'h04) begin
+ // $display("Monitor: Test PLL (RTL) Failed");
+ // $finish;
+ // end
+ wait(checkbits == 16'hA042);
+ // $display(" SPI value = 0x%x (should be 0x56)", spivalue);
+ // if(spivalue !== 32'h56) begin
+ // $display("Monitor: Test PLL (RTL) Failed");
+ // $finish;
+ // end
+
+ wait(checkbits == 16'hA090);
+
+ $display("Monitor: Test PLL (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pll.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/storage/Makefile
new file mode 100644
index 0000000..11b0b04
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/storage/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/storage/storage.c b/verilog/dv/caravel/caravel/mgmt_soc/storage/storage.c
new file mode 100644
index 0000000..55fdd98
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/storage/storage.c
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Storage area Test
+ It uses GPIO to flag the success or failure of the test
+*/
+
+void main()
+{
+ int i;
+ volatile uint32_t* ram_addr;
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Management R/W block0
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB400000;
+ }
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Management R/W block1
+ reg_mprj_datal = 0xA0200000;
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block1 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block1 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB200000;
+ }
+
+ reg_mprj_datal = 0xAB210000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/storage/storage_tb.v
new file mode 100644
index 0000000..8a122ff
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/storage/storage_tb.v
@@ -0,0 +1,189 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module storage_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("storage.vcd");
+ $dumpvars(0, storage_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Storage (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Storage (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block0 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block1 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("storage.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/Makefile
new file mode 100644
index 0000000..4816f03
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = sysctrl
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl.c
new file mode 100644
index 0000000..0f5d56d
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl.c
@@ -0,0 +1,165 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * System Control Test
+ * - Enables SPI master
+ * - Uses SPI master to internally access the housekeeping SPI
+ * - Reads default value of SPI-Controlled registers
+ * - Flags failure/success using mprj_io
+ */
+void main()
+{
+ int i;
+ uint32_t value;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Configure next 8 bits for writing the SPI value read on GPIO
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Enable SPI master
+ // SPI master configuration bits:
+ // bits 7-0: Clock prescaler value (default 2)
+ // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
+ // bit 9: CSB sense (0 = inverted, 1 = noninverted)
+ // bit 10: SCK sense (0 = noninverted, 1 = inverted)
+ // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
+ // bit 12: stream (1 = CSB ends transmission)
+ // bit 13: enable (1 = enabled)
+ // bit 14: IRQ enable (1 = enabled)
+ // bit 15: Connect to housekeeping SPI (1 = connected)
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Apply stream read (0x40 + 0x03) and read back one byte
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x01; // Write 0x01 (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0410000 | (value << 8); // Mfgr ID (high)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0420000 | (value << 8); // Mfgr ID (low)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0430000 | (value << 8); // Prod ID
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x08; // Write 0x08 (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0440000 | (value << 8); // PLL enable
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0450000 | (value << 8); // PLL bypass
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x0d; // Write 0x0d (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0460000 | (value << 8); // PLL trim (2 high bits)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0470000 | (value << 8); // PLL trim (2nd byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0480000 | (value << 8); // PLL trim (3rd byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0490000 | (value << 8); // PLL trim (low byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04a0000 | (value << 8); // PLL select (3 lowest bits)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04b0000 | (value << 8); // PLL divider (5 lowest bits)
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x2102; // Release housekeeping SPI
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
new file mode 100644
index 0000000..5be1b5b
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -0,0 +1,219 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module sysctrl_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("sysctrl.vcd");
+ $dumpvars(0, sysctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Started");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Started");
+ `endif
+ wait(checkbits == 16'hA041);
+ $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ if(spivalue !== 32'h04) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA042);
+ $display(" SPI value = 0x%x (should be 0x56)", spivalue);
+ if(spivalue !== 32'h56) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA043);
+ $display(" SPI value = 0x%x (should be 0x10)", spivalue);
+ if(spivalue !== 32'h10) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA044);
+ $display(" SPI value = 0x%x (should be 0x02)", spivalue);
+ if(spivalue !== 32'h02) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA045);
+ $display(" SPI value = 0x%x (should be 0x01)", spivalue);
+ if(spivalue !== 32'h01) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA046);
+ $display(" SPI value = 0x%x (should be 0xff)", spivalue);
+ if(spivalue !== 32'hff) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA047);
+ $display(" SPI value = 0x%x (should be 0xef)", spivalue);
+ if(spivalue !== 32'hef) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA048);
+ $display(" SPI value = 0x%x (should be 0xff)", spivalue);
+ if(spivalue !== 32'hff) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA049);
+ $display(" SPI value = 0x%x (should be 0x03)", spivalue);
+ if(spivalue !== 32'h03) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04a);
+ $display(" SPI value = 0x%x (should be 0x12)", spivalue);
+ if(spivalue !== 32'h12) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04b);
+ $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ if(spivalue !== 32'h04) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA090);
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Passed");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("sysctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/timer/Makefile
new file mode 100644
index 0000000..d7b66b8
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer/timer.c b/verilog/dv/caravel/caravel/mgmt_soc/timer/timer.c
new file mode 100644
index 0000000..e01ed7f
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer/timer.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer Test
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer0_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer0_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer0_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer0_value = 0x00000011;
+ reg_timer0_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000101; // Set value (will be reset)
+ reg_timer0_config = 2; /* Disabled, one-shot, count up */
+ reg_timer0_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x05;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/timer/timer_tb.v
new file mode 100644
index 0000000..9956e19
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer/timer_tb.v
@@ -0,0 +1,200 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer_tb;
+
+ reg RSTB;
+ reg clock;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer.vcd");
+ $dumpvars(0, timer_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (50) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Started");
+ `else
+ $display("Monitor: Test Timer (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Passed");
+ `else
+ $display("Monitor: Test Timer (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/timer2/Makefile
new file mode 100644
index 0000000..0be97ef
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer2/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2.c b/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2.c
new file mode 100644
index 0000000..6d598ac
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer2 Test --- This runs the same testbench as the
+ * other timer, on the 2nd counter/timer module instance.
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer1_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer1_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer1_value = 0x00000011;
+ reg_timer1_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000101; // Set value (will be reset)
+ reg_timer1_config = 2; /* Disabled, one-shot, count up */
+ reg_timer1_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x05; /* Check value in testbench */
+
+ /* Now, set up chained 64 bit timer. Check count-up */
+ /* value and count-down value crossing the 32-bit */
+ /* boundary. */
+
+ /* First disable both counters, and set the "chained" */
+ /* property so that enable/disable will be synchronized */
+
+ reg_timer1_config = 8; /* Disabled, chained */
+ reg_timer0_config = 8; /* Disabled, chained */
+
+ /* Configure timer for a chained single-shot countdown. */
+ /* Count start = 0x0000000100001000, end = 0x0 */
+
+ reg_timer1_value = 0x00000055;
+ reg_timer0_value = 0x00001000;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 11; /* Enabled, one-shot, down count, chained */
+ reg_timer0_config = 11; /* Enabled, one-shot, down count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x06; /* Check value in testbench */
+
+ // Skip to the end. . .
+ reg_timer1_data = 0x00000000;
+ reg_timer0_data = 0x00000200;
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x07; /* Check value in testbench */
+
+ reg_timer1_config = 14; /* Disabled, one-shot, up count, chained */
+ reg_timer0_config = 14; /* Disabled, one-shot, up count, chained */
+
+ reg_timer1_value = 0x00000002;
+ reg_timer0_value = 0x00000000;
+
+ reg_timer1_config = 15; /* Enabled, one-shot, up count, chained */
+ reg_timer0_config = 15; /* Enabled, one-shot, up count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x08; /* Check value in testbench */
+
+ // Skip to the end. . .
+ /* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
+
+ reg_timer1_data = 0x00000001; // Set value (will be reset)
+ reg_timer0_data = 0xffffff00; // Set value (will be reset)
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put timer1 count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x10;
+}
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2_tb.v
new file mode 100644
index 0000000..6fc0501
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -0,0 +1,228 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer2_tb;
+
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer2.vcd");
+ $dumpvars(0, timer2_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (60) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Started");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h06);
+ $display(" countbits = %x (should be 0x005d)", countbits);
+ if(countbits !== 32'h005d) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h07);
+ $display(" countbits = %x (should be 0x0008)", countbits);
+ if(countbits !== 32'h0008) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h08);
+ $display(" countbits = %x (should be 0x0259)", countbits);
+ if(countbits !== 32'h0259) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h10);
+ $display(" countbits = %x (should be 0x000a)", countbits);
+ if(countbits !== 32'h000a) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Passed");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/caravel/mgmt_soc/uart/Makefile
new file mode 100644
index 0000000..e446947
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/uart/Makefile
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/caravel/mgmt_soc/uart/uart.c
new file mode 100644
index 0000000..13cee0f
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/uart/uart.c
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+void main()
+{
+ int j;
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set clock to 64 kbaud and enable the UART. It is important to do this
+ // before applying the configuration, or else the Tx line initializes as
+ // zero, which indicates the start of a byte to the receiver.
+
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Now, apply the configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // This should appear at the output, received by the testbench UART.
+ // (Makes simulation time long.)
+ print("Monitor: Test UART (RTL) passed\n");
+
+ // Allow transmission to complete before signalling that the program
+ // has ended.
+ for (j = 0; j < 20; j++);
+ reg_mprj_datal = 0xab000000;
+}
diff --git a/verilog/dv/caravel/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/caravel/mgmt_soc/uart/uart_tb.v
new file mode 100644
index 0000000..ee5df0b
--- /dev/null
+++ b/verilog/dv/caravel/caravel/mgmt_soc/uart/uart_tb.v
@@ -0,0 +1,149 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module uart_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire uart_tx;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("uart.vcd");
+ $dumpvars(0, uart_tb);
+
+ $display("Wait for UART o/p");
+ repeat (150) begin
+ repeat (10000) @(posedge clock);
+ // Diagnostic. . . interrupts output pattern.
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA000) begin
+ $display("UART Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ `ifdef GL
+ $display("UART Test (GL) passed");
+ `else
+ $display("UART Test (RTL) passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("uart.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/sections.lds b/verilog/dv/caravel/caravel/sections.lds
new file mode 100644
index 0000000..8da9aae
--- /dev/null
+++ b/verilog/dv/caravel/caravel/sections.lds
@@ -0,0 +1,58 @@
+MEMORY {
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 256 words (1 KB) */
+}
+
+SECTIONS {
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.srodata) /* .srodata sections (constants, strings, etc.) */
+ *(.srodata*) /* .srodata*sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } >FLASH
+
+ /* Initialized data section */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(4);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ /* Define the start of the heap */
+ .heap :
+ {
+ . = ALIGN(4);
+ _heap_start = .;
+ } >RAM
+}
diff --git a/verilog/dv/caravel/caravel/spiflash.v b/verilog/dv/caravel/caravel/spiflash.v
new file mode 100644
index 0000000..8bf286c
--- /dev/null
+++ b/verilog/dv/caravel/caravel/spiflash.v
@@ -0,0 +1,417 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+// AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+// Cypress S25FL064L http://www.cypress.com/file/316661/download
+// Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+ parameter FILENAME = "firmware.hex"
+)(
+ input csb,
+ input clk,
+ inout io0, // MOSI
+ inout io1, // MISO
+ inout io2,
+ inout io3
+);
+ localparam verbose = 0;
+ localparam integer latency = 8;
+
+ reg [7:0] buffer;
+ integer bitcount = 0;
+ integer bytecount = 0;
+ integer dummycount = 0;
+
+ reg [7:0] spi_cmd;
+ reg [7:0] xip_cmd = 0;
+ reg [23:0] spi_addr;
+
+ reg [7:0] spi_in;
+ reg [7:0] spi_out;
+ reg spi_io_vld;
+
+ reg powered_up = 0;
+
+ localparam [3:0] mode_spi = 1;
+ localparam [3:0] mode_dspi_rd = 2;
+ localparam [3:0] mode_dspi_wr = 3;
+ localparam [3:0] mode_qspi_rd = 4;
+ localparam [3:0] mode_qspi_wr = 5;
+ localparam [3:0] mode_qspi_ddr_rd = 6;
+ localparam [3:0] mode_qspi_ddr_wr = 7;
+
+ reg [3:0] mode = 0;
+ reg [3:0] next_mode = 0;
+
+ reg io0_oe = 0;
+ reg io1_oe = 0;
+ reg io2_oe = 0;
+ reg io3_oe = 0;
+
+ reg io0_dout = 0;
+ reg io1_dout = 0;
+ reg io2_dout = 0;
+ reg io3_dout = 0;
+
+ assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+ assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+ assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+ assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+ wire io0_delayed;
+ wire io1_delayed;
+ wire io2_delayed;
+ wire io3_delayed;
+
+ assign #1 io0_delayed = io0;
+ assign #1 io1_delayed = io1;
+ assign #1 io2_delayed = io2;
+ assign #1 io3_delayed = io3;
+
+ // 16 MB (128Mb) Flash
+ reg [7:0] memory [0:16*1024*1024-1];
+
+ initial begin
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ $display("Reading %s", FILENAME);
+ $readmemh(FILENAME, memory);
+ $display("%s loaded into memory", FILENAME);
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ end
+
+ task spi_action;
+ begin
+ spi_in = buffer;
+
+ if (bytecount == 1) begin
+ spi_cmd = buffer;
+
+ if (spi_cmd == 8'h ab)
+ powered_up = 1;
+
+ if (spi_cmd == 8'h b9)
+ powered_up = 0;
+
+ if (spi_cmd == 8'h ff)
+ xip_cmd = 0;
+ end
+
+ if (powered_up && spi_cmd == 'h 03) begin
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount >= 4) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h bb) begin
+ if (bytecount == 1)
+ mode = mode_dspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_dspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h eb) begin
+ if (bytecount == 1)
+ mode = mode_qspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h ed) begin
+ if (bytecount == 1)
+ next_mode = mode_qspi_ddr_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_ddr_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ spi_out = buffer;
+ spi_io_vld = 1;
+
+ if (verbose) begin
+ if (bytecount == 1)
+ $write("<SPI-START>");
+ $write("<SPI:%02x:%02x>", spi_in, spi_out);
+ end
+
+ end
+ endtask
+
+ task ddr_rd_edge;
+ begin
+ buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ task ddr_wr_edge;
+ begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+
+ buffer = {buffer, 4'h 0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ always @(csb) begin
+ if (csb) begin
+ if (verbose) begin
+ $display("");
+ $fflush;
+ end
+ buffer = 0;
+ bitcount = 0;
+ bytecount = 0;
+ mode = mode_spi;
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end else
+ if (xip_cmd) begin
+ buffer = xip_cmd;
+ bitcount = 0;
+ bytecount = 1;
+ spi_action;
+ end
+ end
+
+ always @(csb, clk) begin
+ spi_io_vld = 0;
+ if (!csb && !clk) begin
+ if (dummycount > 0) begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end else
+ case (mode)
+ mode_spi: begin
+ io0_oe = 0;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io1_dout = buffer[7];
+ end
+ mode_dspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_dspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io0_dout = buffer[6];
+ io1_dout = buffer[7];
+ end
+ mode_qspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ if (next_mode) begin
+ case (next_mode)
+ mode_qspi_ddr_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_ddr_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ endcase
+ mode = next_mode;
+ next_mode = 0;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!csb) begin
+ if (dummycount > 0) begin
+ dummycount = dummycount - 1;
+ end else
+ case (mode)
+ mode_spi: begin
+ buffer = {buffer, io0};
+ bitcount = bitcount + 1;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_dspi_rd, mode_dspi_wr: begin
+ buffer = {buffer, io1, io0};
+ bitcount = bitcount + 2;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_rd, mode_qspi_wr: begin
+ buffer = {buffer, io3, io2, io1, io0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ end
+ end
+endmodule
diff --git a/verilog/dv/caravel/caravel/start.s b/verilog/dv/caravel/caravel/start.s
new file mode 100644
index 0000000..62a6f42
--- /dev/null
+++ b/verilog/dv/caravel/caravel/start.s
@@ -0,0 +1,159 @@
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li t0, 0x28000000
+
+# Set CS high, IO0 is output
+li t1, 0x120
+sh t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li t5, 32
+# Load t2 from address a0 (4 bytes)
+lw t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+lbu t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw t2, 0(a0)
+addi a0, a0, 4
+lw t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li t1, 0x80
+sb t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+
diff --git a/verilog/dv/caravel/caravel/stub.c b/verilog/dv/caravel/caravel/stub.c
new file mode 100644
index 0000000..575cfc3
--- /dev/null
+++ b/verilog/dv/caravel/caravel/stub.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
\ No newline at end of file
diff --git a/verilog/dv/caravel/caravel/tbuart.v b/verilog/dv/caravel/caravel/tbuart.v
new file mode 100644
index 0000000..bac9480
--- /dev/null
+++ b/verilog/dv/caravel/caravel/tbuart.v
@@ -0,0 +1,93 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud */
+/* and accepting ASCII characters for display. */
+
+/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */
+/* should be possible on a testing system to interface to the UART */
+/* pins on a Raspberry Pi, also running at 3.3V. */
+
+module tbuart (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+ reg [8*50-1:0] recv_buf_data; // 50 characters. Increase as needed for tests.
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ recv_buf_data <= 0;
+ end
+
+ // NOTE: Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+ // bit ~= 64 kbaud. Not tuned to any particular UART. Most run at
+ // 9600 baud default and will bounce up to higher baud rates when
+ // passed specific command words.
+
+ always #1500 clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ // 0x0a = '\n'
+ if (recv_pattern == 8'h0a) begin
+ $display("output: %s", recv_buf_data);
+ end else begin
+ recv_buf_data <= {recv_buf_data, recv_pattern};
+ end
+ recv_state <= 0;
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+
+endmodule
diff --git a/verilog/dv/caravel/caravel/user_proj_example/Makefile b/verilog/dv/caravel/caravel/user_proj_example/Makefile
new file mode 100644
index 0000000..7e37e02
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = io_ports la_test1 la_test2
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/verilog/dv/caravel/caravel/user_proj_example/README.md b/verilog/dv/caravel/caravel/user_proj_example/README.md
new file mode 100644
index 0000000..503b8f4
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/README.md
@@ -0,0 +1,37 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+# Mega-Project Counter Tests
+
+The directory includes three tests for the counter mega-project example:
+
+1) IO Ports Test:
+
+ * Configures the user space lower 8 IO pins as outputs
+ * Observes the counter value through the configured pins in the testbench
+
+ 2) Logic Analyzer Test 1:
+
+ * Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value
+ * Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value
+ * Flags when counter value exceeds 500 through the management SoC gpio
+ * Outputs message to the UART when the test concludes successfuly
+
+ 3) Logic Analyzer Test 2:
+
+ * Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values
+ * Provides counter clock and monitors the counter value after five clock cycles
diff --git a/verilog/dv/caravel/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/caravel/user_proj_example/io_ports/Makefile
new file mode 100644
index 0000000..321de72
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/io_ports/Makefile
@@ -0,0 +1,67 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = io_ports
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports.c
new file mode 100644
index 0000000..f0542f6
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports.c
@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+/*
+ IO Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // Configure lower 8-IOs as user output
+ // Observe counter value in the testbench
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+}
+
diff --git a/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports_tb.v
new file mode 100644
index 0000000..e644347
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module io_ports_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+
+ assign mprj_io_0 = mprj_io[7:0];
+ // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = 1'b1;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("io_ports.vcd");
+ $dumpvars(0, io_ports_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ // Observe Output pins [7:0]
+ wait(mprj_io_0 == 8'h01);
+ wait(mprj_io_0 == 8'h02);
+ wait(mprj_io_0 == 8'h03);
+ wait(mprj_io_0 == 8'h04);
+ wait(mprj_io_0 == 8'h05);
+ wait(mprj_io_0 == 8'h06);
+ wait(mprj_io_0 == 8'h07);
+ wait(mprj_io_0 == 8'h08);
+ wait(mprj_io_0 == 8'h09);
+ wait(mprj_io_0 == 8'h0A);
+ wait(mprj_io_0 == 8'hFF);
+ wait(mprj_io_0 == 8'h00);
+
+ `ifdef GL
+ $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+ `else
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("io_ports.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/caravel/user_proj_example/la_test1/Makefile
new file mode 100644
index 0000000..e9ad798
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test1/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = la_test1
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1.c
new file mode 100644
index 0000000..c5d47bc
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1.c
@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+/*
+ MPRJ Logic Analyzer Test:
+ - Observes counter value through LA probes [31:0]
+ - Sets counter initial value through LA probes [63:32]
+ - Flags when counter value exceeds 500 through the management SoC gpio
+ - Outputs message to the UART when the test concludes successfuly
+*/
+
+void main()
+{
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // The upper GPIO pins are configured to be output
+ // and accessble to the management SoC.
+ // Used to flad the start/end of a test
+ // The lower GPIO pins are configured to be output
+ // and accessible to the user project. They show
+ // the project count value, although this test is
+ // designed to read the project count through the
+ // logic analyzer probes.
+ // I/O 6 is configured for the UART Tx line
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set UART clock to 64 kbaud (enable before I/O configuration)
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [63:32] as outputs from the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0x00000000; // [63:32]
+ reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB400000;
+
+ // Set Counter value to zero through LA probes [63:32]
+ reg_la1_data = 0x00000000;
+
+ // Configure LA probes from [63:32] as inputs to disable counter write
+ reg_la1_ena = 0xFFFFFFFF;
+
+ while (1) {
+ if (reg_la0_data > 0x1F4) {
+ reg_mprj_datal = 0xAB410000;
+ break;
+ }
+ }
+ print("\n");
+ print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long!
+ reg_mprj_datal = 0xAB510000;
+}
+
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1_tb.v
new file mode 100644
index 0000000..125f842
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -0,0 +1,148 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module la_test1_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ initial begin
+ // $dumpfile("la_test1.vcd");
+ // $dumpvars(0, la_test1_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (200) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test LA (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test LA (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(checkbits == 16'hAB40);
+ $display("LA Test 1 started");
+ wait(checkbits == 16'hAB41);
+ wait(checkbits == 16'hAB51);
+ #10000;
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("la_test1.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/caravel/user_proj_example/la_test2/Makefile
new file mode 100644
index 0000000..189dfa4
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test2/Makefile
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = la_test2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2.c b/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2.c
new file mode 100644
index 0000000..ef1b5e9
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+/*
+ MPRJ LA Test:
+ - Sets counter clk through LA[64]
+ - Sets counter rst through LA[65]
+ - Observes count value for five clk cycle through LA[31:0]
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+
+ // All GPIO pins are configured to be output
+ // Used to flad the start/end of a test
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configure All LA probes as inputs to the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0xFFFFFFFF; // [63:32]
+ reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB600000;
+
+ // Configure LA[64] LA[65] as outputs from the cpu
+ reg_la2_ena = 0xFFFFFFFC;
+
+ // Set clk & reset to one
+ reg_la2_data = 0x00000003;
+
+ // Toggle clk & de-assert reset
+ for (i=0; i<11; i=i+1) {
+ clk = !clk;
+ reg_la2_data = 0x00000000 | clk;
+ }
+
+ if (reg_la0_data == 0x05) {
+ reg_mprj_datal = 0xAB610000;
+ }
+
+}
+
diff --git a/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2_tb.v
new file mode 100644
index 0000000..d004269
--- /dev/null
+++ b/verilog/dv/caravel/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -0,0 +1,138 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module la_test2_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+
+ assign checkbits = mprj_io[31:16];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("la_test2.vcd");
+ $dumpvars(0, la_test2_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (30) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(checkbits == 16'h AB60);
+ $display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
+ wait(checkbits == 16'h AB61);
+ $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("la_test2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(),
+ .io3()
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_utests/wb_utests/Makefile b/verilog/dv/wb_utests/wb_utests/Makefile
new file mode 100644
index 0000000..82e5da4
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_wb intercon_wb la_wb mem_wb mprj_ctrl spi_sysctrl_wb spimemio_wb uart_wb storage_wb mgmt_protect
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/gpio_wb/Makefile b/verilog/dv/wb_utests/wb_utests/gpio_wb/Makefile
new file mode 100644
index 0000000..a42f609
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/gpio_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = gpio_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/wb_utests/gpio_wb/gpio_wb_tb.v
new file mode 100644
index 0000000..ea6c772
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -0,0 +1,199 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "gpio_wb.v"
+
+module gpio_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+ reg gpio_in_pad;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ gpio_in_pad = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("gpio_wb_tb.vcd");
+ $dumpvars(0, gpio_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test GPIO Wishbone Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // GPIO Internal Register Addresses
+ wire [31:0] gpio_adr = uut.BASE_ADR | uut.GPIO_DATA;
+ wire [31:0] gpio_oeb_adr = uut.BASE_ADR | uut.GPIO_ENA;
+ wire [31:0] gpio_pu_adr = uut.BASE_ADR | uut.GPIO_PU;
+ wire [31:0] gpio_pd_adr = uut.BASE_ADR | uut.GPIO_PD;
+
+ reg gpio_data;
+ reg gpio_pu;
+ reg gpio_pd;
+ reg gpio_oeb;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to gpio_data reg
+ gpio_in_pad = 1'b1;
+ gpio_data = 1'b1;
+ write(gpio_adr, gpio_data);
+
+ #2;
+ // Read from gpio_data reg
+ read(gpio_adr);
+ if (wb_dat_o !== {30'd0, gpio_data, gpio_in_pad}) begin
+ $display("Monitor: Error reading from gpio reg");
+ $finish;
+ end
+
+ #2;
+ // Write to pull-up reg
+ gpio_pu = 1'b1;
+ write(gpio_pu_adr, gpio_pu);
+
+ #2;
+ // Read from pull-up reg
+ read(gpio_pu_adr);
+ if (wb_dat_o !== {31'd0, gpio_pu}) begin
+ $display("Monitor: Error reading from gpio pull-up reg");
+ $finish;
+ end
+
+ #2;
+ // Write to pull-down reg
+ gpio_pd = 1'b1;
+ write(gpio_pd_adr, gpio_pd);
+
+ #2;
+ // Read from pull-down reg
+ read(gpio_pd_adr);
+ if (wb_dat_o !== {31'd0, gpio_pd}) begin
+ $display("Monitor: Error reading from gpio pull-down reg");
+ $finish;
+ end
+
+ #2;
+ // Write to gpio enable reg
+ gpio_oeb = 1'b1;
+ write(gpio_oeb_adr, gpio_oeb);
+
+ #2;
+ // Read from gpio enable reg
+ read(gpio_oeb_adr);
+ if (wb_dat_o !== {31'd0, gpio_oeb}) begin
+ $display("Monitor: Error reading from gpio output enable reg");
+ $finish;
+ end
+
+ #6;
+ $display("Monitor: GPIO WB Success!");
+ $display("Monitor: GPIO WB Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ gpio_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o),
+ .gpio_in_pad(gpio_in_pad)
+ );
+
+endmodule
diff --git a/verilog/dv/wb_utests/wb_utests/intercon_wb/Makefile b/verilog/dv/wb_utests/wb_utests/intercon_wb/Makefile
new file mode 100644
index 0000000..294cf17
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/intercon_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = intercon_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/wb_utests/intercon_wb/intercon_wb_tb.v
new file mode 100644
index 0000000..4f6fd38
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "wb_intercon.v"
+`include "dummy_slave.v"
+
+`define AW 32
+`define DW 32
+`define NS 6
+
+`define SLAVE_ADR { \
+ {8'h28, {24{1'b0}} }, \
+ {8'h23, {24{1'b0}} }, \
+ {8'h21, {24{1'b0}} }, \
+ {8'h20, {24{1'b0}} }, \
+ {8'h10, {24{1'b0}} }, \
+ {8'h00, {24{1'b0}} } \
+}\
+
+`define ADR_MASK { \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} } \
+}\
+
+module intercon_wb_tb;
+
+ localparam SEL = `DW / 8;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ // Master Interface
+ reg wbm_stb_i;
+ reg wbm_cyc_i;
+ reg wbm_we_i;
+ reg [SEL-1:0] wbm_sel_i;
+ reg [`AW-1:0] wbm_adr_i;
+ reg [`DW-1:0] wbm_dat_i;
+
+ wire [`DW-1:0] wbm_dat_o;
+ wire wbm_ack_o;
+
+ // Wishbone Slave Interface
+ wire [`NS-1:0] wbs_stb_i;
+ wire [`NS-1:0] wbs_ack_o;
+ wire [(`NS*`DW)-1:0] wbs_adr_i;
+ wire [(`NS*`AW)-1:0] wbs_dat_i;
+ wire [(`NS*`DW)-1:0] wbs_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wbm_adr_i = 0;
+ wbm_dat_i = 0;
+ wbm_sel_i = 0;
+ wbm_we_i = 0;
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("intercon_wb_tb.vcd");
+ $dumpvars(0, intercon_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone Interconnect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [`AW*`NS-1: 0] addr = `SLAVE_ADR;
+ reg [`DW:0] slave_data;
+ reg [`AW:0] slave_addr;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // W/R from all slaves
+ for (i=0; i<`NS; i=i+1) begin
+ slave_addr = addr[i*`AW +: `AW];
+ slave_data = $urandom_range(0, 2**32);
+ write(slave_addr, slave_data);
+ #2;
+ read(slave_addr);
+ if (wbm_dat_o !== slave_data) begin
+ $display("%c[1;31m",27);
+ $display ("Monitor: Reading from slave %0d failed", i);
+ $display("Monitor: Test Wishbone Interconnect failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ end
+ $display("Monitor: Test Wishbone Interconnect Success!");
+ $display("Monitor: Test Wishbone Interconnect Passed!");
+ $finish;
+ end
+
+ task write;
+ input [`AW-1:0] addr;
+ input [`AW-1:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wbm_stb_i = 1;
+ wbm_cyc_i = 1;
+ wbm_sel_i = {SEL{1'b1}};
+ wbm_we_i = 1;
+ wbm_adr_i = addr;
+ wbm_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wbm_ack_o == 1);
+ wait(wbm_ack_o == 0);
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [`AW-1:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wbm_stb_i = 1;
+ wbm_cyc_i = 1;
+ wbm_adr_i = addr;
+ wbm_we_i = 0;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wbm_ack_o == 1);
+ wait(wbm_ack_o == 0);
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ $display("Read Cycle Ended.");
+
+ end
+ endtask
+
+ wb_intercon #(
+ .AW(`AW),
+ .DW(`DW),
+ .NS(`NS),
+ .ADR_MASK(`ADR_MASK),
+ .SLAVE_ADR(`SLAVE_ADR)
+ ) uut(
+ // Master Interface
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_ack_o(wbm_ack_o),
+
+ // Slave Interface
+ .wbs_stb_o(wbs_stb_i),
+ .wbs_dat_i(wbs_dat_o),
+ .wbs_ack_i(wbs_ack_o)
+ );
+
+ // Instantiate five dummy slaves for testing
+ dummy_slave dummy_slaves [`NS-1:0](
+ .wb_clk_i({`NS{wb_clk_i}}),
+ .wb_rst_i({`NS{wb_rst_i}}),
+ .wb_stb_i(wbs_stb_i),
+ .wb_cyc_i(wbm_cyc_i),
+ .wb_we_i(wbm_we_i),
+ .wb_sel_i(wbm_sel_i),
+ .wb_adr_i(wbm_adr_i),
+ .wb_dat_i(wbm_dat_i),
+ .wb_dat_o(wbs_dat_o),
+ .wb_ack_o(wbs_ack_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/la_wb/Makefile b/verilog/dv/wb_utests/wb_utests/la_wb/Makefile
new file mode 100644
index 0000000..1b76d6b
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/la_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = la_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/wb_utests/la_wb/la_wb_tb.v
new file mode 100644
index 0000000..6839fdc
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/la_wb/la_wb_tb.v
@@ -0,0 +1,230 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+`include "la_wb.v"
+
+module la_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("la_wb_tb.vcd");
+ $dumpvars(0, la_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone LA Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // LA Wishbone Internal Register Addresses
+ wire [31:0] la_data_adr_0 = uut.BASE_ADR | uut.LA_DATA_0;
+ wire [31:0] la_data_adr_1 = uut.BASE_ADR | uut.LA_DATA_1;
+ wire [31:0] la_data_adr_2 = uut.BASE_ADR | uut.LA_DATA_2;
+ wire [31:0] la_data_adr_3 = uut.BASE_ADR | uut.LA_DATA_3;
+
+ wire [31:0] la_ena_adr_0 = uut.BASE_ADR | uut.LA_ENA_0;
+ wire [31:0] la_ena_adr_1 = uut.BASE_ADR | uut.LA_ENA_1;
+ wire [31:0] la_ena_adr_2 = uut.BASE_ADR | uut.LA_ENA_2;
+ wire [31:0] la_ena_adr_3 = uut.BASE_ADR | uut.LA_ENA_3;
+
+ reg [31:0] la_data_0;
+ reg [31:0] la_data_1;
+ reg [31:0] la_data_2;
+ reg [31:0] la_data_3;
+
+ reg [31:0] la_ena_0;
+ reg [31:0] la_ena_1;
+ reg [31:0] la_ena_2;
+ reg [31:0] la_ena_3;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to la emable registers
+ la_ena_0 = 32'h0000_0000;
+ la_ena_1 = 32'h0000_0000;
+ la_ena_2 = 32'h0000_0000;
+ la_ena_3 = 32'h0000_0000;
+
+ write(la_ena_adr_0, la_ena_0);
+ write(la_ena_adr_1, la_ena_1);
+ write(la_ena_adr_2, la_ena_2);
+ write(la_ena_adr_3, la_ena_3);
+
+ #2;
+ // Read from la data registers
+ read(la_ena_adr_0);
+ if (wb_dat_o !== la_ena_0) begin
+ $display("Monitor: Error reading from la_ena_0 reg");
+ $finish;
+ end
+
+ read(la_ena_adr_1);
+ if (wb_dat_o !== la_ena_1) begin
+ $display("Monitor: Error reading from la_ena_1 reg");
+ $finish;
+ end
+
+ read(la_ena_adr_2);
+ if (wb_dat_o !== la_ena_1) begin
+ $display("Monitor: Error reading from la_ena_2 reg");
+ $finish;
+ end
+
+ read(la_ena_adr_3);
+ if (wb_dat_o !== la_ena_3) begin
+ $display("Monitor: Error reading from la_ena_3 reg");
+ $finish;
+ end
+
+ // Write to la data registers
+ la_data_0 = $urandom_range(0, 2**30);
+ la_data_1 = $urandom_range(0, 2**30);
+ la_data_2 = $urandom_range(0, 2**30);
+ la_data_3 = $urandom_range(0, 2**30);
+
+ write(la_data_adr_0, la_data_0);
+ write(la_data_adr_1, la_data_1);
+ write(la_data_adr_2, la_data_2);
+ write(la_data_adr_3, la_data_3);
+
+ // #2;
+ // Read from la data registers
+ read(la_data_adr_0);
+ $display("%0b", wb_dat_o);
+ $display("%0b", la_data_0);
+
+ if (wb_dat_o !== la_data_0) begin
+ $display("Monitor: Error reading from la data_0 reg");
+ $finish;
+ end
+
+ read(la_data_adr_1);
+ if (wb_dat_o !== la_data_1) begin
+ $display("Monitor: Error reading from la data_1 reg");
+ $finish;
+ end
+
+ read(la_data_adr_2);
+ $display("%0b", wb_dat_o);
+ $display("%0b", la_data_0);
+ if (wb_dat_o !== la_data_2) begin
+ $display("Monitor: Error reading from la data_2 reg");
+ $finish;
+ end
+
+ read(la_data_adr_3);
+ if (wb_dat_o !== la_data_3) begin
+ $display("Monitor: Error reading from la data_3 reg");
+ $finish;
+ end
+ #6;
+ $display("Monitor: Test LA Wishbone Success!");
+ $display("Monitor: Test LA Wishbone Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ la_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/mem_wb/Makefile b/verilog/dv/wb_utests/wb_utests/mem_wb/Makefile
new file mode 100644
index 0000000..b018559
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mem_wb/Makefile
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+.SUFFIXES:
+
+PATTERN = mem_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -s mem_wb_tb -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/wb_utests/mem_wb/mem_wb_tb.v
new file mode 100644
index 0000000..cfc82aa
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mem_wb/mem_wb_tb.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+`include "DFFRAMBB.v"
+`include "DFFRAM.v"
+`include "mem_wb.v"
+
+module mem_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+ reg [3:0] wb_sel_i;
+ reg wb_we_i;
+ reg wb_cyc_i;
+ reg wb_stb_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+ reg power1;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+
+ wb_stb_i = 0; // master select-signal for the slave
+ wb_we_i = 0; // R = 0 , W = 1
+ wb_cyc_i = 0; // master is transferring
+ wb_adr_i = 0; // input addr 32-bits
+ wb_dat_i = 0; // input data 32-bits
+ wb_sel_i = 0; // where data is available on data_i 4-bits
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ #1;
+ power1 <= 1'b1;
+ end
+
+ wire VPWR;
+ wire VGND;
+ assign VGND = 1'b0;
+ assign VPWR = power1;
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("mem_wb_tb.vcd");
+ $dumpvars(0, mem_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone Memory Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] ref_data [255: 0];
+ reg [31: 0] read_data;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Randomly Write to memory array
+ for ( i = 0; i < 1; i = i + 1) begin
+ ref_data[i] = $urandom_range(0, 2**30);
+ write(i, ref_data[i]);
+ #2;
+ end
+
+ #6;
+ for ( i = 0; i < 1; i = i + 1) begin
+ read(i);
+ if (wb_dat_o !== ref_data[i]) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", ref_data[i], wb_dat_o);
+ $display("Monitor: Wishbone Memory Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #2;
+ end
+ #6;
+ $display("Success!");
+ $display ("Monitor: Test Wishbone Memory Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ mem_wb uut(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_stb_i(wb_stb_i),
+
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/mgmt_protect/Makefile b/verilog/dv/wb_utests/wb_utests/mgmt_protect/Makefile
new file mode 100644
index 0000000..31917ec
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mgmt_protect/Makefile
@@ -0,0 +1,44 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=/ef/tech/SW/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = mgmt_protect
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/mgmt_protect/mgmt_protect_tb.v b/verilog/dv/wb_utests/wb_utests/mgmt_protect/mgmt_protect_tb.v
new file mode 100644
index 0000000..bedf7a5
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -0,0 +1,263 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`include "defines.v"
+
+`ifdef GL
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+`else
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+`endif
+
+module mgmt_protect_tb;
+
+ reg caravel_clk;
+ reg caravel_clk2;
+ reg caravel_rstn;
+
+ reg mprj_cyc_o_core;
+ reg mprj_stb_o_core;
+ reg mprj_we_o_core;
+ reg [31:0] mprj_adr_o_core;
+ reg [31:0] mprj_dat_o_core;
+ reg [3:0] mprj_sel_o_core;
+
+ wire [127:0] la_data_in_mprj;
+ reg [127:0] la_data_out_mprj;
+ reg [127:0] la_oen_mprj;
+
+ reg [127:0] la_data_out_core;
+ wire [127:0] la_data_in_core;
+ wire [127:0] la_oen_core;
+
+ wire user_clock;
+ wire user_clock2;
+ wire user_resetn;
+ wire user_reset;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire user1_vcc_powergood;
+ wire user2_vcc_powergood;
+ wire user1_vdd_powergood;
+ wire user2_vdd_powergood;
+
+ always #12.5 caravel_clk <= (caravel_clk === 1'b0);
+ always #12.5 caravel_clk2 <= (caravel_clk2 === 1'b0);
+
+ initial begin
+ caravel_clk = 0;
+ caravel_clk2 = 0;
+ caravel_rstn = 0;
+
+ mprj_cyc_o_core = 0;
+ mprj_stb_o_core = 0;
+ mprj_we_o_core = 0;
+ mprj_adr_o_core = 0;
+ mprj_dat_o_core = 0;
+ mprj_sel_o_core = 0;
+
+ la_data_out_mprj = 0;
+ la_oen_mprj = 0;
+ la_data_out_core = 0;
+ end
+
+ reg USER_VDD3V3;
+ reg USER_VDD1V8;
+ reg VDD3V3;
+ reg VDD1V8;
+
+ wire VCCD; // Management/Common 1.8V power
+ wire VSSD; // Common digital ground
+
+ wire VCCD1; // User area 1 1.8V power
+ wire VSSD1; // User area 1 digital ground
+ wire VCCD2; // User area 2 1.8V power
+ wire VSSD2; // User area 2 digital ground
+
+ wire VDDA1; // User area 1 3.3V power
+ wire VSSA1; // User area 1 analog ground
+ wire VDDA2; // User area 2 3.3V power
+ wire VSSA2; // User area 2 analog ground
+
+ assign VCCD = VDD1V8;
+ assign VSSD = 1'b0;
+
+ assign VCCD1 = USER_VDD1V8;
+ assign VSSD1 = 1'b0;
+
+ assign VCCD2 = USER_VDD1V8;
+ assign VSSD2 = 1'b0;
+
+ assign VDDA1 = USER_VDD3V3;
+ assign VSSA1 = 1'b0;
+
+ assign VDDA2 = USER_VDD3V3;
+ assign VSSA2 = 1'b0;
+
+ initial begin // Power-up sequence
+ VDD1V8 <= 1'b0;
+ USER_VDD3V3 <= 1'b0;
+ USER_VDD1V8 <= 1'b0;
+ #200;
+ VDD1V8 <= 1'b1;
+ #200;
+ USER_VDD3V3 <= 1'b1;
+ #200;
+ USER_VDD1V8 <= 1'b1;
+ end
+
+ initial begin
+ $dumpfile("mgmt_protect.vcd");
+ $dumpvars(0, mgmt_protect_tb);
+ #(`SIM_TIME);
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Management Protect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ caravel_rstn = 1'b1;
+ mprj_cyc_o_core = 1'b1;
+ mprj_stb_o_core = 1'b1;
+ mprj_we_o_core = 1'b1;
+ mprj_sel_o_core = 4'b1010;
+ mprj_adr_o_core = 32'hF0F0;
+ mprj_dat_o_core = 32'h0F0F;
+ la_data_out_mprj = 128'hF0F0_F0F0_F0F0_F0F0;
+ la_oen_mprj = 128'h0F0F_0F0F_0F0F_0F0F;
+ la_data_out_core = 128'h0F0F_FFFF_F0F0_FFFF;
+
+ wait(user1_vdd_powergood === 1'b1);
+ wait(user2_vdd_powergood === 1'b1);
+ wait(user1_vcc_powergood === 1'b1);
+ wait(user2_vcc_powergood === 1'b1);
+ #25;
+
+ if (user_resetn !== caravel_rstn) begin
+ $display("Monitor: Error on user_resetn. "); $finish;
+ end
+ if (user_reset !== ~caravel_rstn) begin
+ $display("Monitor: Error on user_reset. "); $finish;
+ end
+ if (mprj_cyc_o_user !== mprj_cyc_o_core) begin
+ $display("Monitor: Error on mprj_cyc_o_user. "); $finish;
+ end
+ if (mprj_stb_o_user !== mprj_stb_o_core) begin
+ $display("Monitor: Error on mprj_stb_o_user. "); $finish;
+ end
+ if (mprj_we_o_user !== mprj_we_o_core) begin
+ $display("Monitor: Error on mprj_we_o_user. "); $finish;
+ end
+ if (mprj_sel_o_user !== mprj_sel_o_core) begin
+ $display("Monitor: Error on mprj_sel_o_user. "); $finish;
+ end
+ if (mprj_adr_o_user !== mprj_adr_o_core) begin
+ $display("Monitor: Error on mprj_adr_o_user. "); $finish;
+ end
+ if (la_data_in_core !== la_data_out_mprj) begin
+ $display("Monitor: Error on la_data_in_core. "); $finish;
+ end
+ if (la_oen_core !== la_oen_mprj) begin
+ $display("Monitor: Error on la_oen_core. "); $finish;
+ end
+ if (la_data_in_mprj !== la_data_out_core) begin
+ $display("%0h , %0h", la_data_in_mprj, la_data_out_core);
+ $display("Monitor: Error on la_data_in_mprj. "); $finish;
+ end
+ $display ("Success!");
+ $display ("Monitor: Test Management Protect Passed");
+ $finish;
+ end
+
+ mgmt_protect uut (
+ `ifdef USE_POWER_PINS
+ .vccd(VCCD),
+ .vssd(VSSD),
+ .vccd1(VCCD1),
+ .vssd1(VSSD1),
+ .vccd2(VCCD2),
+ .vssd2(VSSD2),
+ .vdda1(VDDA1),
+ .vssa1(VSSA1),
+ .vdda2(VDDA2),
+ .vssa2(VSSA2),
+ `endif
+
+ .caravel_clk (caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core (mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+
+ .la_data_out_core(la_data_out_core),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core (la_data_in_core),
+
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oen_mprj(la_oen_mprj),
+ .la_oen_core(la_oen_core),
+
+ .user_clock (user_clock),
+ .user_clock2(user_clock2),
+ .user_resetn(user_resetn),
+ .user_reset (user_reset),
+
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user (mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+
+ .user1_vcc_powergood(user1_vcc_powergood),
+ .user2_vcc_powergood(user2_vcc_powergood),
+ .user1_vdd_powergood(user1_vdd_powergood),
+ .user2_vdd_powergood(user2_vdd_powergood)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/mprj_ctrl/Makefile b/verilog/dv/wb_utests/wb_utests/mprj_ctrl/Makefile
new file mode 100644
index 0000000..f354018
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mprj_ctrl/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..fd9e5a2
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,159 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+`include "mprj_ctrl.v"
+
+module mprj_ctrl_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // Mega Project Control Registers
+ wire [31:0] mprj_ctrl = uut.BASE_ADR | uut.IOCONFIG;
+ wire [31:0] pwr_ctrl = uut.BASE_ADR | uut.PWRDATA;
+
+ initial begin
+ $dumpfile("mprj_ctrl_tb.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] data;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
+ data = $urandom_range(0, 2**(7));
+ write(mprj_ctrl+i*4, data);
+ #2;
+ read(mprj_ctrl+i*4);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from IO-CTRL Failed.");
+ $finish;
+ end
+ end
+
+ data = $urandom_range(0, 2**(`MPRJ_PWR_PADS-2));
+ write(pwr_ctrl, data);
+ #2;
+ read(pwr_ctrl);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from POWER-CTRL Failed.");
+ $finish;
+ end
+
+
+ $display("Success!");
+ $display ("Monitor: Test Mega-Project Control Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ mprj_ctrl_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/Makefile b/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/Makefile
new file mode 100644
index 0000000..8bf03c7
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spi_sysctrl_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
new file mode 100644
index 0000000..99cb008
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -0,0 +1,157 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simple_spi_master.v"
+
+module spi_sysctrl_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ reg [31:0] spi_cfg_data;
+ reg [31:0] spi_data;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // SPI Control Register Addresses
+ wire [31:0] spi_cfg = uut.BASE_ADR | uut.CONFIG;
+ wire [31:0] spi_data_adr = uut.BASE_ADR | uut.DATA;
+
+ initial begin
+ $dumpfile("spi_sysctrl_wb_tb.vcd");
+ $dumpvars(0, spi_sysctrl_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test SPI System Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #10;
+
+ // Write to SPI_CFG
+ spi_cfg_data = {16'd0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 8'd2};
+ write(spi_cfg, spi_cfg_data);
+
+ #2;
+ // Read from SPI_CFG
+ read(spi_cfg);
+ if (wb_dat_o !== spi_cfg_data) begin
+ $display("Error reading spi_cfg reg");
+ $finish;
+ end
+
+ // Read default value of SPI_DATA
+ spi_data = 32'h00FF;
+ read(spi_data_adr);
+ if (wb_dat_o !== spi_data) begin
+ $display("Error reading data register reg");
+ $finish;
+ end
+ $display("Success!");
+ $display ("Monitor: Test SPI-SYSCTRL WB Passed");
+ $finish;
+ end
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Monitor: Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_adr_i = 0;
+ $display("Monitor: Read Cycle Ended.");
+ end
+ endtask
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_adr_i = 0;
+ wait(wb_ack_o == 0);
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ simple_spi_master_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/spimemio_wb/Makefile b/verilog/dv/wb_utests/wb_utests/spimemio_wb/Makefile
new file mode 100644
index 0000000..d145f04
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/spimemio_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spimemio_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../ -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb_utests/wb_utests/spimemio_wb/flash.hex b/verilog/dv/wb_utests/wb_utests/spimemio_wb/flash.hex
new file mode 100644
index 0000000..23bd76d
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/spimemio_wb/flash.hex
@@ -0,0 +1,6 @@
+@10000000
+a1
+b1
+c1
+d1
+f1
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/wb_utests/spimemio_wb/spimemio_wb_tb.v
new file mode 100644
index 0000000..c474fd0
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -0,0 +1,234 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define FLASH_BASE 32'h 1000_000
+
+`include "spimemio.v"
+// `include "spiflash.v"
+
+module spimemio_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_flash_stb_i;
+ reg wb_cfg_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+
+ wire wb_flash_ack_o;
+ wire wb_cfg_ack_o;
+ wire [31:0] wb_flash_dat_o;
+ wire [31:0] wb_cfg_dat_o;
+
+ wire flash_csb;
+ wire flash_clk;
+
+ wire flash_io0_oeb;
+ wire flash_io1_oeb;
+ wire flash_io2_oeb;
+ wire flash_io3_oeb;
+
+ wire flash_io0_di = 1'b 1;
+ wire flash_io1_di = 1'b 1;
+ wire flash_io2_di = 1'b 1;
+ wire flash_io3_di = 1'b 1;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_flash_stb_i = 0;
+ wb_cfg_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_we_i = 0;
+ wb_sel_i = 0;
+ wb_adr_i = 0;
+ wb_dat_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ spimemio_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_flash_stb_i(wb_flash_stb_i),
+ .wb_cfg_stb_i(wb_cfg_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_we_i(wb_we_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_flash_ack_o(wb_flash_ack_o),
+ .wb_cfg_ack_o(wb_cfg_ack_o),
+ .wb_flash_dat_o(wb_flash_dat_o),
+ .wb_cfg_dat_o(wb_cfg_dat_o),
+
+ .flash_clk(flash_clk),
+ .flash_csb(flash_csb),
+
+ .flash_io0_oeb(flash_io0_oeb),
+ .flash_io1_oeb(flash_io1_oeb),
+ .flash_io2_oeb(flash_io2_oeb),
+ .flash_io3_oeb(flash_io3_oeb),
+
+ .flash_io0_di(flash_io0_di),
+ .flash_io1_di(flash_io1_di),
+ .flash_io2_di(flash_io2_di),
+ .flash_io3_di(flash_io3_di)
+ );
+
+ initial begin
+ $dumpfile("spimemio_wb_tb.vcd");
+ $dumpvars(0, spimemio_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test spimmemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ wire [31:0] cfgreg_data;
+ assign cfgreg_data = {
+ 1'b 1,
+ 8'b 0,
+ 3'b 111,
+ 4'b 1010,
+ 4'b 0, // make sure is it tied to zero in the module itself
+ {~flash_io3_oeb, ~flash_io2_oeb, ~flash_io1_oeb, ~flash_io0_oeb},
+ 2'b 0,
+ flash_csb,
+ flash_clk,
+ {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}
+ };
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Read from flash
+ for (i = `FLASH_BASE; i < `FLASH_BASE + 100 ; i = i + 4) begin
+ read(i, 1, 0);
+ if (wb_flash_dat_o !== 32'hFFFF_FFFF) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", 32'hFFFF_FFFF, wb_flash_dat_o);
+ $display("Monitor: Wishbone spimemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #2;
+ end
+
+ #6;
+ // Write to Configuration register
+ write(cfgreg_data, 0);
+ #2;
+ read(0, 0, 1);
+ if (wb_cfg_dat_o !== cfgreg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", cfgreg_data, wb_cfg_dat_o);
+ $display("Monitor: Wishbone spimemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ $display("Success!");
+ $display("Monitor: Wishbone spimemio Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] data;
+ input [31:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_cfg_stb_i = 1'b 1;
+ wb_flash_stb_i = 1'b 0;
+ wb_cyc_i = 1'b 1;
+ wb_sel_i = 4'b 1111; // complete word
+ wb_we_i = 1'b 1; // write enable
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ end
+
+ wait_ack();
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ input flash_stb;
+ input cfg_stb;
+ begin
+ wb_flash_stb_i = flash_stb;
+ wb_cfg_stb_i = cfg_stb;
+
+ wb_cyc_i = 1'b 1;
+ wb_adr_i = addr;
+ wb_dat_i = 24;
+ wb_sel_i = 4'b 1111; // complete word
+ wb_we_i = 1'b 0; // read
+ $display("Initiated Read transaction...");
+ wait_ack();
+ end
+ endtask
+
+ task wait_ack;
+ // Wait for an ACK
+ if (wb_cfg_stb_i == 1) begin
+ @(posedge wb_cfg_ack_o) begin
+ #2; // To end the transaction on the falling edge of ack
+ wb_cyc_i = 1'b 0;
+ wb_cfg_stb_i = 1'b 0;
+ $display("Monitor: Received an ACK from slave");
+ end
+ end
+ else begin
+ @(posedge wb_flash_ack_o) begin
+ #2; // To end the transaction on the falling edge of ack
+ wb_cyc_i = 1'b 0;
+ wb_flash_stb_i = 1'b 0;
+ $display("Monitor: Received an ACK from slave");
+ end
+ end
+ endtask
+
+ // spiflash #(
+ // .FILENAME("flash.hex")
+ // ) spiflash (
+ // .csb(flash_csb),
+ // .clk(flash_clk),
+ // .io0(flash_io0),
+ // .io1(flash_io1),
+ // .io2(flash_io2),
+ // .io3(flash_io3)
+ // );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/storage_wb/Makefile b/verilog/dv/wb_utests/wb_utests/storage_wb/Makefile
new file mode 100644
index 0000000..d080bcf
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/storage_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = storage_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/wb_utests/storage_wb/storage_wb_tb.v
new file mode 100644
index 0000000..c9aa768
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/storage_wb/storage_wb_tb.v
@@ -0,0 +1,229 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// `define DBG
+
+`define STORAGE_BASE_ADR 32'h0100_0000
+
+`include "defines.v"
+`include "sram_1rw1r_32_256_8_sky130.v"
+`include "storage.v"
+`include "storage_bridge_wb.v"
+
+module storage_tb;
+
+ localparam [(`RAM_BLOCKS*24)-1:0] STORAGE_RW_ADR = {
+ {24'h 10_0000},
+ {24'h 00_0000}
+ };
+
+ localparam [23:0] STORAGE_RO_ADR = {
+ {24'h 20_0000}
+ };
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+ reg [3:0] wb_sel_i;
+ reg wb_we_i;
+ reg wb_cyc_i;
+ reg [1:0] wb_stb_i;
+ wire [1:0] wb_ack_o;
+ wire [31:0] wb_rw_dat_o;
+
+ // MGMT_AREA RO WB Interface
+ wire [31:0] wb_ro_dat_o;
+
+ wire [`RAM_BLOCKS-1:0] mgmt_ena;
+ wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+ wire [`RAM_BLOCKS-1:0] mgmt_wen;
+ wire [31:0] mgmt_wdata;
+ wire [7:0] mgmt_addr;
+ wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+ wire ro_ena;
+ wire [7:0] ro_addr;
+ wire [31:0] ro_rdata;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("storage.vcd");
+ $dumpvars(0, storage_tb);
+ repeat (100) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Storage Area Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ reg [31:0] ref_data [255: 0];
+ reg [(24*`RAM_BLOCKS)-1:0] storage_rw_adr = STORAGE_RW_ADR;
+ reg [23:0] storage_ro_adr = STORAGE_RO_ADR;
+ reg [31:0] block_adr;
+
+ integer i,j;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Test MGMT R/W port and user RO port
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+ for ( j = 0; j < 100; j = j + 1) begin
+ if (i == 0) begin
+ ref_data[j] = $urandom_range(0, 2**30);
+ end
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ write(block_adr, ref_data[j]);
+ #2;
+ end
+ end
+
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+ for ( j = 0; j < 100; j = j + 1) begin
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 0);
+ if (wb_rw_dat_o !== ref_data[j]) begin
+ $display("Got %0h, Expected %0h from addr %0h: ",wb_rw_dat_o,ref_data[j], block_adr);
+ $display("Monitor: MGMT R/W Operation Failed");
+ $finish;
+ end
+
+ if (i == 0) begin
+ block_adr = (storage_ro_adr + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 1);
+ if (wb_ro_dat_o !== ref_data[j]) begin
+ $display("Monitor: MGMT RO Operation Failed");
+ $finish;
+ end
+ end
+ #2;
+ end
+ end
+
+ $display("Success");
+ $display ("Monitor: Test Storage Area Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i[0] = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o[0] == 1);
+ wait(wb_ack_o[0] == 0);
+ wb_cyc_i = 0;
+ wb_stb_i[0] = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ input integer interface;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i[interface] = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o[interface] == 1);
+ wait(wb_ack_o[interface] == 0);
+ wb_cyc_i = 0;
+ wb_stb_i[interface] = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ storage_bridge_wb #(
+ .RW_BLOCKS_ADR(STORAGE_RW_ADR),
+ .RO_BLOCKS_ADR(STORAGE_RO_ADR)
+ ) wb_bridge (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_rw_dat_o(wb_rw_dat_o),
+
+ // MGMT_AREA RO WB Interface
+ .wb_ro_dat_o(wb_ro_dat_o),
+
+ // MGMT Area native memory interface
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // MGMT_AREA RO Interface
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
+ );
+
+ storage uut (
+ // Management R/W WB interface
+ .mgmt_clk(wb_clk_i),
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // Management RO interface
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb_utests/wb_utests/sysctrl_wb/Makefile b/verilog/dv/wb_utests/wb_utests/sysctrl_wb/Makefile
new file mode 100644
index 0000000..89aa77b
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/sysctrl_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = sysctrl_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb_utests/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
new file mode 100644
index 0000000..77140c7
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "sysctrl.v"
+
+module sysctrl_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("sysctrl_wb_tb.vcd");
+ $dumpvars(0, sysctrl_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test System Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // System Control Default Register Addresses
+ wire [31:0] clk_out_adr = uut.BASE_ADR | uut.CLK_OUT;
+ wire [31:0] trap_out_adr = uut.BASE_ADR | uut.TRAP_OUT;
+ wire [31:0] irq_src_adr = uut.BASE_ADR | uut.IRQ_SRC;
+
+ reg clk1_output_dest;
+ reg clk2_output_dest;
+ reg trap_output_dest;
+ reg irq_7_inputsrc;
+ reg irq_8_inputsrc;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ clk1_output_dest = 1'b1;
+ clk2_output_dest = 1'b1;
+ trap_output_dest = 1'b1;
+ irq_7_inputsrc = 1'b1;
+ irq_8_inputsrc = 1'b1;
+
+ // Write to System Control Registers
+ write(clk_out_adr, clk1_output_dest);
+ write(trap_out_adr, trap_output_dest);
+ write(irq_src_adr, irq_7_inputsrc);
+ #2;
+ read(clk_out_adr);
+ if (wb_dat_o !== clk1_output_dest) begin
+ $display("Error reading CLK1 output destination register.");
+ $finish;
+ end
+
+ read(trap_out_adr);
+ if (wb_dat_o !== trap_output_dest) begin
+ $display("Error reading trap output destination register.");
+ $finish;
+ end
+
+ read(irq_src_adr);
+ if (wb_dat_o !== irq_7_inputsrc) begin
+ $display("Error reading IRQ7 input source register.");
+ $finish;
+ end
+
+ $display("Success!");
+ $display ("Monitor: Test System Control Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Monitor: Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Monitor: Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Read Cycle Ended.");
+ end
+ endtask
+
+ sysctrl_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
diff --git a/verilog/dv/wb_utests/wb_utests/uart_wb/Makefile b/verilog/dv/wb_utests/wb_utests/uart_wb/Makefile
new file mode 100644
index 0000000..d1c587f
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/uart_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = uart_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb_utests/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/wb_utests/uart_wb/uart_wb_tb.v
new file mode 100644
index 0000000..da48151
--- /dev/null
+++ b/verilog/dv/wb_utests/wb_utests/uart_wb/uart_wb_tb.v
@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simpleuart.v"
+
+module uart_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ wire tbuart_rx;
+ wire ser_rx;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_we_i = 0;
+ wb_cyc_i = 0;
+ wb_adr_i = 0;
+ wb_dat_i = 0;
+ wb_sel_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("uart_wb_tb.vcd");
+ $dumpvars(0, uart_wb_tb);
+ repeat (500) begin
+ repeat (10000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display("Monitor: Timeout, Test UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ wire [31:0] div_reg_addr = uut.BASE_ADR | uut.CLK_DIV;
+ wire [31:0] div_reg_data = 32'h FFFF_FFFF;
+
+ wire [31:0] dat_reg_addr = uut.BASE_ADR | uut.DATA;
+ wire [31:0] dat_reg_data = 32'h FFFF_FFFF;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to div register
+ write(div_reg_addr, div_reg_data);
+ #2;
+ read(div_reg_addr);
+ if (wb_dat_o !== div_reg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", div_reg_data, wb_dat_o);
+ $display("Monitor: Wishbone UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #6;
+
+ // Write Operation: writes to data register
+ write(dat_reg_addr, dat_reg_data);
+ #2;
+ read(dat_reg_addr);
+ if (wb_dat_o !== dat_reg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", dat_reg_data, wb_dat_o);
+ $display("Monitor: Wishbone UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ $display("Success!");
+ $display("Monitor: Wishbone UART Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ #2;
+ wb_we_i = 0;
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ // wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ simpleuart_wb uut (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o),
+ .ser_tx(tbuart_rx),
+ .ser_rx(ser_rx)
+ );
+
+endmodule
diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v
new file mode 100644
index 0000000..66e6207
--- /dev/null
+++ b/verilog/rtl/caravel_netlists.v
@@ -0,0 +1,88 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+
+`ifdef SIM
+
+`define USE_POWER_PINS
+
+`include "defines.v"
+`include "pads.v"
+
+/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
+
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`ifdef GL
+ `include "gl/mgmt_core.v"
+ `include "gl/digital_pll.v"
+ `include "gl/DFFRAM.v"
+ `include "gl/storage.v"
+ `include "gl/user_id_programming.v"
+ `include "gl/chip_io.v"
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+ `include "gl/gpio_control_block.v"
+ `include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+ `include "gl/user_project_wrapper.v"
+ `include "gl/caravel.v"
+`else
+ `include "mgmt_soc.v"
+ `include "housekeeping_spi.v"
+ `include "caravel_clocking.v"
+ `include "mgmt_core.v"
+ `include "digital_pll.v"
+ `include "DFFRAM.v"
+ `include "DFFRAMBB.v"
+ `include "storage.v"
+ `include "user_id_programming.v"
+ `include "clock_div.v"
+ `include "storage_bridge_wb.v"
+ `include "mprj_io.v"
+ `include "chip_io.v"
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+ `include "gpio_control_block.v"
+ `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+ `include "user_project_wrapper.v"
+ `include "caravel.v"
+`endif
+
+`include "simple_por.v"
+`include "sram_1rw1r_32_256_8_sky130.v"
+
+/*------------------------------*/
+/* Include user project here */
+/*------------------------------*/
+`include "user_proj_example.v"
+
+// `ifdef USE_OPENRAM
+// `include "sram_1rw1r_32_256_8_sky130.v"
+// `endif
+`endif
