| commit | a210b7db1c995e29ffcf3452a1720c2e76e8684b | [log] [tgz] |
|---|---|---|
| author | Manar <manarabdelatty@aucegypt.edu> | Fri Dec 04 01:57:35 2020 +0200 |
| committer | manarabdelaty <manarabdelatty@aucegypt.edu> | Fri Dec 18 13:48:31 2020 +0200 |
| tree | cdb41a2dc2d824dce7530455e18f8d4020bfbd62 | |
| parent | f48448d4736bd6d56fed4dbf7f9cc50552d8745d [diff] |
Update README.md
The repo contains the FPGA layout integration with the Caravel chip. Thee layout is an 8x8 FPGA fabric generated using OpenFPGA and hardened using OpenLANE.
The 8x8 fpga interface to the managent area can be found at fpga_top.v . The fabric is conncted to the managemtent area logic analyzer and wishbone bus.
(WIP)