| commit | 72d191d655c63ed3a705f54f558e8ce0f8425c15 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Thu Jan 28 11:13:05 2021 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Thu Jan 28 11:13:05 2021 -0800 |
| tree | 554657b998456d007f22b39b0df1ff99b3896365 | |
| parent | 08eace786e740ec0a835d8c867fe3321fc80a4ab [diff] |
final gds & drc results
The repo contains the FPGA layout integration with the Caravel chip. Thee layout is an 8x8 FPGA fabric generated using OpenFPGA and hardened using OpenLANE.
The 8x8 fpga interface to the managent area can be found at user_project_wrapper.v . The fabric is conncted to the managemtent area logic analyzer, wishbone bus, and IO-ports.
| Caravel-IO | FPGA | Mode |
|---|---|---|
| io[0] | test_en | Input |
| io[1] | IO_ISOL_N | Input |
| io[7:2] | EMBED-IO[10:15] | Bi-directional |
| io[11] | sc_tail | Output |
| io[12] | ccff_head | Input |
| io[13:14] | EMBED-IO[8:9] | Bi-directional |
| io[17:23] | EMBED-IO[1:8] | Bi-directional |
| io[24] | EMBED-IO[0]* | Bi-directional |
| io[25] | wb_la_switch | Input |
| io[26] | sc_head | Input |
| io[27:34] | EMBED-IO[88-95] | Bi-directional |
| io[35] | ccff_tail | Output |
| io[36] | clk | Input |
| io[37] | prog_clk | Input |