User project wrapper: use user_proj_aes
diff --git a/openlane/user_project_wrapper_empty/config.tcl b/openlane/user_project_wrapper_empty/config.tcl
index faaee02..792b445 100644
--- a/openlane/user_project_wrapper_empty/config.tcl
+++ b/openlane/user_project_wrapper_empty/config.tcl
@@ -23,7 +23,7 @@
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
-set ::unit 2.4
+set ::unit 2
set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
set ::env(FP_IO_VLENGTH) $::unit
@@ -52,10 +52,10 @@
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/user_proj_aes/aes_core.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/user_proj_aes.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/user_proj_aes.gds"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..1dcf92a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -79,7 +79,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
- user_proj_example mprj (
+ user_proj_aes mprj (
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
