Merge branch 'main' of https://github.com/shalan/Caravel_EL2_SoC into main

README.md

diff --git a/README.md b/README.md
index 50a6a67..f98daaa 100644
--- a/README.md
+++ b/README.md
@@ -8,7 +8,7 @@
 
 The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to [user_project_wrapper.v](verilog/rtl/user_project_wrapper.v)
 
-| Caravel-IO    | Chameloen SoC |  Mode
+| Caravel-IO    | EL2 SoC |  Mode
 | ------------- | ------------- | -------------
 |  io[13:0]     | GPIO          | Bi-directional
 |  io[17:14]    | flash         | Bi-directional