Modified the io_ports testbench so that it passes the gate-level simulation.
Also, it exercises the method of using the internal loopback connection between
the SPI master and housekeeping SPI to keep the CSB signal at a known state so
that the GPIO[3] pin can be used as a user project output.
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index a159f0a..f0542f6 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -41,6 +41,16 @@
*/
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
// Configure lower 8-IOs as user output
// Observe counter value in the testbench
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index c680a0b..4e6cd84 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -23,6 +23,7 @@
module io_ports_tb;
reg clock;
reg RSTB;
+ reg CSB;
reg power1, power2;
reg power3, power4;
@@ -31,6 +32,10 @@
wire [7:0] mprj_io_0;
assign mprj_io_0 = mprj_io[7:0];
+ // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -78,8 +83,11 @@
initial begin
RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
#2000;
- RSTB <= 1'b1; // Release reset
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
@@ -87,13 +95,13 @@
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
- #200;
+ #100;
power1 <= 1'b1;
- #200;
+ #100;
power2 <= 1'b1;
- #200;
+ #100;
power3 <= 1'b1;
- #200;
+ #100;
power4 <= 1'b1;
end
