Applied the same io_ports testbench fix to the la_tests
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index d6c2bf6..321de72 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -38,11 +38,11 @@
ifeq ($(SIM),RTL)
iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-else
+ $< -o $@
+else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
endif
%.vcd: %.vvp
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 4e6cd84..3a98f7a 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -22,8 +22,8 @@
module io_ports_tb;
reg clock;
- reg RSTB;
- reg CSB;
+ reg RSTB;
+ reg CSB;
reg power1, power2;
reg power3, power4;
@@ -57,7 +57,11 @@
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -76,8 +80,12 @@
wait(mprj_io_0 == 8'h0A);
wait(mprj_io_0 == 8'hFF);
wait(mprj_io_0 == 8'h00);
-
- $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+
+ `ifdef GL
+ $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+ `else
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ `endif
$finish;
end
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
index 968a74b..e9ad798 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
@@ -14,8 +14,10 @@
#
# SPDX-License-Identifier: Apache-2.0
+
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -37,11 +39,11 @@
ifeq ($(SIM),RTL)
iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-else
+ $< -o $@
+else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
endif
%.vcd: %.vvp
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
index 9759ed7..c5d47bc 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
@@ -30,6 +30,17 @@
void main()
{
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
// The upper GPIO pins are configured to be output
// and accessble to the management SoC.
// Used to flad the start/end of a test
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index 210098f..8f07fe4 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -23,7 +23,9 @@
module la_test1_tb;
reg clock;
- reg RSTB;
+ reg RSTB;
+ reg CSB;
+
reg power1, power2;
wire gpio;
@@ -40,9 +42,11 @@
clock = 0;
end
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
initial begin
- $dumpfile("la_test1.vcd");
- $dumpvars(0, la_test1_tb);
+ // $dumpfile("la_test1.vcd");
+ // $dumpvars(0, la_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (200) begin
@@ -50,7 +54,11 @@
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test LA (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test LA (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -66,9 +74,11 @@
initial begin
RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
+ CSB <= 1'b1; // Force CSB high
#2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
index 4980a08..189dfa4 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
@@ -14,8 +14,10 @@
#
# SPDX-License-Identifier: Apache-2.0
+
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -37,11 +39,11 @@
ifeq ($(SIM),RTL)
iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-else
+ $< -o $@
+else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
endif
%.vcd: %.vvp
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
index 0267d25..ef1b5e9 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
@@ -30,6 +30,17 @@
void main()
{
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+
// All GPIO pins are configured to be output
// Used to flad the start/end of a test
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index b9e5c80..a0e7fcf 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -22,7 +22,9 @@
module la_test2_tb;
reg clock;
- reg RSTB;
+ reg RSTB;
+ reg CSB;
+
reg power1, power2;
wire gpio;
@@ -30,6 +32,7 @@
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
always #12.5 clock <= (clock === 1'b0);
@@ -47,7 +50,11 @@
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -62,9 +69,11 @@
initial begin
RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
+ CSB <= 1'b1; // Force CSB high
#2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
