commit 01e7303068f6c8810c4096e57d1e148bee71a6e9
author Anton Blanchard <anton@linux.ibm.com> Mon Feb 01 22:42:16 2021 +1100
committer Anton Blanchard <anton@ozlabs.org> Mon Feb 01 22:42:16 2021 +1100
tree 542c65665cf5544744d67b25aa4dce5598885f11
parent 195158b0c071df817899f8ea8b24e4ef4c6b0e50

Add fake diode model for gate level simulation

verilog/rtl/caravel_netlists.v

diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v
index 478263b..0bd58df 100644
--- a/verilog/rtl/caravel_netlists.v
+++ b/verilog/rtl/caravel_netlists.v
@@ -50,6 +50,7 @@
 	`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
 
 `default_nettype wire
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
 	`include "gl/icache.v"
 	`include "gl/dcache.v"
 	`include "gl/register_file.v"