[CONFIG] remove the need for an interactive script for user_project_wrapper - Use the default common_pdn.tcl (pdn.tcl no longer needed). - Use the new pdn features. - Use a macro.cfg - Re-order configurations. - Disable unwanted flow stages. - To be followed with a Doc update after further testing. - pin_order.cfg no longer needed.
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl deleted file mode 120000 index d4a8f25..0000000 --- a/openlane/user_project_wrapper/config.tcl +++ /dev/null
@@ -1 +0,0 @@ -../user_project_wrapper_empty/config.tcl \ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl new file mode 100644 index 0000000..522ca78 --- /dev/null +++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,83 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Base Configurations. Don't Touch +# section begin +set script_dir [file dirname [file normalize [info script]]] +set ::env(DESIGN_NAME) user_project_wrapper +#section end + + +# User Configurations +set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg + +set ::env(CLOCK_PORT) "user_clock2" +set ::env(CLOCK_NET) "mprj.clk" + +set ::env(CLOCK_PERIOD) "10" + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_project_wrapper.v" + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_proj_example.v" + +set ::env(EXTRA_LEFS) "\ + $script_dir/../../lef/user_proj_example.lef" + +set ::env(EXTRA_GDS_FILES) "\ + $script_dir/../../gds/user_proj_example.gds" + + +# The following is because there are no std cells in the example wrapper project. +set ::env(SYNTH_TOP_LEVEL) 1 +set ::env(PL_RANDOM_GLB_PLACEMENT) 1 +set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 +set ::env(DIODE_INSERTION_STRATEGY) 0 +set ::env(FILL_INSERTION) 0 +set ::env(TAP_DECAP_INSERTION) 0 +set ::env(CLOCK_TREE_SYNTH) 0 + +# Area Configurations. DON'T TOUCH. +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 2920 3520" + +# Power & Pin Configurations. DON'T TOUCH. +set ::env(FP_PDN_CORE_RING) 1 + +set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] +set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] +#set ::env(PDN_CFG) $script_dir/pdn.tcl + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def +set ::unit 2.4 +set ::env(FP_IO_VEXTEND) [expr 2*$::unit] +set ::env(FP_IO_HEXTEND) [expr 2*$::unit] +set ::env(FP_IO_VLENGTH) $::unit +set ::env(FP_IO_HLENGTH) $::unit + +set ::env(FP_IO_VTHICKNESS_MULT) 4 +set ::env(FP_IO_HTHICKNESS_MULT) 4 + + + +# Need to fix a FastRoute bug for this to work, but it's good +# for a sense of "isolation" +set ::env(MAGIC_ZEROIZE_ORIGIN) 0 +set ::env(MAGIC_WRITE_FULL_LEF) 1 +
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg new file mode 100644 index 0000000..bae1d2d --- /dev/null +++ b/openlane/user_project_wrapper/macro.cfg
@@ -0,0 +1 @@ +mprj 1150 1700 N \ No newline at end of file
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl index a3c8e6a..c1ab326 100644 --- a/openlane/user_project_wrapper/pdn.tcl +++ b/openlane/user_project_wrapper/pdn.tcl
@@ -37,8 +37,8 @@ power_pins $::env(_VDD_NET_NAME) ground_pins $::env(_GND_NET_NAME) blockages "li1 met1 met2 met3 met4 met5" - straps { - } + straps { + } connect {} } @@ -47,8 +47,8 @@ power_pins $::env(_VDD_NET_NAME) ground_pins $::env(_GND_NET_NAME) blockages "" - straps { - } + straps { + } connect {} }
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/x_interactive.tcl similarity index 97% rename from openlane/user_project_wrapper/interactive.tcl rename to openlane/user_project_wrapper/x_interactive.tcl index 078bf98..e074109 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/x_interactive.tcl
@@ -13,6 +13,8 @@ # limitations under the License. # SPDX-License-Identifier: Apache-2.0 +# This file is no longer used. But it's kept here for reference. + package require openlane set script_dir [file dirname [file normalize [info script]]]