Added two testbenches for the user_project , WIP
diff --git a/verilog/dv/caravel/user_proj_example/Makefile b/verilog/dv/caravel/user_proj_example/Makefile
index dd0b951..e36f577 100644
--- a/verilog/dv/caravel/user_proj_example/Makefile
+++ b/verilog/dv/caravel/user_proj_example/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = spm
+PATTERNS = spm chain
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/caravel/user_proj_example/chain/Makefile b/verilog/dv/caravel/user_proj_example/chain/Makefile
new file mode 100644
index 0000000..ca171c2
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/chain/Makefile
@@ -0,0 +1,67 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = chain
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/chain/chain.c b/verilog/dv/caravel/user_proj_example/chain/chain.c
new file mode 100644
index 0000000..dcabc98
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/chain/chain.c
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+/*
+ SPM Scan-Chain test Test:
+*/
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ */
+
+ // Configure JTAG ports
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; // tck
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; // tms
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL; // tdi
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL; // trst
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL; // tdo
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+}
+
diff --git a/verilog/dv/caravel/user_proj_example/chain/chain_tb.v b/verilog/dv/caravel/user_proj_example/chain/chain_tb.v
new file mode 100644
index 0000000..1b3bb7e
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/chain/chain_tb.v
@@ -0,0 +1,227 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "gl/user_project/gl/user_proj_top.v"
+`include "caravel.v"
+`include "spiflash.v"
+
+`define SOC_SETUP_TIM 170_000
+
+module chain_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ // JTAG Ports
+ reg tms;
+ reg tck;
+ reg tdi;
+ reg trst;
+
+ wire tdo;
+
+ assign mprj_io[0] = tck;
+ assign mprj_io[1] = tms;
+ assign mprj_io[2] = tdi;
+ assign mprj_io[3] = trst;
+ assign tdo = mprj_io[4];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ wire[501:0] serializable =
+ 502'b1010110101101111001111101100111011011111011100101101011100110101011001001100110001000000000100001010010001001011001011101111110001101111111001101011111000101001111011001001110001100011001011101010010100100010110111101101011001111100010000110110101110100010110110101010011110110011100100011111001110111101110101111010110000010001000111010010001111111000110101011101110000011000001110010111101110000111111010010111001010011110100010011011001100100101100000011011001000110011010110111111100101011101101100;
+ reg[501:0] serial;
+
+ wire[7:0] tmsPattern = 8'b 01100110;
+ wire[3:0] preload_chain = 4'b0011;
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("chain.vcd");
+ $dumpvars(0, chain_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (40) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Chain (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ tms = 0 ;
+ tck = 0 ;
+ tdi = 0 ;
+ trst = 0 ;
+ RSTB <= 1'b0;
+ tms = 1;
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #(`SOC_SETUP_TIM);
+ trst = 1;
+ #20;
+
+ /*
+ Test PreloadChain Instruction
+ */
+ shiftIR(preload_chain);
+ enterShiftDR();
+
+ for (i = 0; i < 502; i = i + 1) begin
+ tdi = serializable[i];
+ #20;
+ end
+ for(i = 0; i< 502; i = i + 1) begin
+ serial[i] = tdo;
+ #20;
+ end
+
+ if(serial !== serializable) begin
+ $error("EXECUTING_PRELOAD_CHAIN_INST_FAILED");
+ $finish;
+ end
+ exitDR();
+
+ $display("SUCCESS_STRING");
+ $finish;
+ end
+
+ task shiftIR;
+ input[3:0] instruction;
+ integer i;
+ begin
+ for (i = 0; i< 5; i = i + 1) begin
+ tms = tmsPattern[i];
+ #20;
+ end
+
+ // At shift-IR: shift new instruction on tdi line
+ for (i = 0; i < 4; i = i + 1) begin
+ tdi = instruction[i];
+ if(i == 3) begin
+ tms = tmsPattern[5]; // exit-ir
+ end
+ #20;
+ end
+
+ tms = tmsPattern[6]; // update-ir
+ #20;
+ tms = tmsPattern[7]; // run test-idle
+ #60;
+ end
+ endtask
+
+ task enterShiftDR;
+ begin
+ tms = 1; // select DR
+ #20;
+ tms = 0; // capture DR -- shift DR
+ #40;
+ end
+ endtask
+
+ task exitDR;
+ begin
+ tms = 1; // Exit DR -- update DR
+ #40;
+ tms = 0; // Run test-idle
+ #20;
+ end
+ endtask
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #200;
+ power3 <= 1'b1;
+ #200;
+ power4 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("chain.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/user_proj_example/spm/spm.c b/verilog/dv/caravel/user_proj_example/spm/spm.c
index dc91b71..d901e6b 100644
--- a/verilog/dv/caravel/user_proj_example/spm/spm.c
+++ b/verilog/dv/caravel/user_proj_example/spm/spm.c
@@ -69,12 +69,12 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- // Configure LA probes [31:0], [63:32],[64] as inputs to the cpu
- // Configure LA probe [65], [127:96] as output from the cpu
+ // Configure LA probes [31:0], [63:32],[64], [65] as inputs to the cpu
+ // Configure LA probe [127:96] as output from the cpu
reg_la0_ena = 0xFFFFFFFF; // [31:0]
reg_la1_ena = 0xFFFFFFFF; // [63:32]
- reg_la2_ena = 0x00000001; // [95:64]
- reg_la3_ena = 0x00000000; // [127:96]
+ reg_la2_ena = 0x00000007; // [95:64]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
// Write mc & mp
reg_la0_data = 4; // mc
@@ -83,22 +83,59 @@
// Start Multiplication
reg_la2_data = 1;
- // Configure LA[0] as output
- reg_la0_ena = 0x00000000;
-
// Wait on done signal
- while((reg_la0_data & 0x00000001) != 1);
-
- // Configure [64] as output
- reg_la2_ena = 0x00000001;
-
- // read multiplication value
- int long prod = ((reg_la3_data << 32) | reg_la2_data);
+ while(((reg_la2_data >> 2) & 0x00000001) != 1);
- if (prod != 25) {
+ reg_mprj_datal = 0xAB300000; // flag multiplication done
+
+ if (reg_la3_data != 24) {
reg_mprj_datal = 0xAB410000;
} else {
reg_mprj_datal = 0xAB400000;
}
+
+ reg_la2_data = 0;
+
+ // Write mc & mp
+ reg_la0_data = 153; // mc
+ reg_la1_data = 99; // mp
+
+ // Start Multiplication
+ reg_la2_data = 1;
+
+ // Wait on done signal
+ while(((reg_la2_data >> 2) & 0x00000001) != 1);
+
+ reg_mprj_datal = 0xAB300000; // flag multiplication done
+
+ if (reg_la3_data != 15147) {
+ reg_mprj_datal = 0xAB510000;
+ } else {
+ reg_mprj_datal = 0xAB500000;
+ }
+
+ reg_la2_data = 0;
+
+
+ // Write mc & mp
+ reg_la0_data = -183; // mc
+ reg_la1_data = -83; // mp
+
+ // Start Multiplication
+ reg_la2_data = 1;
+
+ // Wait on done signal
+ while(((reg_la2_data >> 2) & 0x00000001) != 1);
+
+ reg_mprj_datal = 0xAB300000; // flag multiplication done
+
+ if (reg_la3_data != 15189) {
+ reg_mprj_datal = 0xAB610000;
+ } else {
+ reg_mprj_datal = 0xAB600000;
+ }
+
+ reg_la2_data = 0;
+
}
diff --git a/verilog/dv/caravel/user_proj_example/spm/spm_tb.v b/verilog/dv/caravel/user_proj_example/spm/spm_tb.v
index 05593fd..a4850c9 100644
--- a/verilog/dv/caravel/user_proj_example/spm/spm_tb.v
+++ b/verilog/dv/caravel/user_proj_example/spm/spm_tb.v
@@ -17,7 +17,7 @@
`timescale 1 ns / 1 ps
-`include "gl/user_project/gl/spm_top.v"
+`include "gl/user_project/gl/user_proj_top.v"
`include "caravel.v"
`include "spiflash.v"
@@ -53,7 +53,7 @@
$dumpvars(0, spm_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
+ repeat (40) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -64,9 +64,16 @@
end
initial begin
- // Observe Output pins [7:0]
+ wait(mprj_io_h == 16'hAB30);
+ $display("Multiplication is done !");
wait(mprj_io_h == 16'hAB40);
- $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ wait(mprj_io_h == 16'hAB30);
+ $display("Multiplication is done !");
+ wait(mprj_io_h == 16'hAB50);
+ wait(mprj_io_h == 16'hAB30);
+ $display("Multiplication is done !");
+ wait(mprj_io_h == 16'hAB60);
+ $display("Monitor: Test 1 SPM Functional Test (RTL) Passed");
$finish;
end
