Added SPM RTL
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..0fb61a0 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -29,9 +29,9 @@
*-------------------------------------------------------------
*/
-module user_project_wrapper #(
- parameter BITS = 32
-)(
+`define MPRJ_IO_PADS 38
+
+module user_project_wrapper (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
@@ -52,7 +52,7 @@
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
- output wbs_ack_o,
+ output reg wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
@@ -79,7 +79,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
- user_proj_example mprj (
+ user_proj_top user_proj_top (
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
@@ -93,32 +93,26 @@
// MGMT core clock and reset
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+ .clk(wb_clk_i),
+ .rst(wb_rst_i),
// Logic Analyzer
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oen (la_oen),
+ .mc (la_data_in[31:0]),
+ .mp (la_data_in[63:32]),
+ .start (la_data_in[64]),
+ .done (la_data_out[0]),
+ .prod (la_data_out[127:64]),
+ .tie ({io_oeb[`MPRJ_IO_PADS-1:5], io_oeb[3:0], io_out[`MPRJ_IO_PADS-1:5], io_out[3:0], la_data_out[63:1], wbs_ack_o, wbs_dat_o[31:0]}),
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb)
+ // IO Pads
+ .tck(io_in[0]), // test clock on one of the IOs ?
+ .tms(io_in[1]),
+ .tdi(io_in[2]),
+ .trst(io_in[3]),
+ .tdo(io_out[4]),
+ .tdo_paden_o(io_oeb[4])
);
endmodule // user_project_wrapper
-`default_nettype wire
+`default_nettype wire
\ No newline at end of file
