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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-023 / 398513982eb94daec68efed90746e62a6e7c5092
commit398513982eb94daec68efed90746e62a6e7c5092[log] [tgz]
authormina_maksimous <mina_maksimous@mabrains.com>Tue Feb 02 13:54:39 2021 +0200
committermina_maksimous <mina_maksimous@mabrains.com>Tue Feb 02 13:54:39 2021 +0200
tree7d70c10b65c9287ec7de92d8322c12299c0b3a00
parenta83d4e4213fc39e16b3b2990e9311a69e9914a11 [diff]
modificationsof the ldo netlist
1 file changed
tree: 7d70c10b65c9287ec7de92d8322c12299c0b3a00
  1. .travisCI/
  2. def/
  3. doc/
  4. documents/
  5. gds/
  6. lef/
  7. macros/
  8. mag/
  9. maglef/
  10. netlists/
  11. ngspice/
  12. openlane/
  13. qflow/
  14. scripts/
  15. spi/
  16. test_integrate/
  17. utils/
  18. verilog/
  19. .travis.yml
  20. info.yaml
  21. LICENSE
  22. Makefile
  23. mpw-one-a.md
  24. README.md
README.md

Analog and RF Testchip on Skywaters 130nm Technology.

In this tapeout, we are planning to achieve the following:

  • 5 Transistor OTA with trimming resistors to adjust bias. [Completed with Layout, without the trimming resistor]
  • LDO [Schematic is complete, no layout currently]
  • VCO at 2.45GHz for BT, Wifi applications [Tentative plan and in progress]

OTA Design

  • Simulated specs
spec/cornerttfssfssff
Gain36db36db36.1db36.2db35.8db
BW10Mega Hz12.6Mgea Hz10Mega Hz10Mega Hz10 Mega Hz
GBW64Mega80 Mega64 Mega65 Mega62Mega
power82.5 uw98.6 uw67 uw96 uw70 uw
phase margin92 degre94 degree93degree93 degree94 degree
cmrr59.2db55.8db61.7db56.2db61.5

LDO Design

  • Input voltage is 1.8V
  • Will add the specs later.

Schedule and timeline:

Monday December 7th, 2020

  • Complete the layout of trimming resistor for biasing of the 5 Transistor OTA

Thursday December 10th, 2020

  • Complete the LDO layout.

Thursday December 17th, 2020

  • Add a second stage for the OTA and have double stage OTA to achieve higher gain.

Contributers