Finalized the voltage clamp arrangement and the total number of pads.
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index ebe0234..5238bef 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -73,97 +73,62 @@
// 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
// One each HV and LV clamp.
- s8iom0_vddio_hvc_pad mgmt_vddio_hvclamp_pad (
+ // HV clamps connect between one HV power rail and one ground
+ // LV clamps have two clamps connecting between any two LV power
+ // rails and grounds, and one back-to-back diode which connects
+ // between the first LV clamp ground and any other ground.
+
+ s8iom0_vddio_hvc_pad mgmt_vddio_hvclamp_pad [1:0] (
`MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vddio_lvc_pad mgmt_vddio_lvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vddio, vssio)
);
s8iom0_vdda_hvc_pad mgmt_vdda_hvclamp_pad (
`MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vdda_lvc_pad mgmt_vdda_lvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda, vssa)
);
- s8iom0_vccd_hvc_pad mgmt_vccd_hvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vccd_lvc_pad mgmt_vccd_lvclamp_pad (
`MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd, vssio, vccd, vssd, vssa)
);
- s8iom0_vssio_hvc_pad mgmt_vssio_hvclamp_pad (
+ s8iom0_vssio_hvc_pad mgmt_vssio_hvclamp_pad [1:0] (
`MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vssio_lvc_pad mgmt_vssio_lvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vddio, vssio)
);
s8iom0_vssa_hvc_pad mgmt_vssa_hvclamp_pad (
`MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vssa_lvc_pad mgmt_vssa_lvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda, vssa)
);
- s8iom0_vssd_hvc_pad mgmt_vssd_hvclamp_pad (
- `MGMT_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vssd_lvc_pad mgmt_vssd_lvclmap_pad (
`MGMT_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd, vssio, vccd, vssd, vssa)
);
// Instantiate power and ground pads for user 1 domain
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
- s8iom0_vdda_hvc_pad user1_vdda_hvclamp_pad (
+ s8iom0_vdda_hvc_pad user1_vdda_hvclamp_pad [1:0] (
`USER1_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vdda_lvc_pad user1_vdda_lvclamp_pad (
- `USER1_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda1, vssa1)
);
- s8iom0_vccd_hvc_pad user1_vccd_hvclamp_pad (
- `USER1_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vccd_lvc_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd1, vssd1, vccd1, vssd, vssio)
);
- s8iom0_vssa_hvc_pad user1_vssa_hvclamp_pad (
+ s8iom0_vssa_hvc_pad user1_vssa_hvclamp_pad [1:0] (
`USER1_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vssa_lvc_pad user1_vssa_lvclamp_pad (
- `USER1_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda1, vssa1)
);
- s8iom0_vssd_hvc_pad user1_vssd_hvclamp_pad (
- `USER1_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vssd_lvc_pad user1_vssd_lvclmap_pad (
`USER1_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd1, vssd1, vccd1, vssd, vssio)
);
// Instantiate power and ground pads for user 2 domain
@@ -171,38 +136,22 @@
s8iom0_vdda_hvc_pad user2_vdda_hvclamp_pad (
`USER2_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vdda_lvc_pad user2_vdda_lvclamp_pad (
- `USER2_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda2, vssa2)
);
- s8iom0_vccd_hvc_pad user2_vccd_hvclamp_pad (
- `USER2_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vccd_lvc_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd2, vssd2, vccd2, vssd, vssio)
);
s8iom0_vssa_hvc_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
- s8iom0_vssa_lvc_pad user2_vssa_lvclamp_pad (
- `USER2_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `HVCLAMP_PINS(vdda2, vssa2)
);
- s8iom0_vssd_hvc_pad user2_vssd_hvclamp_pad (
- `USER2_ABUTMENT_PINS
- `HVCLAMP_PINS
- );
s8iom0_vssd_lvc_pad user2_vssd_lvclmap_pad (
`USER2_ABUTMENT_PINS
- `LVCLAMP_PINS
+ `LVCLAMP_PINS(vccd2, vssd2, vccd2, vssd, vssio)
);
wire [2:0] dm_all =
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index b17bf1d..1c3a4bf 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -46,16 +46,16 @@
`define MGMT_ABUTMENT_PINS
`endif
-`define HVCLAMP_PINS \
- .drn_hvc(), \
- .src_bdy_hvc()
+`define HVCLAMP_PINS(H,L) \
+ .drn_hvc(H), \
+ .src_bdy_hvc(L)
-`define LVCLAMP_PINS \
- .bdy2_b2b(), \
- .drn_lvc1(), \
- .drn_lvc2(), \
- .src_bdy_lvc1(), \
- .src_bdy_lvc2()
+`define LVCLAMP_PINS(H1,L1,H2,L2,L3) \
+ .bdy2_b2b(L3), \
+ .drn_lvc1(H1), \
+ .drn_lvc2(H2), \
+ .src_bdy_lvc1(L1), \
+ .src_bdy_lvc2(L2)
`define INPUT_PAD(X,Y) \
wire loop_``X; \
