commit 907394669505129b4a7baf4fb8236313fc552af3
author Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 22:15:28 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 22:15:28 2020 -0400
tree 9ee29cf037b49ccffa25ed26cf9b7156e5ec4707
parent bb3cd69b4ddc706fd7c4f828fb85044152a6bbc5

Removed a small error in the PLL testbench C code.  However, the
PLL testbench drives the CPU into the trap state, and it is not
obvious why.

verilog/dv/caravel/mgmt_soc/pll/pll.c

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll.c b/verilog/dv/caravel/mgmt_soc/pll/pll.c
index 042e41d..ac0c375 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll.c
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll.c
@@ -14,7 +14,6 @@
 void main()
 {
     int i;
-    uint32_t value;
 
     reg_mprj_datal = 0;
 
@@ -38,16 +37,6 @@
     reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
-    // Configure next 8 bits for writing the SPI value read on GPIO
-    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
-
     /* Apply configuration */
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
@@ -81,7 +70,7 @@
     reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
 
     // Write checkpoint
-    reg_mprj_datal = 0xA0410000 | (value << 8);	// Mfgr ID (high)
+    reg_mprj_datal = 0xA0410000;
 
     reg_spimaster_config = 0xb002;	// Apply stream mode
     reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
@@ -91,7 +80,7 @@
     reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
 
     // Write checkpoint
-    reg_mprj_datal = 0xA0420000 | (value << 8);	// PLL enable
+    reg_mprj_datal = 0xA0420000;
 
     reg_spimaster_config = 0xb002;	// Apply stream mode
     reg_spimaster_data = 0x80;		// Write 0x80 (write mode)