commit 61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55
author Tim Edwards <tim@opencircuitdesign.com> Sat Oct 03 11:51:17 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Sat Oct 03 11:51:17 2020 -0400
tree b7d5960f853d8a0f8363dbd9b05446e9c1467794
parent c18c474118be6020a759267525f5df7c62ce7ee4

Corrected the primary issue with simulation, which was the failure
to change the "vdd" connection of vddio to "vdd3v3", leaving it as
an isolated net.

verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd b/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd
deleted file mode 100644
index 06fe61e..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd
+++ /dev/null
@@ -1,124217 +0,0 @@
-$date
-	Sat Oct  3 11:19:20 2020
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1ps
-$end
-$scope module gpio_tb $end
-$var wire 1 ! CSB $end
-$var wire 1 " SCK $end
-$var wire 1 # SDI $end
-$var wire 1 $ SDO $end
-$var wire 1 % VDD1V8 $end
-$var wire 1 & VDD3V3 $end
-$var wire 1 ' VSS $end
-$var wire 16 ( checkbits [15:0] $end
-$var wire 1 ) flash_clk $end
-$var wire 1 * flash_csb $end
-$var wire 1 + flash_io0 $end
-$var wire 1 , flash_io1 $end
-$var wire 1 - gpio $end
-$var wire 12 . noconnect [11:0] $end
-$var wire 8 / checkbits_hi [7:0] $end
-$var reg 1 0 RSTB $end
-$var reg 8 1 checkbits_lo [7:0] $end
-$var reg 1 2 clock $end
-$scope module spiflash $end
-$var wire 1 ) clk $end
-$var wire 1 * csb $end
-$var wire 1 + io0 $end
-$var wire 1 3 io0_delayed $end
-$var wire 1 , io1 $end
-$var wire 1 4 io1_delayed $end
-$var wire 1 5 io2_delayed $end
-$var wire 1 6 io3_delayed $end
-$var wire 1 7 io3 $end
-$var wire 1 8 io2 $end
-$var reg 8 9 buffer [7:0] $end
-$var reg 1 : io0_dout $end
-$var reg 1 ; io0_oe $end
-$var reg 1 < io1_dout $end
-$var reg 1 = io1_oe $end
-$var reg 1 > io2_dout $end
-$var reg 1 ? io2_oe $end
-$var reg 1 @ io3_dout $end
-$var reg 1 A io3_oe $end
-$var reg 4 B mode [3:0] $end
-$var reg 4 C next_mode [3:0] $end
-$var reg 1 D powered_up $end
-$var reg 24 E spi_addr [23:0] $end
-$var reg 8 F spi_cmd [7:0] $end
-$var reg 8 G spi_in [7:0] $end
-$var reg 1 H spi_io_vld $end
-$var reg 8 I spi_out [7:0] $end
-$var reg 8 J xip_cmd [7:0] $end
-$var integer 32 K bitcount [31:0] $end
-$var integer 32 L bytecount [31:0] $end
-$var integer 32 M dummycount [31:0] $end
-$scope task ddr_rd_edge $end
-$upscope $end
-$scope task ddr_wr_edge $end
-$upscope $end
-$scope task spi_action $end
-$upscope $end
-$upscope $end
-$scope module uut $end
-$var wire 1 N clock $end
-$var wire 1 ) flash_clk $end
-$var wire 1 O flash_clk_ieb_core $end
-$var wire 1 * flash_csb $end
-$var wire 1 P flash_csb_ieb_core $end
-$var wire 1 + flash_io0 $end
-$var wire 1 , flash_io1 $end
-$var wire 1 - gpio $end
-$var wire 32 Q mgmt_io_data [31:0] $end
-$var wire 1 R mprj_ack_i_core $end
-$var wire 32 S mprj_adr_o_core [31:0] $end
-$var wire 1 T mprj_cyc_o_core $end
-$var wire 32 U mprj_dat_o_core [31:0] $end
-$var wire 32 V mprj_io [31:0] $end
-$var wire 32 W mprj_io_enh [31:0] $end
-$var wire 32 X mprj_io_hldh_n [31:0] $end
-$var wire 32 Y mprj_io_oeb_n [31:0] $end
-$var wire 1 Z mprj_io_oen_n $end
-$var wire 4 [ mprj_sel_o_core [3:0] $end
-$var wire 1 \ mprj_we_o_core $end
-$var wire 1 ] resetb $end
-$var wire 32 ^ user_io_oeb_n [31:0] $end
-$var wire 32 _ user_io_out [31:0] $end
-$var wire 1 % vdd1v8 $end
-$var wire 1 & vdd3v3 $end
-$var wire 1 ' vss $end
-$var wire 1 ` xbar_ack_i_core $end
-$var wire 32 a xbar_dat_i_core [31:0] $end
-$var wire 1 b xbar_we_o_core $end
-$var wire 1 c xbar_stb_o_core $end
-$var wire 4 d xbar_sel_o_core [3:0] $end
-$var wire 32 e xbar_dat_o_core [31:0] $end
-$var wire 1 f xbar_cyc_o_core $end
-$var wire 32 g xbar_adr_o_core [31:0] $end
-$var wire 32 h user_io_in [31:0] $end
-$var wire 1 i porb_l $end
-$var wire 1 j porb_h $end
-$var wire 1 k pll_clk16 $end
-$var wire 1 l mprj_stb_o_core $end
-$var wire 32 m mprj_io_vtrip_sel [31:0] $end
-$var wire 32 n mprj_io_slow_sel [31:0] $end
-$var wire 32 o mprj_io_out [31:0] $end
-$var wire 1 p mprj_io_loader_resetn $end
-$var wire 1 q mprj_io_loader_data $end
-$var wire 1 r mprj_io_loader_clock $end
-$var wire 32 s mprj_io_inp_dis [31:0] $end
-$var wire 32 t mprj_io_in [31:0] $end
-$var wire 32 u mprj_io_ib_mode_sel [31:0] $end
-$var wire 32 v mprj_io_holdover [31:0] $end
-$var wire 96 w mprj_io_dm [95:0] $end
-$var wire 32 x mprj_io_analog_sel [31:0] $end
-$var wire 32 y mprj_io_analog_pol [31:0] $end
-$var wire 32 z mprj_io_analog_en [31:0] $end
-$var wire 32 { mprj_dat_i_core [31:0] $end
-$var wire 32 | mask_rev [31:0] $end
-$var wire 128 } la_output_core [127:0] $end
-$var wire 128 ~ la_oen [127:0] $end
-$var wire 128 !" la_data_out_mprj [127:0] $end
-$var wire 128 "" la_data_in_mprj [127:0] $end
-$var wire 32 #" gpio_serial_link_shifted [31:0] $end
-$var wire 32 $" gpio_serial_link [31:0] $end
-$var wire 1 %" gpio_outenb_core $end
-$var wire 1 &" gpio_out_core $end
-$var wire 1 '" gpio_mode1_core $end
-$var wire 1 (" gpio_mode0_core $end
-$var wire 1 )" gpio_inenb_core $end
-$var wire 1 *" gpio_in_core $end
-$var wire 1 +" flash_io1_oeb_core $end
-$var wire 1 ," flash_io1_ieb_core $end
-$var wire 1 -" flash_io1_do_core $end
-$var wire 1 ." flash_io1_di_core $end
-$var wire 1 /" flash_io0_oeb_core $end
-$var wire 1 0" flash_io0_ieb_core $end
-$var wire 1 1" flash_io0_do_core $end
-$var wire 1 2" flash_io0_di_core $end
-$var wire 1 3" flash_csb_oeb_core $end
-$var wire 1 4" flash_csb_core $end
-$var wire 1 5" flash_clk_oeb_core $end
-$var wire 1 6" flash_clk_core $end
-$var wire 1 7" clock_core $end
-$var wire 1 8" caravel_rstn $end
-$var wire 1 9" caravel_clk $end
-$scope module gpio_control_inst[0] $end
-$var wire 1 :" int_reset $end
-$var wire 1 ;" load_data $end
-$var wire 1 <" mgmt_gpio_io $end
-$var wire 1 =" pad_gpio_ana_en $end
-$var wire 1 >" pad_gpio_ana_pol $end
-$var wire 1 ?" pad_gpio_ana_sel $end
-$var wire 3 @" pad_gpio_dm [2:0] $end
-$var wire 1 A" pad_gpio_holdover $end
-$var wire 1 B" pad_gpio_ib_mode_sel $end
-$var wire 1 C" pad_gpio_in $end
-$var wire 1 D" pad_gpio_inenb $end
-$var wire 1 E" pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 F" pad_gpio_slow_sel $end
-$var wire 1 G" pad_gpio_vtrip_sel $end
-$var wire 1 H" serial_data_in $end
-$var wire 1 I" user_gpio_out $end
-$var wire 1 J" user_gpio_outenb $end
-$var wire 1 K" user_gpio_in $end
-$var wire 1 L" serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 =" gpio_ana_en $end
-$var reg 1 >" gpio_ana_pol $end
-$var reg 1 ?" gpio_ana_sel $end
-$var reg 3 M" gpio_dm [2:0] $end
-$var reg 1 A" gpio_holdover $end
-$var reg 1 B" gpio_ib_mode_sel $end
-$var reg 1 N" gpio_inenb $end
-$var reg 1 O" gpio_outenb $end
-$var reg 1 F" gpio_slow_sel $end
-$var reg 1 G" gpio_vtrip_sel $end
-$var reg 1 P" mgmt_ena $end
-$var reg 13 Q" shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[1] $end
-$var wire 1 R" int_reset $end
-$var wire 1 S" load_data $end
-$var wire 1 T" mgmt_gpio_io $end
-$var wire 1 U" pad_gpio_ana_en $end
-$var wire 1 V" pad_gpio_ana_pol $end
-$var wire 1 W" pad_gpio_ana_sel $end
-$var wire 3 X" pad_gpio_dm [2:0] $end
-$var wire 1 Y" pad_gpio_holdover $end
-$var wire 1 Z" pad_gpio_ib_mode_sel $end
-$var wire 1 [" pad_gpio_in $end
-$var wire 1 \" pad_gpio_inenb $end
-$var wire 1 ]" pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 ^" pad_gpio_slow_sel $end
-$var wire 1 _" pad_gpio_vtrip_sel $end
-$var wire 1 `" serial_data_in $end
-$var wire 1 a" user_gpio_out $end
-$var wire 1 b" user_gpio_outenb $end
-$var wire 1 c" user_gpio_in $end
-$var wire 1 d" serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 U" gpio_ana_en $end
-$var reg 1 V" gpio_ana_pol $end
-$var reg 1 W" gpio_ana_sel $end
-$var reg 3 e" gpio_dm [2:0] $end
-$var reg 1 Y" gpio_holdover $end
-$var reg 1 Z" gpio_ib_mode_sel $end
-$var reg 1 f" gpio_inenb $end
-$var reg 1 g" gpio_outenb $end
-$var reg 1 ^" gpio_slow_sel $end
-$var reg 1 _" gpio_vtrip_sel $end
-$var reg 1 h" mgmt_ena $end
-$var reg 13 i" shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[2] $end
-$var wire 1 j" int_reset $end
-$var wire 1 k" load_data $end
-$var wire 1 l" mgmt_gpio_io $end
-$var wire 1 m" pad_gpio_ana_en $end
-$var wire 1 n" pad_gpio_ana_pol $end
-$var wire 1 o" pad_gpio_ana_sel $end
-$var wire 3 p" pad_gpio_dm [2:0] $end
-$var wire 1 q" pad_gpio_holdover $end
-$var wire 1 r" pad_gpio_ib_mode_sel $end
-$var wire 1 s" pad_gpio_in $end
-$var wire 1 t" pad_gpio_inenb $end
-$var wire 1 u" pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 v" pad_gpio_slow_sel $end
-$var wire 1 w" pad_gpio_vtrip_sel $end
-$var wire 1 x" serial_data_in $end
-$var wire 1 y" user_gpio_out $end
-$var wire 1 z" user_gpio_outenb $end
-$var wire 1 {" user_gpio_in $end
-$var wire 1 |" serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 m" gpio_ana_en $end
-$var reg 1 n" gpio_ana_pol $end
-$var reg 1 o" gpio_ana_sel $end
-$var reg 3 }" gpio_dm [2:0] $end
-$var reg 1 q" gpio_holdover $end
-$var reg 1 r" gpio_ib_mode_sel $end
-$var reg 1 ~" gpio_inenb $end
-$var reg 1 !# gpio_outenb $end
-$var reg 1 v" gpio_slow_sel $end
-$var reg 1 w" gpio_vtrip_sel $end
-$var reg 1 "# mgmt_ena $end
-$var reg 13 ## shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[3] $end
-$var wire 1 $# int_reset $end
-$var wire 1 %# load_data $end
-$var wire 1 &# mgmt_gpio_io $end
-$var wire 1 '# pad_gpio_ana_en $end
-$var wire 1 (# pad_gpio_ana_pol $end
-$var wire 1 )# pad_gpio_ana_sel $end
-$var wire 3 *# pad_gpio_dm [2:0] $end
-$var wire 1 +# pad_gpio_holdover $end
-$var wire 1 ,# pad_gpio_ib_mode_sel $end
-$var wire 1 -# pad_gpio_in $end
-$var wire 1 .# pad_gpio_inenb $end
-$var wire 1 /# pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 0# pad_gpio_slow_sel $end
-$var wire 1 1# pad_gpio_vtrip_sel $end
-$var wire 1 2# serial_data_in $end
-$var wire 1 3# user_gpio_out $end
-$var wire 1 4# user_gpio_outenb $end
-$var wire 1 5# user_gpio_in $end
-$var wire 1 6# serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 '# gpio_ana_en $end
-$var reg 1 (# gpio_ana_pol $end
-$var reg 1 )# gpio_ana_sel $end
-$var reg 3 7# gpio_dm [2:0] $end
-$var reg 1 +# gpio_holdover $end
-$var reg 1 ,# gpio_ib_mode_sel $end
-$var reg 1 8# gpio_inenb $end
-$var reg 1 9# gpio_outenb $end
-$var reg 1 0# gpio_slow_sel $end
-$var reg 1 1# gpio_vtrip_sel $end
-$var reg 1 :# mgmt_ena $end
-$var reg 13 ;# shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[4] $end
-$var wire 1 <# int_reset $end
-$var wire 1 =# load_data $end
-$var wire 1 ># mgmt_gpio_io $end
-$var wire 1 ?# pad_gpio_ana_en $end
-$var wire 1 @# pad_gpio_ana_pol $end
-$var wire 1 A# pad_gpio_ana_sel $end
-$var wire 3 B# pad_gpio_dm [2:0] $end
-$var wire 1 C# pad_gpio_holdover $end
-$var wire 1 D# pad_gpio_ib_mode_sel $end
-$var wire 1 E# pad_gpio_in $end
-$var wire 1 F# pad_gpio_inenb $end
-$var wire 1 G# pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 H# pad_gpio_slow_sel $end
-$var wire 1 I# pad_gpio_vtrip_sel $end
-$var wire 1 J# serial_data_in $end
-$var wire 1 K# user_gpio_out $end
-$var wire 1 L# user_gpio_outenb $end
-$var wire 1 M# user_gpio_in $end
-$var wire 1 N# serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 ?# gpio_ana_en $end
-$var reg 1 @# gpio_ana_pol $end
-$var reg 1 A# gpio_ana_sel $end
-$var reg 3 O# gpio_dm [2:0] $end
-$var reg 1 C# gpio_holdover $end
-$var reg 1 D# gpio_ib_mode_sel $end
-$var reg 1 P# gpio_inenb $end
-$var reg 1 Q# gpio_outenb $end
-$var reg 1 H# gpio_slow_sel $end
-$var reg 1 I# gpio_vtrip_sel $end
-$var reg 1 R# mgmt_ena $end
-$var reg 13 S# shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[5] $end
-$var wire 1 T# int_reset $end
-$var wire 1 U# load_data $end
-$var wire 1 V# mgmt_gpio_io $end
-$var wire 1 W# pad_gpio_ana_en $end
-$var wire 1 X# pad_gpio_ana_pol $end
-$var wire 1 Y# pad_gpio_ana_sel $end
-$var wire 3 Z# pad_gpio_dm [2:0] $end
-$var wire 1 [# pad_gpio_holdover $end
-$var wire 1 \# pad_gpio_ib_mode_sel $end
-$var wire 1 ]# pad_gpio_in $end
-$var wire 1 ^# pad_gpio_inenb $end
-$var wire 1 _# pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 `# pad_gpio_slow_sel $end
-$var wire 1 a# pad_gpio_vtrip_sel $end
-$var wire 1 b# serial_data_in $end
-$var wire 1 c# user_gpio_out $end
-$var wire 1 d# user_gpio_outenb $end
-$var wire 1 e# user_gpio_in $end
-$var wire 1 f# serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 W# gpio_ana_en $end
-$var reg 1 X# gpio_ana_pol $end
-$var reg 1 Y# gpio_ana_sel $end
-$var reg 3 g# gpio_dm [2:0] $end
-$var reg 1 [# gpio_holdover $end
-$var reg 1 \# gpio_ib_mode_sel $end
-$var reg 1 h# gpio_inenb $end
-$var reg 1 i# gpio_outenb $end
-$var reg 1 `# gpio_slow_sel $end
-$var reg 1 a# gpio_vtrip_sel $end
-$var reg 1 j# mgmt_ena $end
-$var reg 13 k# shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[6] $end
-$var wire 1 l# int_reset $end
-$var wire 1 m# load_data $end
-$var wire 1 n# mgmt_gpio_io $end
-$var wire 1 o# pad_gpio_ana_en $end
-$var wire 1 p# pad_gpio_ana_pol $end
-$var wire 1 q# pad_gpio_ana_sel $end
-$var wire 3 r# pad_gpio_dm [2:0] $end
-$var wire 1 s# pad_gpio_holdover $end
-$var wire 1 t# pad_gpio_ib_mode_sel $end
-$var wire 1 u# pad_gpio_in $end
-$var wire 1 v# pad_gpio_inenb $end
-$var wire 1 w# pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 x# pad_gpio_slow_sel $end
-$var wire 1 y# pad_gpio_vtrip_sel $end
-$var wire 1 z# serial_data_in $end
-$var wire 1 {# user_gpio_out $end
-$var wire 1 |# user_gpio_outenb $end
-$var wire 1 }# user_gpio_in $end
-$var wire 1 ~# serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 o# gpio_ana_en $end
-$var reg 1 p# gpio_ana_pol $end
-$var reg 1 q# gpio_ana_sel $end
-$var reg 3 !$ gpio_dm [2:0] $end
-$var reg 1 s# gpio_holdover $end
-$var reg 1 t# gpio_ib_mode_sel $end
-$var reg 1 "$ gpio_inenb $end
-$var reg 1 #$ gpio_outenb $end
-$var reg 1 x# gpio_slow_sel $end
-$var reg 1 y# gpio_vtrip_sel $end
-$var reg 1 $$ mgmt_ena $end
-$var reg 13 %$ shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[7] $end
-$var wire 1 &$ int_reset $end
-$var wire 1 '$ load_data $end
-$var wire 1 ($ mgmt_gpio_io $end
-$var wire 1 )$ pad_gpio_ana_en $end
-$var wire 1 *$ pad_gpio_ana_pol $end
-$var wire 1 +$ pad_gpio_ana_sel $end
-$var wire 3 ,$ pad_gpio_dm [2:0] $end
-$var wire 1 -$ pad_gpio_holdover $end
-$var wire 1 .$ pad_gpio_ib_mode_sel $end
-$var wire 1 /$ pad_gpio_in $end
-$var wire 1 0$ pad_gpio_inenb $end
-$var wire 1 1$ pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 2$ pad_gpio_slow_sel $end
-$var wire 1 3$ pad_gpio_vtrip_sel $end
-$var wire 1 4$ serial_data_in $end
-$var wire 1 5$ user_gpio_out $end
-$var wire 1 6$ user_gpio_outenb $end
-$var wire 1 7$ user_gpio_in $end
-$var wire 1 8$ serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 )$ gpio_ana_en $end
-$var reg 1 *$ gpio_ana_pol $end
-$var reg 1 +$ gpio_ana_sel $end
-$var reg 3 9$ gpio_dm [2:0] $end
-$var reg 1 -$ gpio_holdover $end
-$var reg 1 .$ gpio_ib_mode_sel $end
-$var reg 1 :$ gpio_inenb $end
-$var reg 1 ;$ gpio_outenb $end
-$var reg 1 2$ gpio_slow_sel $end
-$var reg 1 3$ gpio_vtrip_sel $end
-$var reg 1 <$ mgmt_ena $end
-$var reg 13 =$ shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[8] $end
-$var wire 1 >$ int_reset $end
-$var wire 1 ?$ load_data $end
-$var wire 1 @$ mgmt_gpio_io $end
-$var wire 1 A$ pad_gpio_ana_en $end
-$var wire 1 B$ pad_gpio_ana_pol $end
-$var wire 1 C$ pad_gpio_ana_sel $end
-$var wire 3 D$ pad_gpio_dm [2:0] $end
-$var wire 1 E$ pad_gpio_holdover $end
-$var wire 1 F$ pad_gpio_ib_mode_sel $end
-$var wire 1 G$ pad_gpio_in $end
-$var wire 1 H$ pad_gpio_inenb $end
-$var wire 1 I$ pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 J$ pad_gpio_slow_sel $end
-$var wire 1 K$ pad_gpio_vtrip_sel $end
-$var wire 1 L$ serial_data_in $end
-$var wire 1 M$ user_gpio_out $end
-$var wire 1 N$ user_gpio_outenb $end
-$var wire 1 O$ user_gpio_in $end
-$var wire 1 P$ serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 A$ gpio_ana_en $end
-$var reg 1 B$ gpio_ana_pol $end
-$var reg 1 C$ gpio_ana_sel $end
-$var reg 3 Q$ gpio_dm [2:0] $end
-$var reg 1 E$ gpio_holdover $end
-$var reg 1 F$ gpio_ib_mode_sel $end
-$var reg 1 R$ gpio_inenb $end
-$var reg 1 S$ gpio_outenb $end
-$var reg 1 J$ gpio_slow_sel $end
-$var reg 1 K$ gpio_vtrip_sel $end
-$var reg 1 T$ mgmt_ena $end
-$var reg 13 U$ shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[9] $end
-$var wire 1 V$ int_reset $end
-$var wire 1 W$ load_data $end
-$var wire 1 X$ mgmt_gpio_io $end
-$var wire 1 Y$ pad_gpio_ana_en $end
-$var wire 1 Z$ pad_gpio_ana_pol $end
-$var wire 1 [$ pad_gpio_ana_sel $end
-$var wire 3 \$ pad_gpio_dm [2:0] $end
-$var wire 1 ]$ pad_gpio_holdover $end
-$var wire 1 ^$ pad_gpio_ib_mode_sel $end
-$var wire 1 _$ pad_gpio_in $end
-$var wire 1 `$ pad_gpio_inenb $end
-$var wire 1 a$ pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 b$ pad_gpio_slow_sel $end
-$var wire 1 c$ pad_gpio_vtrip_sel $end
-$var wire 1 d$ serial_data_in $end
-$var wire 1 e$ user_gpio_out $end
-$var wire 1 f$ user_gpio_outenb $end
-$var wire 1 g$ user_gpio_in $end
-$var wire 1 h$ serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 Y$ gpio_ana_en $end
-$var reg 1 Z$ gpio_ana_pol $end
-$var reg 1 [$ gpio_ana_sel $end
-$var reg 3 i$ gpio_dm [2:0] $end
-$var reg 1 ]$ gpio_holdover $end
-$var reg 1 ^$ gpio_ib_mode_sel $end
-$var reg 1 j$ gpio_inenb $end
-$var reg 1 k$ gpio_outenb $end
-$var reg 1 b$ gpio_slow_sel $end
-$var reg 1 c$ gpio_vtrip_sel $end
-$var reg 1 l$ mgmt_ena $end
-$var reg 13 m$ shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[10] $end
-$var wire 1 n$ int_reset $end
-$var wire 1 o$ load_data $end
-$var wire 1 p$ mgmt_gpio_io $end
-$var wire 1 q$ pad_gpio_ana_en $end
-$var wire 1 r$ pad_gpio_ana_pol $end
-$var wire 1 s$ pad_gpio_ana_sel $end
-$var wire 3 t$ pad_gpio_dm [2:0] $end
-$var wire 1 u$ pad_gpio_holdover $end
-$var wire 1 v$ pad_gpio_ib_mode_sel $end
-$var wire 1 w$ pad_gpio_in $end
-$var wire 1 x$ pad_gpio_inenb $end
-$var wire 1 y$ pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 z$ pad_gpio_slow_sel $end
-$var wire 1 {$ pad_gpio_vtrip_sel $end
-$var wire 1 |$ serial_data_in $end
-$var wire 1 }$ user_gpio_out $end
-$var wire 1 ~$ user_gpio_outenb $end
-$var wire 1 !% user_gpio_in $end
-$var wire 1 "% serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 q$ gpio_ana_en $end
-$var reg 1 r$ gpio_ana_pol $end
-$var reg 1 s$ gpio_ana_sel $end
-$var reg 3 #% gpio_dm [2:0] $end
-$var reg 1 u$ gpio_holdover $end
-$var reg 1 v$ gpio_ib_mode_sel $end
-$var reg 1 $% gpio_inenb $end
-$var reg 1 %% gpio_outenb $end
-$var reg 1 z$ gpio_slow_sel $end
-$var reg 1 {$ gpio_vtrip_sel $end
-$var reg 1 &% mgmt_ena $end
-$var reg 13 '% shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[11] $end
-$var wire 1 (% int_reset $end
-$var wire 1 )% load_data $end
-$var wire 1 *% mgmt_gpio_io $end
-$var wire 1 +% pad_gpio_ana_en $end
-$var wire 1 ,% pad_gpio_ana_pol $end
-$var wire 1 -% pad_gpio_ana_sel $end
-$var wire 3 .% pad_gpio_dm [2:0] $end
-$var wire 1 /% pad_gpio_holdover $end
-$var wire 1 0% pad_gpio_ib_mode_sel $end
-$var wire 1 1% pad_gpio_in $end
-$var wire 1 2% pad_gpio_inenb $end
-$var wire 1 3% pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 4% pad_gpio_slow_sel $end
-$var wire 1 5% pad_gpio_vtrip_sel $end
-$var wire 1 6% serial_data_in $end
-$var wire 1 7% user_gpio_out $end
-$var wire 1 8% user_gpio_outenb $end
-$var wire 1 9% user_gpio_in $end
-$var wire 1 :% serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 +% gpio_ana_en $end
-$var reg 1 ,% gpio_ana_pol $end
-$var reg 1 -% gpio_ana_sel $end
-$var reg 3 ;% gpio_dm [2:0] $end
-$var reg 1 /% gpio_holdover $end
-$var reg 1 0% gpio_ib_mode_sel $end
-$var reg 1 <% gpio_inenb $end
-$var reg 1 =% gpio_outenb $end
-$var reg 1 4% gpio_slow_sel $end
-$var reg 1 5% gpio_vtrip_sel $end
-$var reg 1 >% mgmt_ena $end
-$var reg 13 ?% shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[12] $end
-$var wire 1 @% int_reset $end
-$var wire 1 A% load_data $end
-$var wire 1 B% mgmt_gpio_io $end
-$var wire 1 C% pad_gpio_ana_en $end
-$var wire 1 D% pad_gpio_ana_pol $end
-$var wire 1 E% pad_gpio_ana_sel $end
-$var wire 3 F% pad_gpio_dm [2:0] $end
-$var wire 1 G% pad_gpio_holdover $end
-$var wire 1 H% pad_gpio_ib_mode_sel $end
-$var wire 1 I% pad_gpio_in $end
-$var wire 1 J% pad_gpio_inenb $end
-$var wire 1 K% pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 L% pad_gpio_slow_sel $end
-$var wire 1 M% pad_gpio_vtrip_sel $end
-$var wire 1 N% serial_data_in $end
-$var wire 1 O% user_gpio_out $end
-$var wire 1 P% user_gpio_outenb $end
-$var wire 1 Q% user_gpio_in $end
-$var wire 1 R% serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 C% gpio_ana_en $end
-$var reg 1 D% gpio_ana_pol $end
-$var reg 1 E% gpio_ana_sel $end
-$var reg 3 S% gpio_dm [2:0] $end
-$var reg 1 G% gpio_holdover $end
-$var reg 1 H% gpio_ib_mode_sel $end
-$var reg 1 T% gpio_inenb $end
-$var reg 1 U% gpio_outenb $end
-$var reg 1 L% gpio_slow_sel $end
-$var reg 1 M% gpio_vtrip_sel $end
-$var reg 1 V% mgmt_ena $end
-$var reg 13 W% shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[13] $end
-$var wire 1 X% int_reset $end
-$var wire 1 Y% load_data $end
-$var wire 1 Z% mgmt_gpio_io $end
-$var wire 1 [% pad_gpio_ana_en $end
-$var wire 1 \% pad_gpio_ana_pol $end
-$var wire 1 ]% pad_gpio_ana_sel $end
-$var wire 3 ^% pad_gpio_dm [2:0] $end
-$var wire 1 _% pad_gpio_holdover $end
-$var wire 1 `% pad_gpio_ib_mode_sel $end
-$var wire 1 a% pad_gpio_in $end
-$var wire 1 b% pad_gpio_inenb $end
-$var wire 1 c% pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 d% pad_gpio_slow_sel $end
-$var wire 1 e% pad_gpio_vtrip_sel $end
-$var wire 1 f% serial_data_in $end
-$var wire 1 g% user_gpio_out $end
-$var wire 1 h% user_gpio_outenb $end
-$var wire 1 i% user_gpio_in $end
-$var wire 1 j% serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 [% gpio_ana_en $end
-$var reg 1 \% gpio_ana_pol $end
-$var reg 1 ]% gpio_ana_sel $end
-$var reg 3 k% gpio_dm [2:0] $end
-$var reg 1 _% gpio_holdover $end
-$var reg 1 `% gpio_ib_mode_sel $end
-$var reg 1 l% gpio_inenb $end
-$var reg 1 m% gpio_outenb $end
-$var reg 1 d% gpio_slow_sel $end
-$var reg 1 e% gpio_vtrip_sel $end
-$var reg 1 n% mgmt_ena $end
-$var reg 13 o% shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[14] $end
-$var wire 1 p% int_reset $end
-$var wire 1 q% load_data $end
-$var wire 1 r% mgmt_gpio_io $end
-$var wire 1 s% pad_gpio_ana_en $end
-$var wire 1 t% pad_gpio_ana_pol $end
-$var wire 1 u% pad_gpio_ana_sel $end
-$var wire 3 v% pad_gpio_dm [2:0] $end
-$var wire 1 w% pad_gpio_holdover $end
-$var wire 1 x% pad_gpio_ib_mode_sel $end
-$var wire 1 y% pad_gpio_in $end
-$var wire 1 z% pad_gpio_inenb $end
-$var wire 1 {% pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 |% pad_gpio_slow_sel $end
-$var wire 1 }% pad_gpio_vtrip_sel $end
-$var wire 1 ~% serial_data_in $end
-$var wire 1 !& user_gpio_out $end
-$var wire 1 "& user_gpio_outenb $end
-$var wire 1 #& user_gpio_in $end
-$var wire 1 $& serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 s% gpio_ana_en $end
-$var reg 1 t% gpio_ana_pol $end
-$var reg 1 u% gpio_ana_sel $end
-$var reg 3 %& gpio_dm [2:0] $end
-$var reg 1 w% gpio_holdover $end
-$var reg 1 x% gpio_ib_mode_sel $end
-$var reg 1 && gpio_inenb $end
-$var reg 1 '& gpio_outenb $end
-$var reg 1 |% gpio_slow_sel $end
-$var reg 1 }% gpio_vtrip_sel $end
-$var reg 1 (& mgmt_ena $end
-$var reg 13 )& shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[15] $end
-$var wire 1 *& int_reset $end
-$var wire 1 +& load_data $end
-$var wire 1 ,& mgmt_gpio_io $end
-$var wire 1 -& pad_gpio_ana_en $end
-$var wire 1 .& pad_gpio_ana_pol $end
-$var wire 1 /& pad_gpio_ana_sel $end
-$var wire 3 0& pad_gpio_dm [2:0] $end
-$var wire 1 1& pad_gpio_holdover $end
-$var wire 1 2& pad_gpio_ib_mode_sel $end
-$var wire 1 3& pad_gpio_in $end
-$var wire 1 4& pad_gpio_inenb $end
-$var wire 1 5& pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 6& pad_gpio_slow_sel $end
-$var wire 1 7& pad_gpio_vtrip_sel $end
-$var wire 1 8& serial_data_in $end
-$var wire 1 9& user_gpio_out $end
-$var wire 1 :& user_gpio_outenb $end
-$var wire 1 ;& user_gpio_in $end
-$var wire 1 <& serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 -& gpio_ana_en $end
-$var reg 1 .& gpio_ana_pol $end
-$var reg 1 /& gpio_ana_sel $end
-$var reg 3 =& gpio_dm [2:0] $end
-$var reg 1 1& gpio_holdover $end
-$var reg 1 2& gpio_ib_mode_sel $end
-$var reg 1 >& gpio_inenb $end
-$var reg 1 ?& gpio_outenb $end
-$var reg 1 6& gpio_slow_sel $end
-$var reg 1 7& gpio_vtrip_sel $end
-$var reg 1 @& mgmt_ena $end
-$var reg 13 A& shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[16] $end
-$var wire 1 B& int_reset $end
-$var wire 1 C& load_data $end
-$var wire 1 D& mgmt_gpio_io $end
-$var wire 1 E& pad_gpio_ana_en $end
-$var wire 1 F& pad_gpio_ana_pol $end
-$var wire 1 G& pad_gpio_ana_sel $end
-$var wire 3 H& pad_gpio_dm [2:0] $end
-$var wire 1 I& pad_gpio_holdover $end
-$var wire 1 J& pad_gpio_ib_mode_sel $end
-$var wire 1 K& pad_gpio_in $end
-$var wire 1 L& pad_gpio_inenb $end
-$var wire 1 M& pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 N& pad_gpio_slow_sel $end
-$var wire 1 O& pad_gpio_vtrip_sel $end
-$var wire 1 P& serial_data_in $end
-$var wire 1 Q& user_gpio_out $end
-$var wire 1 R& user_gpio_outenb $end
-$var wire 1 S& user_gpio_in $end
-$var wire 1 T& serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 E& gpio_ana_en $end
-$var reg 1 F& gpio_ana_pol $end
-$var reg 1 G& gpio_ana_sel $end
-$var reg 3 U& gpio_dm [2:0] $end
-$var reg 1 I& gpio_holdover $end
-$var reg 1 J& gpio_ib_mode_sel $end
-$var reg 1 V& gpio_inenb $end
-$var reg 1 W& gpio_outenb $end
-$var reg 1 N& gpio_slow_sel $end
-$var reg 1 O& gpio_vtrip_sel $end
-$var reg 1 X& mgmt_ena $end
-$var reg 13 Y& shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[17] $end
-$var wire 1 Z& int_reset $end
-$var wire 1 [& load_data $end
-$var wire 1 \& mgmt_gpio_io $end
-$var wire 1 ]& pad_gpio_ana_en $end
-$var wire 1 ^& pad_gpio_ana_pol $end
-$var wire 1 _& pad_gpio_ana_sel $end
-$var wire 3 `& pad_gpio_dm [2:0] $end
-$var wire 1 a& pad_gpio_holdover $end
-$var wire 1 b& pad_gpio_ib_mode_sel $end
-$var wire 1 c& pad_gpio_in $end
-$var wire 1 d& pad_gpio_inenb $end
-$var wire 1 e& pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 f& pad_gpio_slow_sel $end
-$var wire 1 g& pad_gpio_vtrip_sel $end
-$var wire 1 h& serial_data_in $end
-$var wire 1 i& user_gpio_out $end
-$var wire 1 j& user_gpio_outenb $end
-$var wire 1 k& user_gpio_in $end
-$var wire 1 l& serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 ]& gpio_ana_en $end
-$var reg 1 ^& gpio_ana_pol $end
-$var reg 1 _& gpio_ana_sel $end
-$var reg 3 m& gpio_dm [2:0] $end
-$var reg 1 a& gpio_holdover $end
-$var reg 1 b& gpio_ib_mode_sel $end
-$var reg 1 n& gpio_inenb $end
-$var reg 1 o& gpio_outenb $end
-$var reg 1 f& gpio_slow_sel $end
-$var reg 1 g& gpio_vtrip_sel $end
-$var reg 1 p& mgmt_ena $end
-$var reg 13 q& shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[18] $end
-$var wire 1 r& int_reset $end
-$var wire 1 s& load_data $end
-$var wire 1 t& mgmt_gpio_io $end
-$var wire 1 u& pad_gpio_ana_en $end
-$var wire 1 v& pad_gpio_ana_pol $end
-$var wire 1 w& pad_gpio_ana_sel $end
-$var wire 3 x& pad_gpio_dm [2:0] $end
-$var wire 1 y& pad_gpio_holdover $end
-$var wire 1 z& pad_gpio_ib_mode_sel $end
-$var wire 1 {& pad_gpio_in $end
-$var wire 1 |& pad_gpio_inenb $end
-$var wire 1 }& pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 ~& pad_gpio_slow_sel $end
-$var wire 1 !' pad_gpio_vtrip_sel $end
-$var wire 1 "' serial_data_in $end
-$var wire 1 #' user_gpio_out $end
-$var wire 1 $' user_gpio_outenb $end
-$var wire 1 %' user_gpio_in $end
-$var wire 1 &' serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 u& gpio_ana_en $end
-$var reg 1 v& gpio_ana_pol $end
-$var reg 1 w& gpio_ana_sel $end
-$var reg 3 '' gpio_dm [2:0] $end
-$var reg 1 y& gpio_holdover $end
-$var reg 1 z& gpio_ib_mode_sel $end
-$var reg 1 (' gpio_inenb $end
-$var reg 1 )' gpio_outenb $end
-$var reg 1 ~& gpio_slow_sel $end
-$var reg 1 !' gpio_vtrip_sel $end
-$var reg 1 *' mgmt_ena $end
-$var reg 13 +' shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[19] $end
-$var wire 1 ,' int_reset $end
-$var wire 1 -' load_data $end
-$var wire 1 .' mgmt_gpio_io $end
-$var wire 1 /' pad_gpio_ana_en $end
-$var wire 1 0' pad_gpio_ana_pol $end
-$var wire 1 1' pad_gpio_ana_sel $end
-$var wire 3 2' pad_gpio_dm [2:0] $end
-$var wire 1 3' pad_gpio_holdover $end
-$var wire 1 4' pad_gpio_ib_mode_sel $end
-$var wire 1 5' pad_gpio_in $end
-$var wire 1 6' pad_gpio_inenb $end
-$var wire 1 7' pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 8' pad_gpio_slow_sel $end
-$var wire 1 9' pad_gpio_vtrip_sel $end
-$var wire 1 :' serial_data_in $end
-$var wire 1 ;' user_gpio_out $end
-$var wire 1 <' user_gpio_outenb $end
-$var wire 1 =' user_gpio_in $end
-$var wire 1 >' serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 /' gpio_ana_en $end
-$var reg 1 0' gpio_ana_pol $end
-$var reg 1 1' gpio_ana_sel $end
-$var reg 3 ?' gpio_dm [2:0] $end
-$var reg 1 3' gpio_holdover $end
-$var reg 1 4' gpio_ib_mode_sel $end
-$var reg 1 @' gpio_inenb $end
-$var reg 1 A' gpio_outenb $end
-$var reg 1 8' gpio_slow_sel $end
-$var reg 1 9' gpio_vtrip_sel $end
-$var reg 1 B' mgmt_ena $end
-$var reg 13 C' shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[20] $end
-$var wire 1 D' int_reset $end
-$var wire 1 E' load_data $end
-$var wire 1 F' mgmt_gpio_io $end
-$var wire 1 G' pad_gpio_ana_en $end
-$var wire 1 H' pad_gpio_ana_pol $end
-$var wire 1 I' pad_gpio_ana_sel $end
-$var wire 3 J' pad_gpio_dm [2:0] $end
-$var wire 1 K' pad_gpio_holdover $end
-$var wire 1 L' pad_gpio_ib_mode_sel $end
-$var wire 1 M' pad_gpio_in $end
-$var wire 1 N' pad_gpio_inenb $end
-$var wire 1 O' pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 P' pad_gpio_slow_sel $end
-$var wire 1 Q' pad_gpio_vtrip_sel $end
-$var wire 1 R' serial_data_in $end
-$var wire 1 S' user_gpio_out $end
-$var wire 1 T' user_gpio_outenb $end
-$var wire 1 U' user_gpio_in $end
-$var wire 1 V' serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 G' gpio_ana_en $end
-$var reg 1 H' gpio_ana_pol $end
-$var reg 1 I' gpio_ana_sel $end
-$var reg 3 W' gpio_dm [2:0] $end
-$var reg 1 K' gpio_holdover $end
-$var reg 1 L' gpio_ib_mode_sel $end
-$var reg 1 X' gpio_inenb $end
-$var reg 1 Y' gpio_outenb $end
-$var reg 1 P' gpio_slow_sel $end
-$var reg 1 Q' gpio_vtrip_sel $end
-$var reg 1 Z' mgmt_ena $end
-$var reg 13 [' shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[21] $end
-$var wire 1 \' int_reset $end
-$var wire 1 ]' load_data $end
-$var wire 1 ^' mgmt_gpio_io $end
-$var wire 1 _' pad_gpio_ana_en $end
-$var wire 1 `' pad_gpio_ana_pol $end
-$var wire 1 a' pad_gpio_ana_sel $end
-$var wire 3 b' pad_gpio_dm [2:0] $end
-$var wire 1 c' pad_gpio_holdover $end
-$var wire 1 d' pad_gpio_ib_mode_sel $end
-$var wire 1 e' pad_gpio_in $end
-$var wire 1 f' pad_gpio_inenb $end
-$var wire 1 g' pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 h' pad_gpio_slow_sel $end
-$var wire 1 i' pad_gpio_vtrip_sel $end
-$var wire 1 j' serial_data_in $end
-$var wire 1 k' user_gpio_out $end
-$var wire 1 l' user_gpio_outenb $end
-$var wire 1 m' user_gpio_in $end
-$var wire 1 n' serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 _' gpio_ana_en $end
-$var reg 1 `' gpio_ana_pol $end
-$var reg 1 a' gpio_ana_sel $end
-$var reg 3 o' gpio_dm [2:0] $end
-$var reg 1 c' gpio_holdover $end
-$var reg 1 d' gpio_ib_mode_sel $end
-$var reg 1 p' gpio_inenb $end
-$var reg 1 q' gpio_outenb $end
-$var reg 1 h' gpio_slow_sel $end
-$var reg 1 i' gpio_vtrip_sel $end
-$var reg 1 r' mgmt_ena $end
-$var reg 13 s' shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[22] $end
-$var wire 1 t' int_reset $end
-$var wire 1 u' load_data $end
-$var wire 1 v' mgmt_gpio_io $end
-$var wire 1 w' pad_gpio_ana_en $end
-$var wire 1 x' pad_gpio_ana_pol $end
-$var wire 1 y' pad_gpio_ana_sel $end
-$var wire 3 z' pad_gpio_dm [2:0] $end
-$var wire 1 {' pad_gpio_holdover $end
-$var wire 1 |' pad_gpio_ib_mode_sel $end
-$var wire 1 }' pad_gpio_in $end
-$var wire 1 ~' pad_gpio_inenb $end
-$var wire 1 !( pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 "( pad_gpio_slow_sel $end
-$var wire 1 #( pad_gpio_vtrip_sel $end
-$var wire 1 $( serial_data_in $end
-$var wire 1 %( user_gpio_out $end
-$var wire 1 &( user_gpio_outenb $end
-$var wire 1 '( user_gpio_in $end
-$var wire 1 (( serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 w' gpio_ana_en $end
-$var reg 1 x' gpio_ana_pol $end
-$var reg 1 y' gpio_ana_sel $end
-$var reg 3 )( gpio_dm [2:0] $end
-$var reg 1 {' gpio_holdover $end
-$var reg 1 |' gpio_ib_mode_sel $end
-$var reg 1 *( gpio_inenb $end
-$var reg 1 +( gpio_outenb $end
-$var reg 1 "( gpio_slow_sel $end
-$var reg 1 #( gpio_vtrip_sel $end
-$var reg 1 ,( mgmt_ena $end
-$var reg 13 -( shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[23] $end
-$var wire 1 .( int_reset $end
-$var wire 1 /( load_data $end
-$var wire 1 0( mgmt_gpio_io $end
-$var wire 1 1( pad_gpio_ana_en $end
-$var wire 1 2( pad_gpio_ana_pol $end
-$var wire 1 3( pad_gpio_ana_sel $end
-$var wire 3 4( pad_gpio_dm [2:0] $end
-$var wire 1 5( pad_gpio_holdover $end
-$var wire 1 6( pad_gpio_ib_mode_sel $end
-$var wire 1 7( pad_gpio_in $end
-$var wire 1 8( pad_gpio_inenb $end
-$var wire 1 9( pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 :( pad_gpio_slow_sel $end
-$var wire 1 ;( pad_gpio_vtrip_sel $end
-$var wire 1 <( serial_data_in $end
-$var wire 1 =( user_gpio_out $end
-$var wire 1 >( user_gpio_outenb $end
-$var wire 1 ?( user_gpio_in $end
-$var wire 1 @( serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 1( gpio_ana_en $end
-$var reg 1 2( gpio_ana_pol $end
-$var reg 1 3( gpio_ana_sel $end
-$var reg 3 A( gpio_dm [2:0] $end
-$var reg 1 5( gpio_holdover $end
-$var reg 1 6( gpio_ib_mode_sel $end
-$var reg 1 B( gpio_inenb $end
-$var reg 1 C( gpio_outenb $end
-$var reg 1 :( gpio_slow_sel $end
-$var reg 1 ;( gpio_vtrip_sel $end
-$var reg 1 D( mgmt_ena $end
-$var reg 13 E( shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[24] $end
-$var wire 1 F( int_reset $end
-$var wire 1 G( load_data $end
-$var wire 1 H( mgmt_gpio_io $end
-$var wire 1 I( pad_gpio_ana_en $end
-$var wire 1 J( pad_gpio_ana_pol $end
-$var wire 1 K( pad_gpio_ana_sel $end
-$var wire 3 L( pad_gpio_dm [2:0] $end
-$var wire 1 M( pad_gpio_holdover $end
-$var wire 1 N( pad_gpio_ib_mode_sel $end
-$var wire 1 O( pad_gpio_in $end
-$var wire 1 P( pad_gpio_inenb $end
-$var wire 1 Q( pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 R( pad_gpio_slow_sel $end
-$var wire 1 S( pad_gpio_vtrip_sel $end
-$var wire 1 T( serial_data_in $end
-$var wire 1 U( user_gpio_out $end
-$var wire 1 V( user_gpio_outenb $end
-$var wire 1 W( user_gpio_in $end
-$var wire 1 X( serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 I( gpio_ana_en $end
-$var reg 1 J( gpio_ana_pol $end
-$var reg 1 K( gpio_ana_sel $end
-$var reg 3 Y( gpio_dm [2:0] $end
-$var reg 1 M( gpio_holdover $end
-$var reg 1 N( gpio_ib_mode_sel $end
-$var reg 1 Z( gpio_inenb $end
-$var reg 1 [( gpio_outenb $end
-$var reg 1 R( gpio_slow_sel $end
-$var reg 1 S( gpio_vtrip_sel $end
-$var reg 1 \( mgmt_ena $end
-$var reg 13 ]( shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[25] $end
-$var wire 1 ^( int_reset $end
-$var wire 1 _( load_data $end
-$var wire 1 `( mgmt_gpio_io $end
-$var wire 1 a( pad_gpio_ana_en $end
-$var wire 1 b( pad_gpio_ana_pol $end
-$var wire 1 c( pad_gpio_ana_sel $end
-$var wire 3 d( pad_gpio_dm [2:0] $end
-$var wire 1 e( pad_gpio_holdover $end
-$var wire 1 f( pad_gpio_ib_mode_sel $end
-$var wire 1 g( pad_gpio_in $end
-$var wire 1 h( pad_gpio_inenb $end
-$var wire 1 i( pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 j( pad_gpio_slow_sel $end
-$var wire 1 k( pad_gpio_vtrip_sel $end
-$var wire 1 l( serial_data_in $end
-$var wire 1 m( user_gpio_out $end
-$var wire 1 n( user_gpio_outenb $end
-$var wire 1 o( user_gpio_in $end
-$var wire 1 p( serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 a( gpio_ana_en $end
-$var reg 1 b( gpio_ana_pol $end
-$var reg 1 c( gpio_ana_sel $end
-$var reg 3 q( gpio_dm [2:0] $end
-$var reg 1 e( gpio_holdover $end
-$var reg 1 f( gpio_ib_mode_sel $end
-$var reg 1 r( gpio_inenb $end
-$var reg 1 s( gpio_outenb $end
-$var reg 1 j( gpio_slow_sel $end
-$var reg 1 k( gpio_vtrip_sel $end
-$var reg 1 t( mgmt_ena $end
-$var reg 13 u( shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[26] $end
-$var wire 1 v( int_reset $end
-$var wire 1 w( load_data $end
-$var wire 1 x( mgmt_gpio_io $end
-$var wire 1 y( pad_gpio_ana_en $end
-$var wire 1 z( pad_gpio_ana_pol $end
-$var wire 1 {( pad_gpio_ana_sel $end
-$var wire 3 |( pad_gpio_dm [2:0] $end
-$var wire 1 }( pad_gpio_holdover $end
-$var wire 1 ~( pad_gpio_ib_mode_sel $end
-$var wire 1 !) pad_gpio_in $end
-$var wire 1 ") pad_gpio_inenb $end
-$var wire 1 #) pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 $) pad_gpio_slow_sel $end
-$var wire 1 %) pad_gpio_vtrip_sel $end
-$var wire 1 &) serial_data_in $end
-$var wire 1 ') user_gpio_out $end
-$var wire 1 () user_gpio_outenb $end
-$var wire 1 )) user_gpio_in $end
-$var wire 1 *) serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 y( gpio_ana_en $end
-$var reg 1 z( gpio_ana_pol $end
-$var reg 1 {( gpio_ana_sel $end
-$var reg 3 +) gpio_dm [2:0] $end
-$var reg 1 }( gpio_holdover $end
-$var reg 1 ~( gpio_ib_mode_sel $end
-$var reg 1 ,) gpio_inenb $end
-$var reg 1 -) gpio_outenb $end
-$var reg 1 $) gpio_slow_sel $end
-$var reg 1 %) gpio_vtrip_sel $end
-$var reg 1 .) mgmt_ena $end
-$var reg 13 /) shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[27] $end
-$var wire 1 0) int_reset $end
-$var wire 1 1) load_data $end
-$var wire 1 2) mgmt_gpio_io $end
-$var wire 1 3) pad_gpio_ana_en $end
-$var wire 1 4) pad_gpio_ana_pol $end
-$var wire 1 5) pad_gpio_ana_sel $end
-$var wire 3 6) pad_gpio_dm [2:0] $end
-$var wire 1 7) pad_gpio_holdover $end
-$var wire 1 8) pad_gpio_ib_mode_sel $end
-$var wire 1 9) pad_gpio_in $end
-$var wire 1 :) pad_gpio_inenb $end
-$var wire 1 ;) pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 <) pad_gpio_slow_sel $end
-$var wire 1 =) pad_gpio_vtrip_sel $end
-$var wire 1 >) serial_data_in $end
-$var wire 1 ?) user_gpio_out $end
-$var wire 1 @) user_gpio_outenb $end
-$var wire 1 A) user_gpio_in $end
-$var wire 1 B) serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 3) gpio_ana_en $end
-$var reg 1 4) gpio_ana_pol $end
-$var reg 1 5) gpio_ana_sel $end
-$var reg 3 C) gpio_dm [2:0] $end
-$var reg 1 7) gpio_holdover $end
-$var reg 1 8) gpio_ib_mode_sel $end
-$var reg 1 D) gpio_inenb $end
-$var reg 1 E) gpio_outenb $end
-$var reg 1 <) gpio_slow_sel $end
-$var reg 1 =) gpio_vtrip_sel $end
-$var reg 1 F) mgmt_ena $end
-$var reg 13 G) shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[28] $end
-$var wire 1 H) int_reset $end
-$var wire 1 I) load_data $end
-$var wire 1 J) mgmt_gpio_io $end
-$var wire 1 K) pad_gpio_ana_en $end
-$var wire 1 L) pad_gpio_ana_pol $end
-$var wire 1 M) pad_gpio_ana_sel $end
-$var wire 3 N) pad_gpio_dm [2:0] $end
-$var wire 1 O) pad_gpio_holdover $end
-$var wire 1 P) pad_gpio_ib_mode_sel $end
-$var wire 1 Q) pad_gpio_in $end
-$var wire 1 R) pad_gpio_inenb $end
-$var wire 1 S) pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 T) pad_gpio_slow_sel $end
-$var wire 1 U) pad_gpio_vtrip_sel $end
-$var wire 1 V) serial_data_in $end
-$var wire 1 W) user_gpio_out $end
-$var wire 1 X) user_gpio_outenb $end
-$var wire 1 Y) user_gpio_in $end
-$var wire 1 Z) serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 K) gpio_ana_en $end
-$var reg 1 L) gpio_ana_pol $end
-$var reg 1 M) gpio_ana_sel $end
-$var reg 3 [) gpio_dm [2:0] $end
-$var reg 1 O) gpio_holdover $end
-$var reg 1 P) gpio_ib_mode_sel $end
-$var reg 1 \) gpio_inenb $end
-$var reg 1 ]) gpio_outenb $end
-$var reg 1 T) gpio_slow_sel $end
-$var reg 1 U) gpio_vtrip_sel $end
-$var reg 1 ^) mgmt_ena $end
-$var reg 13 _) shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[29] $end
-$var wire 1 `) int_reset $end
-$var wire 1 a) load_data $end
-$var wire 1 b) mgmt_gpio_io $end
-$var wire 1 c) pad_gpio_ana_en $end
-$var wire 1 d) pad_gpio_ana_pol $end
-$var wire 1 e) pad_gpio_ana_sel $end
-$var wire 3 f) pad_gpio_dm [2:0] $end
-$var wire 1 g) pad_gpio_holdover $end
-$var wire 1 h) pad_gpio_ib_mode_sel $end
-$var wire 1 i) pad_gpio_in $end
-$var wire 1 j) pad_gpio_inenb $end
-$var wire 1 k) pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 l) pad_gpio_slow_sel $end
-$var wire 1 m) pad_gpio_vtrip_sel $end
-$var wire 1 n) serial_data_in $end
-$var wire 1 o) user_gpio_out $end
-$var wire 1 p) user_gpio_outenb $end
-$var wire 1 q) user_gpio_in $end
-$var wire 1 r) serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 c) gpio_ana_en $end
-$var reg 1 d) gpio_ana_pol $end
-$var reg 1 e) gpio_ana_sel $end
-$var reg 3 s) gpio_dm [2:0] $end
-$var reg 1 g) gpio_holdover $end
-$var reg 1 h) gpio_ib_mode_sel $end
-$var reg 1 t) gpio_inenb $end
-$var reg 1 u) gpio_outenb $end
-$var reg 1 l) gpio_slow_sel $end
-$var reg 1 m) gpio_vtrip_sel $end
-$var reg 1 v) mgmt_ena $end
-$var reg 13 w) shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[30] $end
-$var wire 1 x) int_reset $end
-$var wire 1 y) load_data $end
-$var wire 1 z) mgmt_gpio_io $end
-$var wire 1 {) pad_gpio_ana_en $end
-$var wire 1 |) pad_gpio_ana_pol $end
-$var wire 1 }) pad_gpio_ana_sel $end
-$var wire 3 ~) pad_gpio_dm [2:0] $end
-$var wire 1 !* pad_gpio_holdover $end
-$var wire 1 "* pad_gpio_ib_mode_sel $end
-$var wire 1 #* pad_gpio_in $end
-$var wire 1 $* pad_gpio_inenb $end
-$var wire 1 %* pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 &* pad_gpio_slow_sel $end
-$var wire 1 '* pad_gpio_vtrip_sel $end
-$var wire 1 (* serial_data_in $end
-$var wire 1 )* user_gpio_out $end
-$var wire 1 ** user_gpio_outenb $end
-$var wire 1 +* user_gpio_in $end
-$var wire 1 ,* serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 {) gpio_ana_en $end
-$var reg 1 |) gpio_ana_pol $end
-$var reg 1 }) gpio_ana_sel $end
-$var reg 3 -* gpio_dm [2:0] $end
-$var reg 1 !* gpio_holdover $end
-$var reg 1 "* gpio_ib_mode_sel $end
-$var reg 1 .* gpio_inenb $end
-$var reg 1 /* gpio_outenb $end
-$var reg 1 &* gpio_slow_sel $end
-$var reg 1 '* gpio_vtrip_sel $end
-$var reg 1 0* mgmt_ena $end
-$var reg 13 1* shift_register [12:0] $end
-$upscope $end
-$scope module gpio_control_inst[31] $end
-$var wire 1 2* int_reset $end
-$var wire 1 3* load_data $end
-$var wire 1 4* mgmt_gpio_io $end
-$var wire 1 5* pad_gpio_ana_en $end
-$var wire 1 6* pad_gpio_ana_pol $end
-$var wire 1 7* pad_gpio_ana_sel $end
-$var wire 3 8* pad_gpio_dm [2:0] $end
-$var wire 1 9* pad_gpio_holdover $end
-$var wire 1 :* pad_gpio_ib_mode_sel $end
-$var wire 1 ;* pad_gpio_in $end
-$var wire 1 <* pad_gpio_inenb $end
-$var wire 1 =* pad_gpio_out $end
-$var wire 1 Z pad_gpio_outenb $end
-$var wire 1 >* pad_gpio_slow_sel $end
-$var wire 1 ?* pad_gpio_vtrip_sel $end
-$var wire 1 @* serial_data_in $end
-$var wire 1 A* user_gpio_out $end
-$var wire 1 B* user_gpio_outenb $end
-$var wire 1 C* user_gpio_in $end
-$var wire 1 D* serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 p resetn $end
-$var reg 1 5* gpio_ana_en $end
-$var reg 1 6* gpio_ana_pol $end
-$var reg 1 7* gpio_ana_sel $end
-$var reg 3 E* gpio_dm [2:0] $end
-$var reg 1 9* gpio_holdover $end
-$var reg 1 :* gpio_ib_mode_sel $end
-$var reg 1 F* gpio_inenb $end
-$var reg 1 G* gpio_outenb $end
-$var reg 1 >* gpio_slow_sel $end
-$var reg 1 ?* gpio_vtrip_sel $end
-$var reg 1 H* mgmt_ena $end
-$var reg 13 I* shift_register [12:0] $end
-$upscope $end
-$scope module la_buf[0] $end
-$var wire 1 J* A $end
-$var wire 1 K* TE_B $end
-$var wire 1 L* VGND $end
-$var wire 1 M* VNB $end
-$var wire 1 N* VPB $end
-$var wire 1 O* VPWR $end
-$var wire 1 P* Z $end
-$scope module sc_cell $end
-$var wire 1 J* A $end
-$var wire 1 K* TE_B $end
-$var wire 1 P* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[1] $end
-$var wire 1 Q* A $end
-$var wire 1 R* TE_B $end
-$var wire 1 S* VGND $end
-$var wire 1 T* VNB $end
-$var wire 1 U* VPB $end
-$var wire 1 V* VPWR $end
-$var wire 1 W* Z $end
-$scope module sc_cell $end
-$var wire 1 Q* A $end
-$var wire 1 R* TE_B $end
-$var wire 1 W* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[2] $end
-$var wire 1 X* A $end
-$var wire 1 Y* TE_B $end
-$var wire 1 Z* VGND $end
-$var wire 1 [* VNB $end
-$var wire 1 \* VPB $end
-$var wire 1 ]* VPWR $end
-$var wire 1 ^* Z $end
-$scope module sc_cell $end
-$var wire 1 X* A $end
-$var wire 1 Y* TE_B $end
-$var wire 1 ^* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[3] $end
-$var wire 1 _* A $end
-$var wire 1 `* TE_B $end
-$var wire 1 a* VGND $end
-$var wire 1 b* VNB $end
-$var wire 1 c* VPB $end
-$var wire 1 d* VPWR $end
-$var wire 1 e* Z $end
-$scope module sc_cell $end
-$var wire 1 _* A $end
-$var wire 1 `* TE_B $end
-$var wire 1 e* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[4] $end
-$var wire 1 f* A $end
-$var wire 1 g* TE_B $end
-$var wire 1 h* VGND $end
-$var wire 1 i* VNB $end
-$var wire 1 j* VPB $end
-$var wire 1 k* VPWR $end
-$var wire 1 l* Z $end
-$scope module sc_cell $end
-$var wire 1 f* A $end
-$var wire 1 g* TE_B $end
-$var wire 1 l* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[5] $end
-$var wire 1 m* A $end
-$var wire 1 n* TE_B $end
-$var wire 1 o* VGND $end
-$var wire 1 p* VNB $end
-$var wire 1 q* VPB $end
-$var wire 1 r* VPWR $end
-$var wire 1 s* Z $end
-$scope module sc_cell $end
-$var wire 1 m* A $end
-$var wire 1 n* TE_B $end
-$var wire 1 s* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[6] $end
-$var wire 1 t* A $end
-$var wire 1 u* TE_B $end
-$var wire 1 v* VGND $end
-$var wire 1 w* VNB $end
-$var wire 1 x* VPB $end
-$var wire 1 y* VPWR $end
-$var wire 1 z* Z $end
-$scope module sc_cell $end
-$var wire 1 t* A $end
-$var wire 1 u* TE_B $end
-$var wire 1 z* Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[7] $end
-$var wire 1 {* A $end
-$var wire 1 |* TE_B $end
-$var wire 1 }* VGND $end
-$var wire 1 ~* VNB $end
-$var wire 1 !+ VPB $end
-$var wire 1 "+ VPWR $end
-$var wire 1 #+ Z $end
-$scope module sc_cell $end
-$var wire 1 {* A $end
-$var wire 1 |* TE_B $end
-$var wire 1 #+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[8] $end
-$var wire 1 $+ A $end
-$var wire 1 %+ TE_B $end
-$var wire 1 &+ VGND $end
-$var wire 1 '+ VNB $end
-$var wire 1 (+ VPB $end
-$var wire 1 )+ VPWR $end
-$var wire 1 *+ Z $end
-$scope module sc_cell $end
-$var wire 1 $+ A $end
-$var wire 1 %+ TE_B $end
-$var wire 1 *+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[9] $end
-$var wire 1 ++ A $end
-$var wire 1 ,+ TE_B $end
-$var wire 1 -+ VGND $end
-$var wire 1 .+ VNB $end
-$var wire 1 /+ VPB $end
-$var wire 1 0+ VPWR $end
-$var wire 1 1+ Z $end
-$scope module sc_cell $end
-$var wire 1 ++ A $end
-$var wire 1 ,+ TE_B $end
-$var wire 1 1+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[10] $end
-$var wire 1 2+ A $end
-$var wire 1 3+ TE_B $end
-$var wire 1 4+ VGND $end
-$var wire 1 5+ VNB $end
-$var wire 1 6+ VPB $end
-$var wire 1 7+ VPWR $end
-$var wire 1 8+ Z $end
-$scope module sc_cell $end
-$var wire 1 2+ A $end
-$var wire 1 3+ TE_B $end
-$var wire 1 8+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[11] $end
-$var wire 1 9+ A $end
-$var wire 1 :+ TE_B $end
-$var wire 1 ;+ VGND $end
-$var wire 1 <+ VNB $end
-$var wire 1 =+ VPB $end
-$var wire 1 >+ VPWR $end
-$var wire 1 ?+ Z $end
-$scope module sc_cell $end
-$var wire 1 9+ A $end
-$var wire 1 :+ TE_B $end
-$var wire 1 ?+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[12] $end
-$var wire 1 @+ A $end
-$var wire 1 A+ TE_B $end
-$var wire 1 B+ VGND $end
-$var wire 1 C+ VNB $end
-$var wire 1 D+ VPB $end
-$var wire 1 E+ VPWR $end
-$var wire 1 F+ Z $end
-$scope module sc_cell $end
-$var wire 1 @+ A $end
-$var wire 1 A+ TE_B $end
-$var wire 1 F+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[13] $end
-$var wire 1 G+ A $end
-$var wire 1 H+ TE_B $end
-$var wire 1 I+ VGND $end
-$var wire 1 J+ VNB $end
-$var wire 1 K+ VPB $end
-$var wire 1 L+ VPWR $end
-$var wire 1 M+ Z $end
-$scope module sc_cell $end
-$var wire 1 G+ A $end
-$var wire 1 H+ TE_B $end
-$var wire 1 M+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[14] $end
-$var wire 1 N+ A $end
-$var wire 1 O+ TE_B $end
-$var wire 1 P+ VGND $end
-$var wire 1 Q+ VNB $end
-$var wire 1 R+ VPB $end
-$var wire 1 S+ VPWR $end
-$var wire 1 T+ Z $end
-$scope module sc_cell $end
-$var wire 1 N+ A $end
-$var wire 1 O+ TE_B $end
-$var wire 1 T+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[15] $end
-$var wire 1 U+ A $end
-$var wire 1 V+ TE_B $end
-$var wire 1 W+ VGND $end
-$var wire 1 X+ VNB $end
-$var wire 1 Y+ VPB $end
-$var wire 1 Z+ VPWR $end
-$var wire 1 [+ Z $end
-$scope module sc_cell $end
-$var wire 1 U+ A $end
-$var wire 1 V+ TE_B $end
-$var wire 1 [+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[16] $end
-$var wire 1 \+ A $end
-$var wire 1 ]+ TE_B $end
-$var wire 1 ^+ VGND $end
-$var wire 1 _+ VNB $end
-$var wire 1 `+ VPB $end
-$var wire 1 a+ VPWR $end
-$var wire 1 b+ Z $end
-$scope module sc_cell $end
-$var wire 1 \+ A $end
-$var wire 1 ]+ TE_B $end
-$var wire 1 b+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[17] $end
-$var wire 1 c+ A $end
-$var wire 1 d+ TE_B $end
-$var wire 1 e+ VGND $end
-$var wire 1 f+ VNB $end
-$var wire 1 g+ VPB $end
-$var wire 1 h+ VPWR $end
-$var wire 1 i+ Z $end
-$scope module sc_cell $end
-$var wire 1 c+ A $end
-$var wire 1 d+ TE_B $end
-$var wire 1 i+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[18] $end
-$var wire 1 j+ A $end
-$var wire 1 k+ TE_B $end
-$var wire 1 l+ VGND $end
-$var wire 1 m+ VNB $end
-$var wire 1 n+ VPB $end
-$var wire 1 o+ VPWR $end
-$var wire 1 p+ Z $end
-$scope module sc_cell $end
-$var wire 1 j+ A $end
-$var wire 1 k+ TE_B $end
-$var wire 1 p+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[19] $end
-$var wire 1 q+ A $end
-$var wire 1 r+ TE_B $end
-$var wire 1 s+ VGND $end
-$var wire 1 t+ VNB $end
-$var wire 1 u+ VPB $end
-$var wire 1 v+ VPWR $end
-$var wire 1 w+ Z $end
-$scope module sc_cell $end
-$var wire 1 q+ A $end
-$var wire 1 r+ TE_B $end
-$var wire 1 w+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[20] $end
-$var wire 1 x+ A $end
-$var wire 1 y+ TE_B $end
-$var wire 1 z+ VGND $end
-$var wire 1 {+ VNB $end
-$var wire 1 |+ VPB $end
-$var wire 1 }+ VPWR $end
-$var wire 1 ~+ Z $end
-$scope module sc_cell $end
-$var wire 1 x+ A $end
-$var wire 1 y+ TE_B $end
-$var wire 1 ~+ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[21] $end
-$var wire 1 !, A $end
-$var wire 1 ", TE_B $end
-$var wire 1 #, VGND $end
-$var wire 1 $, VNB $end
-$var wire 1 %, VPB $end
-$var wire 1 &, VPWR $end
-$var wire 1 ', Z $end
-$scope module sc_cell $end
-$var wire 1 !, A $end
-$var wire 1 ", TE_B $end
-$var wire 1 ', Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[22] $end
-$var wire 1 (, A $end
-$var wire 1 ), TE_B $end
-$var wire 1 *, VGND $end
-$var wire 1 +, VNB $end
-$var wire 1 ,, VPB $end
-$var wire 1 -, VPWR $end
-$var wire 1 ., Z $end
-$scope module sc_cell $end
-$var wire 1 (, A $end
-$var wire 1 ), TE_B $end
-$var wire 1 ., Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[23] $end
-$var wire 1 /, A $end
-$var wire 1 0, TE_B $end
-$var wire 1 1, VGND $end
-$var wire 1 2, VNB $end
-$var wire 1 3, VPB $end
-$var wire 1 4, VPWR $end
-$var wire 1 5, Z $end
-$scope module sc_cell $end
-$var wire 1 /, A $end
-$var wire 1 0, TE_B $end
-$var wire 1 5, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[24] $end
-$var wire 1 6, A $end
-$var wire 1 7, TE_B $end
-$var wire 1 8, VGND $end
-$var wire 1 9, VNB $end
-$var wire 1 :, VPB $end
-$var wire 1 ;, VPWR $end
-$var wire 1 <, Z $end
-$scope module sc_cell $end
-$var wire 1 6, A $end
-$var wire 1 7, TE_B $end
-$var wire 1 <, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[25] $end
-$var wire 1 =, A $end
-$var wire 1 >, TE_B $end
-$var wire 1 ?, VGND $end
-$var wire 1 @, VNB $end
-$var wire 1 A, VPB $end
-$var wire 1 B, VPWR $end
-$var wire 1 C, Z $end
-$scope module sc_cell $end
-$var wire 1 =, A $end
-$var wire 1 >, TE_B $end
-$var wire 1 C, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[26] $end
-$var wire 1 D, A $end
-$var wire 1 E, TE_B $end
-$var wire 1 F, VGND $end
-$var wire 1 G, VNB $end
-$var wire 1 H, VPB $end
-$var wire 1 I, VPWR $end
-$var wire 1 J, Z $end
-$scope module sc_cell $end
-$var wire 1 D, A $end
-$var wire 1 E, TE_B $end
-$var wire 1 J, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[27] $end
-$var wire 1 K, A $end
-$var wire 1 L, TE_B $end
-$var wire 1 M, VGND $end
-$var wire 1 N, VNB $end
-$var wire 1 O, VPB $end
-$var wire 1 P, VPWR $end
-$var wire 1 Q, Z $end
-$scope module sc_cell $end
-$var wire 1 K, A $end
-$var wire 1 L, TE_B $end
-$var wire 1 Q, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[28] $end
-$var wire 1 R, A $end
-$var wire 1 S, TE_B $end
-$var wire 1 T, VGND $end
-$var wire 1 U, VNB $end
-$var wire 1 V, VPB $end
-$var wire 1 W, VPWR $end
-$var wire 1 X, Z $end
-$scope module sc_cell $end
-$var wire 1 R, A $end
-$var wire 1 S, TE_B $end
-$var wire 1 X, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[29] $end
-$var wire 1 Y, A $end
-$var wire 1 Z, TE_B $end
-$var wire 1 [, VGND $end
-$var wire 1 \, VNB $end
-$var wire 1 ], VPB $end
-$var wire 1 ^, VPWR $end
-$var wire 1 _, Z $end
-$scope module sc_cell $end
-$var wire 1 Y, A $end
-$var wire 1 Z, TE_B $end
-$var wire 1 _, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[30] $end
-$var wire 1 `, A $end
-$var wire 1 a, TE_B $end
-$var wire 1 b, VGND $end
-$var wire 1 c, VNB $end
-$var wire 1 d, VPB $end
-$var wire 1 e, VPWR $end
-$var wire 1 f, Z $end
-$scope module sc_cell $end
-$var wire 1 `, A $end
-$var wire 1 a, TE_B $end
-$var wire 1 f, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[31] $end
-$var wire 1 g, A $end
-$var wire 1 h, TE_B $end
-$var wire 1 i, VGND $end
-$var wire 1 j, VNB $end
-$var wire 1 k, VPB $end
-$var wire 1 l, VPWR $end
-$var wire 1 m, Z $end
-$scope module sc_cell $end
-$var wire 1 g, A $end
-$var wire 1 h, TE_B $end
-$var wire 1 m, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[32] $end
-$var wire 1 n, A $end
-$var wire 1 o, TE_B $end
-$var wire 1 p, VGND $end
-$var wire 1 q, VNB $end
-$var wire 1 r, VPB $end
-$var wire 1 s, VPWR $end
-$var wire 1 t, Z $end
-$scope module sc_cell $end
-$var wire 1 n, A $end
-$var wire 1 o, TE_B $end
-$var wire 1 t, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[33] $end
-$var wire 1 u, A $end
-$var wire 1 v, TE_B $end
-$var wire 1 w, VGND $end
-$var wire 1 x, VNB $end
-$var wire 1 y, VPB $end
-$var wire 1 z, VPWR $end
-$var wire 1 {, Z $end
-$scope module sc_cell $end
-$var wire 1 u, A $end
-$var wire 1 v, TE_B $end
-$var wire 1 {, Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[34] $end
-$var wire 1 |, A $end
-$var wire 1 }, TE_B $end
-$var wire 1 ~, VGND $end
-$var wire 1 !- VNB $end
-$var wire 1 "- VPB $end
-$var wire 1 #- VPWR $end
-$var wire 1 $- Z $end
-$scope module sc_cell $end
-$var wire 1 |, A $end
-$var wire 1 }, TE_B $end
-$var wire 1 $- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[35] $end
-$var wire 1 %- A $end
-$var wire 1 &- TE_B $end
-$var wire 1 '- VGND $end
-$var wire 1 (- VNB $end
-$var wire 1 )- VPB $end
-$var wire 1 *- VPWR $end
-$var wire 1 +- Z $end
-$scope module sc_cell $end
-$var wire 1 %- A $end
-$var wire 1 &- TE_B $end
-$var wire 1 +- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[36] $end
-$var wire 1 ,- A $end
-$var wire 1 -- TE_B $end
-$var wire 1 .- VGND $end
-$var wire 1 /- VNB $end
-$var wire 1 0- VPB $end
-$var wire 1 1- VPWR $end
-$var wire 1 2- Z $end
-$scope module sc_cell $end
-$var wire 1 ,- A $end
-$var wire 1 -- TE_B $end
-$var wire 1 2- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[37] $end
-$var wire 1 3- A $end
-$var wire 1 4- TE_B $end
-$var wire 1 5- VGND $end
-$var wire 1 6- VNB $end
-$var wire 1 7- VPB $end
-$var wire 1 8- VPWR $end
-$var wire 1 9- Z $end
-$scope module sc_cell $end
-$var wire 1 3- A $end
-$var wire 1 4- TE_B $end
-$var wire 1 9- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[38] $end
-$var wire 1 :- A $end
-$var wire 1 ;- TE_B $end
-$var wire 1 <- VGND $end
-$var wire 1 =- VNB $end
-$var wire 1 >- VPB $end
-$var wire 1 ?- VPWR $end
-$var wire 1 @- Z $end
-$scope module sc_cell $end
-$var wire 1 :- A $end
-$var wire 1 ;- TE_B $end
-$var wire 1 @- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[39] $end
-$var wire 1 A- A $end
-$var wire 1 B- TE_B $end
-$var wire 1 C- VGND $end
-$var wire 1 D- VNB $end
-$var wire 1 E- VPB $end
-$var wire 1 F- VPWR $end
-$var wire 1 G- Z $end
-$scope module sc_cell $end
-$var wire 1 A- A $end
-$var wire 1 B- TE_B $end
-$var wire 1 G- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[40] $end
-$var wire 1 H- A $end
-$var wire 1 I- TE_B $end
-$var wire 1 J- VGND $end
-$var wire 1 K- VNB $end
-$var wire 1 L- VPB $end
-$var wire 1 M- VPWR $end
-$var wire 1 N- Z $end
-$scope module sc_cell $end
-$var wire 1 H- A $end
-$var wire 1 I- TE_B $end
-$var wire 1 N- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[41] $end
-$var wire 1 O- A $end
-$var wire 1 P- TE_B $end
-$var wire 1 Q- VGND $end
-$var wire 1 R- VNB $end
-$var wire 1 S- VPB $end
-$var wire 1 T- VPWR $end
-$var wire 1 U- Z $end
-$scope module sc_cell $end
-$var wire 1 O- A $end
-$var wire 1 P- TE_B $end
-$var wire 1 U- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[42] $end
-$var wire 1 V- A $end
-$var wire 1 W- TE_B $end
-$var wire 1 X- VGND $end
-$var wire 1 Y- VNB $end
-$var wire 1 Z- VPB $end
-$var wire 1 [- VPWR $end
-$var wire 1 \- Z $end
-$scope module sc_cell $end
-$var wire 1 V- A $end
-$var wire 1 W- TE_B $end
-$var wire 1 \- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[43] $end
-$var wire 1 ]- A $end
-$var wire 1 ^- TE_B $end
-$var wire 1 _- VGND $end
-$var wire 1 `- VNB $end
-$var wire 1 a- VPB $end
-$var wire 1 b- VPWR $end
-$var wire 1 c- Z $end
-$scope module sc_cell $end
-$var wire 1 ]- A $end
-$var wire 1 ^- TE_B $end
-$var wire 1 c- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[44] $end
-$var wire 1 d- A $end
-$var wire 1 e- TE_B $end
-$var wire 1 f- VGND $end
-$var wire 1 g- VNB $end
-$var wire 1 h- VPB $end
-$var wire 1 i- VPWR $end
-$var wire 1 j- Z $end
-$scope module sc_cell $end
-$var wire 1 d- A $end
-$var wire 1 e- TE_B $end
-$var wire 1 j- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[45] $end
-$var wire 1 k- A $end
-$var wire 1 l- TE_B $end
-$var wire 1 m- VGND $end
-$var wire 1 n- VNB $end
-$var wire 1 o- VPB $end
-$var wire 1 p- VPWR $end
-$var wire 1 q- Z $end
-$scope module sc_cell $end
-$var wire 1 k- A $end
-$var wire 1 l- TE_B $end
-$var wire 1 q- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[46] $end
-$var wire 1 r- A $end
-$var wire 1 s- TE_B $end
-$var wire 1 t- VGND $end
-$var wire 1 u- VNB $end
-$var wire 1 v- VPB $end
-$var wire 1 w- VPWR $end
-$var wire 1 x- Z $end
-$scope module sc_cell $end
-$var wire 1 r- A $end
-$var wire 1 s- TE_B $end
-$var wire 1 x- Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[47] $end
-$var wire 1 y- A $end
-$var wire 1 z- TE_B $end
-$var wire 1 {- VGND $end
-$var wire 1 |- VNB $end
-$var wire 1 }- VPB $end
-$var wire 1 ~- VPWR $end
-$var wire 1 !. Z $end
-$scope module sc_cell $end
-$var wire 1 y- A $end
-$var wire 1 z- TE_B $end
-$var wire 1 !. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[48] $end
-$var wire 1 ". A $end
-$var wire 1 #. TE_B $end
-$var wire 1 $. VGND $end
-$var wire 1 %. VNB $end
-$var wire 1 &. VPB $end
-$var wire 1 '. VPWR $end
-$var wire 1 (. Z $end
-$scope module sc_cell $end
-$var wire 1 ". A $end
-$var wire 1 #. TE_B $end
-$var wire 1 (. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[49] $end
-$var wire 1 ). A $end
-$var wire 1 *. TE_B $end
-$var wire 1 +. VGND $end
-$var wire 1 ,. VNB $end
-$var wire 1 -. VPB $end
-$var wire 1 .. VPWR $end
-$var wire 1 /. Z $end
-$scope module sc_cell $end
-$var wire 1 ). A $end
-$var wire 1 *. TE_B $end
-$var wire 1 /. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[50] $end
-$var wire 1 0. A $end
-$var wire 1 1. TE_B $end
-$var wire 1 2. VGND $end
-$var wire 1 3. VNB $end
-$var wire 1 4. VPB $end
-$var wire 1 5. VPWR $end
-$var wire 1 6. Z $end
-$scope module sc_cell $end
-$var wire 1 0. A $end
-$var wire 1 1. TE_B $end
-$var wire 1 6. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[51] $end
-$var wire 1 7. A $end
-$var wire 1 8. TE_B $end
-$var wire 1 9. VGND $end
-$var wire 1 :. VNB $end
-$var wire 1 ;. VPB $end
-$var wire 1 <. VPWR $end
-$var wire 1 =. Z $end
-$scope module sc_cell $end
-$var wire 1 7. A $end
-$var wire 1 8. TE_B $end
-$var wire 1 =. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[52] $end
-$var wire 1 >. A $end
-$var wire 1 ?. TE_B $end
-$var wire 1 @. VGND $end
-$var wire 1 A. VNB $end
-$var wire 1 B. VPB $end
-$var wire 1 C. VPWR $end
-$var wire 1 D. Z $end
-$scope module sc_cell $end
-$var wire 1 >. A $end
-$var wire 1 ?. TE_B $end
-$var wire 1 D. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[53] $end
-$var wire 1 E. A $end
-$var wire 1 F. TE_B $end
-$var wire 1 G. VGND $end
-$var wire 1 H. VNB $end
-$var wire 1 I. VPB $end
-$var wire 1 J. VPWR $end
-$var wire 1 K. Z $end
-$scope module sc_cell $end
-$var wire 1 E. A $end
-$var wire 1 F. TE_B $end
-$var wire 1 K. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[54] $end
-$var wire 1 L. A $end
-$var wire 1 M. TE_B $end
-$var wire 1 N. VGND $end
-$var wire 1 O. VNB $end
-$var wire 1 P. VPB $end
-$var wire 1 Q. VPWR $end
-$var wire 1 R. Z $end
-$scope module sc_cell $end
-$var wire 1 L. A $end
-$var wire 1 M. TE_B $end
-$var wire 1 R. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[55] $end
-$var wire 1 S. A $end
-$var wire 1 T. TE_B $end
-$var wire 1 U. VGND $end
-$var wire 1 V. VNB $end
-$var wire 1 W. VPB $end
-$var wire 1 X. VPWR $end
-$var wire 1 Y. Z $end
-$scope module sc_cell $end
-$var wire 1 S. A $end
-$var wire 1 T. TE_B $end
-$var wire 1 Y. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[56] $end
-$var wire 1 Z. A $end
-$var wire 1 [. TE_B $end
-$var wire 1 \. VGND $end
-$var wire 1 ]. VNB $end
-$var wire 1 ^. VPB $end
-$var wire 1 _. VPWR $end
-$var wire 1 `. Z $end
-$scope module sc_cell $end
-$var wire 1 Z. A $end
-$var wire 1 [. TE_B $end
-$var wire 1 `. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[57] $end
-$var wire 1 a. A $end
-$var wire 1 b. TE_B $end
-$var wire 1 c. VGND $end
-$var wire 1 d. VNB $end
-$var wire 1 e. VPB $end
-$var wire 1 f. VPWR $end
-$var wire 1 g. Z $end
-$scope module sc_cell $end
-$var wire 1 a. A $end
-$var wire 1 b. TE_B $end
-$var wire 1 g. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[58] $end
-$var wire 1 h. A $end
-$var wire 1 i. TE_B $end
-$var wire 1 j. VGND $end
-$var wire 1 k. VNB $end
-$var wire 1 l. VPB $end
-$var wire 1 m. VPWR $end
-$var wire 1 n. Z $end
-$scope module sc_cell $end
-$var wire 1 h. A $end
-$var wire 1 i. TE_B $end
-$var wire 1 n. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[59] $end
-$var wire 1 o. A $end
-$var wire 1 p. TE_B $end
-$var wire 1 q. VGND $end
-$var wire 1 r. VNB $end
-$var wire 1 s. VPB $end
-$var wire 1 t. VPWR $end
-$var wire 1 u. Z $end
-$scope module sc_cell $end
-$var wire 1 o. A $end
-$var wire 1 p. TE_B $end
-$var wire 1 u. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[60] $end
-$var wire 1 v. A $end
-$var wire 1 w. TE_B $end
-$var wire 1 x. VGND $end
-$var wire 1 y. VNB $end
-$var wire 1 z. VPB $end
-$var wire 1 {. VPWR $end
-$var wire 1 |. Z $end
-$scope module sc_cell $end
-$var wire 1 v. A $end
-$var wire 1 w. TE_B $end
-$var wire 1 |. Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[61] $end
-$var wire 1 }. A $end
-$var wire 1 ~. TE_B $end
-$var wire 1 !/ VGND $end
-$var wire 1 "/ VNB $end
-$var wire 1 #/ VPB $end
-$var wire 1 $/ VPWR $end
-$var wire 1 %/ Z $end
-$scope module sc_cell $end
-$var wire 1 }. A $end
-$var wire 1 ~. TE_B $end
-$var wire 1 %/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[62] $end
-$var wire 1 &/ A $end
-$var wire 1 '/ TE_B $end
-$var wire 1 (/ VGND $end
-$var wire 1 )/ VNB $end
-$var wire 1 */ VPB $end
-$var wire 1 +/ VPWR $end
-$var wire 1 ,/ Z $end
-$scope module sc_cell $end
-$var wire 1 &/ A $end
-$var wire 1 '/ TE_B $end
-$var wire 1 ,/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[63] $end
-$var wire 1 -/ A $end
-$var wire 1 ./ TE_B $end
-$var wire 1 // VGND $end
-$var wire 1 0/ VNB $end
-$var wire 1 1/ VPB $end
-$var wire 1 2/ VPWR $end
-$var wire 1 3/ Z $end
-$scope module sc_cell $end
-$var wire 1 -/ A $end
-$var wire 1 ./ TE_B $end
-$var wire 1 3/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[64] $end
-$var wire 1 4/ A $end
-$var wire 1 5/ TE_B $end
-$var wire 1 6/ VGND $end
-$var wire 1 7/ VNB $end
-$var wire 1 8/ VPB $end
-$var wire 1 9/ VPWR $end
-$var wire 1 :/ Z $end
-$scope module sc_cell $end
-$var wire 1 4/ A $end
-$var wire 1 5/ TE_B $end
-$var wire 1 :/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[65] $end
-$var wire 1 ;/ A $end
-$var wire 1 </ TE_B $end
-$var wire 1 =/ VGND $end
-$var wire 1 >/ VNB $end
-$var wire 1 ?/ VPB $end
-$var wire 1 @/ VPWR $end
-$var wire 1 A/ Z $end
-$scope module sc_cell $end
-$var wire 1 ;/ A $end
-$var wire 1 </ TE_B $end
-$var wire 1 A/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[66] $end
-$var wire 1 B/ A $end
-$var wire 1 C/ TE_B $end
-$var wire 1 D/ VGND $end
-$var wire 1 E/ VNB $end
-$var wire 1 F/ VPB $end
-$var wire 1 G/ VPWR $end
-$var wire 1 H/ Z $end
-$scope module sc_cell $end
-$var wire 1 B/ A $end
-$var wire 1 C/ TE_B $end
-$var wire 1 H/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[67] $end
-$var wire 1 I/ A $end
-$var wire 1 J/ TE_B $end
-$var wire 1 K/ VGND $end
-$var wire 1 L/ VNB $end
-$var wire 1 M/ VPB $end
-$var wire 1 N/ VPWR $end
-$var wire 1 O/ Z $end
-$scope module sc_cell $end
-$var wire 1 I/ A $end
-$var wire 1 J/ TE_B $end
-$var wire 1 O/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[68] $end
-$var wire 1 P/ A $end
-$var wire 1 Q/ TE_B $end
-$var wire 1 R/ VGND $end
-$var wire 1 S/ VNB $end
-$var wire 1 T/ VPB $end
-$var wire 1 U/ VPWR $end
-$var wire 1 V/ Z $end
-$scope module sc_cell $end
-$var wire 1 P/ A $end
-$var wire 1 Q/ TE_B $end
-$var wire 1 V/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[69] $end
-$var wire 1 W/ A $end
-$var wire 1 X/ TE_B $end
-$var wire 1 Y/ VGND $end
-$var wire 1 Z/ VNB $end
-$var wire 1 [/ VPB $end
-$var wire 1 \/ VPWR $end
-$var wire 1 ]/ Z $end
-$scope module sc_cell $end
-$var wire 1 W/ A $end
-$var wire 1 X/ TE_B $end
-$var wire 1 ]/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[70] $end
-$var wire 1 ^/ A $end
-$var wire 1 _/ TE_B $end
-$var wire 1 `/ VGND $end
-$var wire 1 a/ VNB $end
-$var wire 1 b/ VPB $end
-$var wire 1 c/ VPWR $end
-$var wire 1 d/ Z $end
-$scope module sc_cell $end
-$var wire 1 ^/ A $end
-$var wire 1 _/ TE_B $end
-$var wire 1 d/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[71] $end
-$var wire 1 e/ A $end
-$var wire 1 f/ TE_B $end
-$var wire 1 g/ VGND $end
-$var wire 1 h/ VNB $end
-$var wire 1 i/ VPB $end
-$var wire 1 j/ VPWR $end
-$var wire 1 k/ Z $end
-$scope module sc_cell $end
-$var wire 1 e/ A $end
-$var wire 1 f/ TE_B $end
-$var wire 1 k/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[72] $end
-$var wire 1 l/ A $end
-$var wire 1 m/ TE_B $end
-$var wire 1 n/ VGND $end
-$var wire 1 o/ VNB $end
-$var wire 1 p/ VPB $end
-$var wire 1 q/ VPWR $end
-$var wire 1 r/ Z $end
-$scope module sc_cell $end
-$var wire 1 l/ A $end
-$var wire 1 m/ TE_B $end
-$var wire 1 r/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[73] $end
-$var wire 1 s/ A $end
-$var wire 1 t/ TE_B $end
-$var wire 1 u/ VGND $end
-$var wire 1 v/ VNB $end
-$var wire 1 w/ VPB $end
-$var wire 1 x/ VPWR $end
-$var wire 1 y/ Z $end
-$scope module sc_cell $end
-$var wire 1 s/ A $end
-$var wire 1 t/ TE_B $end
-$var wire 1 y/ Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[74] $end
-$var wire 1 z/ A $end
-$var wire 1 {/ TE_B $end
-$var wire 1 |/ VGND $end
-$var wire 1 }/ VNB $end
-$var wire 1 ~/ VPB $end
-$var wire 1 !0 VPWR $end
-$var wire 1 "0 Z $end
-$scope module sc_cell $end
-$var wire 1 z/ A $end
-$var wire 1 {/ TE_B $end
-$var wire 1 "0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[75] $end
-$var wire 1 #0 A $end
-$var wire 1 $0 TE_B $end
-$var wire 1 %0 VGND $end
-$var wire 1 &0 VNB $end
-$var wire 1 '0 VPB $end
-$var wire 1 (0 VPWR $end
-$var wire 1 )0 Z $end
-$scope module sc_cell $end
-$var wire 1 #0 A $end
-$var wire 1 $0 TE_B $end
-$var wire 1 )0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[76] $end
-$var wire 1 *0 A $end
-$var wire 1 +0 TE_B $end
-$var wire 1 ,0 VGND $end
-$var wire 1 -0 VNB $end
-$var wire 1 .0 VPB $end
-$var wire 1 /0 VPWR $end
-$var wire 1 00 Z $end
-$scope module sc_cell $end
-$var wire 1 *0 A $end
-$var wire 1 +0 TE_B $end
-$var wire 1 00 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[77] $end
-$var wire 1 10 A $end
-$var wire 1 20 TE_B $end
-$var wire 1 30 VGND $end
-$var wire 1 40 VNB $end
-$var wire 1 50 VPB $end
-$var wire 1 60 VPWR $end
-$var wire 1 70 Z $end
-$scope module sc_cell $end
-$var wire 1 10 A $end
-$var wire 1 20 TE_B $end
-$var wire 1 70 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[78] $end
-$var wire 1 80 A $end
-$var wire 1 90 TE_B $end
-$var wire 1 :0 VGND $end
-$var wire 1 ;0 VNB $end
-$var wire 1 <0 VPB $end
-$var wire 1 =0 VPWR $end
-$var wire 1 >0 Z $end
-$scope module sc_cell $end
-$var wire 1 80 A $end
-$var wire 1 90 TE_B $end
-$var wire 1 >0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[79] $end
-$var wire 1 ?0 A $end
-$var wire 1 @0 TE_B $end
-$var wire 1 A0 VGND $end
-$var wire 1 B0 VNB $end
-$var wire 1 C0 VPB $end
-$var wire 1 D0 VPWR $end
-$var wire 1 E0 Z $end
-$scope module sc_cell $end
-$var wire 1 ?0 A $end
-$var wire 1 @0 TE_B $end
-$var wire 1 E0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[80] $end
-$var wire 1 F0 A $end
-$var wire 1 G0 TE_B $end
-$var wire 1 H0 VGND $end
-$var wire 1 I0 VNB $end
-$var wire 1 J0 VPB $end
-$var wire 1 K0 VPWR $end
-$var wire 1 L0 Z $end
-$scope module sc_cell $end
-$var wire 1 F0 A $end
-$var wire 1 G0 TE_B $end
-$var wire 1 L0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[81] $end
-$var wire 1 M0 A $end
-$var wire 1 N0 TE_B $end
-$var wire 1 O0 VGND $end
-$var wire 1 P0 VNB $end
-$var wire 1 Q0 VPB $end
-$var wire 1 R0 VPWR $end
-$var wire 1 S0 Z $end
-$scope module sc_cell $end
-$var wire 1 M0 A $end
-$var wire 1 N0 TE_B $end
-$var wire 1 S0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[82] $end
-$var wire 1 T0 A $end
-$var wire 1 U0 TE_B $end
-$var wire 1 V0 VGND $end
-$var wire 1 W0 VNB $end
-$var wire 1 X0 VPB $end
-$var wire 1 Y0 VPWR $end
-$var wire 1 Z0 Z $end
-$scope module sc_cell $end
-$var wire 1 T0 A $end
-$var wire 1 U0 TE_B $end
-$var wire 1 Z0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[83] $end
-$var wire 1 [0 A $end
-$var wire 1 \0 TE_B $end
-$var wire 1 ]0 VGND $end
-$var wire 1 ^0 VNB $end
-$var wire 1 _0 VPB $end
-$var wire 1 `0 VPWR $end
-$var wire 1 a0 Z $end
-$scope module sc_cell $end
-$var wire 1 [0 A $end
-$var wire 1 \0 TE_B $end
-$var wire 1 a0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[84] $end
-$var wire 1 b0 A $end
-$var wire 1 c0 TE_B $end
-$var wire 1 d0 VGND $end
-$var wire 1 e0 VNB $end
-$var wire 1 f0 VPB $end
-$var wire 1 g0 VPWR $end
-$var wire 1 h0 Z $end
-$scope module sc_cell $end
-$var wire 1 b0 A $end
-$var wire 1 c0 TE_B $end
-$var wire 1 h0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[85] $end
-$var wire 1 i0 A $end
-$var wire 1 j0 TE_B $end
-$var wire 1 k0 VGND $end
-$var wire 1 l0 VNB $end
-$var wire 1 m0 VPB $end
-$var wire 1 n0 VPWR $end
-$var wire 1 o0 Z $end
-$scope module sc_cell $end
-$var wire 1 i0 A $end
-$var wire 1 j0 TE_B $end
-$var wire 1 o0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[86] $end
-$var wire 1 p0 A $end
-$var wire 1 q0 TE_B $end
-$var wire 1 r0 VGND $end
-$var wire 1 s0 VNB $end
-$var wire 1 t0 VPB $end
-$var wire 1 u0 VPWR $end
-$var wire 1 v0 Z $end
-$scope module sc_cell $end
-$var wire 1 p0 A $end
-$var wire 1 q0 TE_B $end
-$var wire 1 v0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[87] $end
-$var wire 1 w0 A $end
-$var wire 1 x0 TE_B $end
-$var wire 1 y0 VGND $end
-$var wire 1 z0 VNB $end
-$var wire 1 {0 VPB $end
-$var wire 1 |0 VPWR $end
-$var wire 1 }0 Z $end
-$scope module sc_cell $end
-$var wire 1 w0 A $end
-$var wire 1 x0 TE_B $end
-$var wire 1 }0 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[88] $end
-$var wire 1 ~0 A $end
-$var wire 1 !1 TE_B $end
-$var wire 1 "1 VGND $end
-$var wire 1 #1 VNB $end
-$var wire 1 $1 VPB $end
-$var wire 1 %1 VPWR $end
-$var wire 1 &1 Z $end
-$scope module sc_cell $end
-$var wire 1 ~0 A $end
-$var wire 1 !1 TE_B $end
-$var wire 1 &1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[89] $end
-$var wire 1 '1 A $end
-$var wire 1 (1 TE_B $end
-$var wire 1 )1 VGND $end
-$var wire 1 *1 VNB $end
-$var wire 1 +1 VPB $end
-$var wire 1 ,1 VPWR $end
-$var wire 1 -1 Z $end
-$scope module sc_cell $end
-$var wire 1 '1 A $end
-$var wire 1 (1 TE_B $end
-$var wire 1 -1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[90] $end
-$var wire 1 .1 A $end
-$var wire 1 /1 TE_B $end
-$var wire 1 01 VGND $end
-$var wire 1 11 VNB $end
-$var wire 1 21 VPB $end
-$var wire 1 31 VPWR $end
-$var wire 1 41 Z $end
-$scope module sc_cell $end
-$var wire 1 .1 A $end
-$var wire 1 /1 TE_B $end
-$var wire 1 41 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[91] $end
-$var wire 1 51 A $end
-$var wire 1 61 TE_B $end
-$var wire 1 71 VGND $end
-$var wire 1 81 VNB $end
-$var wire 1 91 VPB $end
-$var wire 1 :1 VPWR $end
-$var wire 1 ;1 Z $end
-$scope module sc_cell $end
-$var wire 1 51 A $end
-$var wire 1 61 TE_B $end
-$var wire 1 ;1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[92] $end
-$var wire 1 <1 A $end
-$var wire 1 =1 TE_B $end
-$var wire 1 >1 VGND $end
-$var wire 1 ?1 VNB $end
-$var wire 1 @1 VPB $end
-$var wire 1 A1 VPWR $end
-$var wire 1 B1 Z $end
-$scope module sc_cell $end
-$var wire 1 <1 A $end
-$var wire 1 =1 TE_B $end
-$var wire 1 B1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[93] $end
-$var wire 1 C1 A $end
-$var wire 1 D1 TE_B $end
-$var wire 1 E1 VGND $end
-$var wire 1 F1 VNB $end
-$var wire 1 G1 VPB $end
-$var wire 1 H1 VPWR $end
-$var wire 1 I1 Z $end
-$scope module sc_cell $end
-$var wire 1 C1 A $end
-$var wire 1 D1 TE_B $end
-$var wire 1 I1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[94] $end
-$var wire 1 J1 A $end
-$var wire 1 K1 TE_B $end
-$var wire 1 L1 VGND $end
-$var wire 1 M1 VNB $end
-$var wire 1 N1 VPB $end
-$var wire 1 O1 VPWR $end
-$var wire 1 P1 Z $end
-$scope module sc_cell $end
-$var wire 1 J1 A $end
-$var wire 1 K1 TE_B $end
-$var wire 1 P1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[95] $end
-$var wire 1 Q1 A $end
-$var wire 1 R1 TE_B $end
-$var wire 1 S1 VGND $end
-$var wire 1 T1 VNB $end
-$var wire 1 U1 VPB $end
-$var wire 1 V1 VPWR $end
-$var wire 1 W1 Z $end
-$scope module sc_cell $end
-$var wire 1 Q1 A $end
-$var wire 1 R1 TE_B $end
-$var wire 1 W1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[96] $end
-$var wire 1 X1 A $end
-$var wire 1 Y1 TE_B $end
-$var wire 1 Z1 VGND $end
-$var wire 1 [1 VNB $end
-$var wire 1 \1 VPB $end
-$var wire 1 ]1 VPWR $end
-$var wire 1 ^1 Z $end
-$scope module sc_cell $end
-$var wire 1 X1 A $end
-$var wire 1 Y1 TE_B $end
-$var wire 1 ^1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[97] $end
-$var wire 1 _1 A $end
-$var wire 1 `1 TE_B $end
-$var wire 1 a1 VGND $end
-$var wire 1 b1 VNB $end
-$var wire 1 c1 VPB $end
-$var wire 1 d1 VPWR $end
-$var wire 1 e1 Z $end
-$scope module sc_cell $end
-$var wire 1 _1 A $end
-$var wire 1 `1 TE_B $end
-$var wire 1 e1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[98] $end
-$var wire 1 f1 A $end
-$var wire 1 g1 TE_B $end
-$var wire 1 h1 VGND $end
-$var wire 1 i1 VNB $end
-$var wire 1 j1 VPB $end
-$var wire 1 k1 VPWR $end
-$var wire 1 l1 Z $end
-$scope module sc_cell $end
-$var wire 1 f1 A $end
-$var wire 1 g1 TE_B $end
-$var wire 1 l1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[99] $end
-$var wire 1 m1 A $end
-$var wire 1 n1 TE_B $end
-$var wire 1 o1 VGND $end
-$var wire 1 p1 VNB $end
-$var wire 1 q1 VPB $end
-$var wire 1 r1 VPWR $end
-$var wire 1 s1 Z $end
-$scope module sc_cell $end
-$var wire 1 m1 A $end
-$var wire 1 n1 TE_B $end
-$var wire 1 s1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[100] $end
-$var wire 1 t1 A $end
-$var wire 1 u1 TE_B $end
-$var wire 1 v1 VGND $end
-$var wire 1 w1 VNB $end
-$var wire 1 x1 VPB $end
-$var wire 1 y1 VPWR $end
-$var wire 1 z1 Z $end
-$scope module sc_cell $end
-$var wire 1 t1 A $end
-$var wire 1 u1 TE_B $end
-$var wire 1 z1 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[101] $end
-$var wire 1 {1 A $end
-$var wire 1 |1 TE_B $end
-$var wire 1 }1 VGND $end
-$var wire 1 ~1 VNB $end
-$var wire 1 !2 VPB $end
-$var wire 1 "2 VPWR $end
-$var wire 1 #2 Z $end
-$scope module sc_cell $end
-$var wire 1 {1 A $end
-$var wire 1 |1 TE_B $end
-$var wire 1 #2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[102] $end
-$var wire 1 $2 A $end
-$var wire 1 %2 TE_B $end
-$var wire 1 &2 VGND $end
-$var wire 1 '2 VNB $end
-$var wire 1 (2 VPB $end
-$var wire 1 )2 VPWR $end
-$var wire 1 *2 Z $end
-$scope module sc_cell $end
-$var wire 1 $2 A $end
-$var wire 1 %2 TE_B $end
-$var wire 1 *2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[103] $end
-$var wire 1 +2 A $end
-$var wire 1 ,2 TE_B $end
-$var wire 1 -2 VGND $end
-$var wire 1 .2 VNB $end
-$var wire 1 /2 VPB $end
-$var wire 1 02 VPWR $end
-$var wire 1 12 Z $end
-$scope module sc_cell $end
-$var wire 1 +2 A $end
-$var wire 1 ,2 TE_B $end
-$var wire 1 12 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[104] $end
-$var wire 1 22 A $end
-$var wire 1 32 TE_B $end
-$var wire 1 42 VGND $end
-$var wire 1 52 VNB $end
-$var wire 1 62 VPB $end
-$var wire 1 72 VPWR $end
-$var wire 1 82 Z $end
-$scope module sc_cell $end
-$var wire 1 22 A $end
-$var wire 1 32 TE_B $end
-$var wire 1 82 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[105] $end
-$var wire 1 92 A $end
-$var wire 1 :2 TE_B $end
-$var wire 1 ;2 VGND $end
-$var wire 1 <2 VNB $end
-$var wire 1 =2 VPB $end
-$var wire 1 >2 VPWR $end
-$var wire 1 ?2 Z $end
-$scope module sc_cell $end
-$var wire 1 92 A $end
-$var wire 1 :2 TE_B $end
-$var wire 1 ?2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[106] $end
-$var wire 1 @2 A $end
-$var wire 1 A2 TE_B $end
-$var wire 1 B2 VGND $end
-$var wire 1 C2 VNB $end
-$var wire 1 D2 VPB $end
-$var wire 1 E2 VPWR $end
-$var wire 1 F2 Z $end
-$scope module sc_cell $end
-$var wire 1 @2 A $end
-$var wire 1 A2 TE_B $end
-$var wire 1 F2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[107] $end
-$var wire 1 G2 A $end
-$var wire 1 H2 TE_B $end
-$var wire 1 I2 VGND $end
-$var wire 1 J2 VNB $end
-$var wire 1 K2 VPB $end
-$var wire 1 L2 VPWR $end
-$var wire 1 M2 Z $end
-$scope module sc_cell $end
-$var wire 1 G2 A $end
-$var wire 1 H2 TE_B $end
-$var wire 1 M2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[108] $end
-$var wire 1 N2 A $end
-$var wire 1 O2 TE_B $end
-$var wire 1 P2 VGND $end
-$var wire 1 Q2 VNB $end
-$var wire 1 R2 VPB $end
-$var wire 1 S2 VPWR $end
-$var wire 1 T2 Z $end
-$scope module sc_cell $end
-$var wire 1 N2 A $end
-$var wire 1 O2 TE_B $end
-$var wire 1 T2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[109] $end
-$var wire 1 U2 A $end
-$var wire 1 V2 TE_B $end
-$var wire 1 W2 VGND $end
-$var wire 1 X2 VNB $end
-$var wire 1 Y2 VPB $end
-$var wire 1 Z2 VPWR $end
-$var wire 1 [2 Z $end
-$scope module sc_cell $end
-$var wire 1 U2 A $end
-$var wire 1 V2 TE_B $end
-$var wire 1 [2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[110] $end
-$var wire 1 \2 A $end
-$var wire 1 ]2 TE_B $end
-$var wire 1 ^2 VGND $end
-$var wire 1 _2 VNB $end
-$var wire 1 `2 VPB $end
-$var wire 1 a2 VPWR $end
-$var wire 1 b2 Z $end
-$scope module sc_cell $end
-$var wire 1 \2 A $end
-$var wire 1 ]2 TE_B $end
-$var wire 1 b2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[111] $end
-$var wire 1 c2 A $end
-$var wire 1 d2 TE_B $end
-$var wire 1 e2 VGND $end
-$var wire 1 f2 VNB $end
-$var wire 1 g2 VPB $end
-$var wire 1 h2 VPWR $end
-$var wire 1 i2 Z $end
-$scope module sc_cell $end
-$var wire 1 c2 A $end
-$var wire 1 d2 TE_B $end
-$var wire 1 i2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[112] $end
-$var wire 1 j2 A $end
-$var wire 1 k2 TE_B $end
-$var wire 1 l2 VGND $end
-$var wire 1 m2 VNB $end
-$var wire 1 n2 VPB $end
-$var wire 1 o2 VPWR $end
-$var wire 1 p2 Z $end
-$scope module sc_cell $end
-$var wire 1 j2 A $end
-$var wire 1 k2 TE_B $end
-$var wire 1 p2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[113] $end
-$var wire 1 q2 A $end
-$var wire 1 r2 TE_B $end
-$var wire 1 s2 VGND $end
-$var wire 1 t2 VNB $end
-$var wire 1 u2 VPB $end
-$var wire 1 v2 VPWR $end
-$var wire 1 w2 Z $end
-$scope module sc_cell $end
-$var wire 1 q2 A $end
-$var wire 1 r2 TE_B $end
-$var wire 1 w2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[114] $end
-$var wire 1 x2 A $end
-$var wire 1 y2 TE_B $end
-$var wire 1 z2 VGND $end
-$var wire 1 {2 VNB $end
-$var wire 1 |2 VPB $end
-$var wire 1 }2 VPWR $end
-$var wire 1 ~2 Z $end
-$scope module sc_cell $end
-$var wire 1 x2 A $end
-$var wire 1 y2 TE_B $end
-$var wire 1 ~2 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[115] $end
-$var wire 1 !3 A $end
-$var wire 1 "3 TE_B $end
-$var wire 1 #3 VGND $end
-$var wire 1 $3 VNB $end
-$var wire 1 %3 VPB $end
-$var wire 1 &3 VPWR $end
-$var wire 1 '3 Z $end
-$scope module sc_cell $end
-$var wire 1 !3 A $end
-$var wire 1 "3 TE_B $end
-$var wire 1 '3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[116] $end
-$var wire 1 (3 A $end
-$var wire 1 )3 TE_B $end
-$var wire 1 *3 VGND $end
-$var wire 1 +3 VNB $end
-$var wire 1 ,3 VPB $end
-$var wire 1 -3 VPWR $end
-$var wire 1 .3 Z $end
-$scope module sc_cell $end
-$var wire 1 (3 A $end
-$var wire 1 )3 TE_B $end
-$var wire 1 .3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[117] $end
-$var wire 1 /3 A $end
-$var wire 1 03 TE_B $end
-$var wire 1 13 VGND $end
-$var wire 1 23 VNB $end
-$var wire 1 33 VPB $end
-$var wire 1 43 VPWR $end
-$var wire 1 53 Z $end
-$scope module sc_cell $end
-$var wire 1 /3 A $end
-$var wire 1 03 TE_B $end
-$var wire 1 53 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[118] $end
-$var wire 1 63 A $end
-$var wire 1 73 TE_B $end
-$var wire 1 83 VGND $end
-$var wire 1 93 VNB $end
-$var wire 1 :3 VPB $end
-$var wire 1 ;3 VPWR $end
-$var wire 1 <3 Z $end
-$scope module sc_cell $end
-$var wire 1 63 A $end
-$var wire 1 73 TE_B $end
-$var wire 1 <3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[119] $end
-$var wire 1 =3 A $end
-$var wire 1 >3 TE_B $end
-$var wire 1 ?3 VGND $end
-$var wire 1 @3 VNB $end
-$var wire 1 A3 VPB $end
-$var wire 1 B3 VPWR $end
-$var wire 1 C3 Z $end
-$scope module sc_cell $end
-$var wire 1 =3 A $end
-$var wire 1 >3 TE_B $end
-$var wire 1 C3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[120] $end
-$var wire 1 D3 A $end
-$var wire 1 E3 TE_B $end
-$var wire 1 F3 VGND $end
-$var wire 1 G3 VNB $end
-$var wire 1 H3 VPB $end
-$var wire 1 I3 VPWR $end
-$var wire 1 J3 Z $end
-$scope module sc_cell $end
-$var wire 1 D3 A $end
-$var wire 1 E3 TE_B $end
-$var wire 1 J3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[121] $end
-$var wire 1 K3 A $end
-$var wire 1 L3 TE_B $end
-$var wire 1 M3 VGND $end
-$var wire 1 N3 VNB $end
-$var wire 1 O3 VPB $end
-$var wire 1 P3 VPWR $end
-$var wire 1 Q3 Z $end
-$scope module sc_cell $end
-$var wire 1 K3 A $end
-$var wire 1 L3 TE_B $end
-$var wire 1 Q3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[122] $end
-$var wire 1 R3 A $end
-$var wire 1 S3 TE_B $end
-$var wire 1 T3 VGND $end
-$var wire 1 U3 VNB $end
-$var wire 1 V3 VPB $end
-$var wire 1 W3 VPWR $end
-$var wire 1 X3 Z $end
-$scope module sc_cell $end
-$var wire 1 R3 A $end
-$var wire 1 S3 TE_B $end
-$var wire 1 X3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[123] $end
-$var wire 1 Y3 A $end
-$var wire 1 Z3 TE_B $end
-$var wire 1 [3 VGND $end
-$var wire 1 \3 VNB $end
-$var wire 1 ]3 VPB $end
-$var wire 1 ^3 VPWR $end
-$var wire 1 _3 Z $end
-$scope module sc_cell $end
-$var wire 1 Y3 A $end
-$var wire 1 Z3 TE_B $end
-$var wire 1 _3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[124] $end
-$var wire 1 `3 A $end
-$var wire 1 a3 TE_B $end
-$var wire 1 b3 VGND $end
-$var wire 1 c3 VNB $end
-$var wire 1 d3 VPB $end
-$var wire 1 e3 VPWR $end
-$var wire 1 f3 Z $end
-$scope module sc_cell $end
-$var wire 1 `3 A $end
-$var wire 1 a3 TE_B $end
-$var wire 1 f3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[125] $end
-$var wire 1 g3 A $end
-$var wire 1 h3 TE_B $end
-$var wire 1 i3 VGND $end
-$var wire 1 j3 VNB $end
-$var wire 1 k3 VPB $end
-$var wire 1 l3 VPWR $end
-$var wire 1 m3 Z $end
-$scope module sc_cell $end
-$var wire 1 g3 A $end
-$var wire 1 h3 TE_B $end
-$var wire 1 m3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[126] $end
-$var wire 1 n3 A $end
-$var wire 1 o3 TE_B $end
-$var wire 1 p3 VGND $end
-$var wire 1 q3 VNB $end
-$var wire 1 r3 VPB $end
-$var wire 1 s3 VPWR $end
-$var wire 1 t3 Z $end
-$scope module sc_cell $end
-$var wire 1 n3 A $end
-$var wire 1 o3 TE_B $end
-$var wire 1 t3 Z $end
-$upscope $end
-$upscope $end
-$scope module la_buf[127] $end
-$var wire 1 u3 A $end
-$var wire 1 v3 TE_B $end
-$var wire 1 w3 VGND $end
-$var wire 1 x3 VNB $end
-$var wire 1 y3 VPB $end
-$var wire 1 z3 VPWR $end
-$var wire 1 {3 Z $end
-$scope module sc_cell $end
-$var wire 1 u3 A $end
-$var wire 1 v3 TE_B $end
-$var wire 1 {3 Z $end
-$upscope $end
-$upscope $end
-$scope module levelshift $end
-$var wire 1 i X $end
-$var wire 1 j A $end
-$upscope $end
-$scope module mprj $end
-$var wire 32 |3 io_out [31:0] $end
-$var wire 128 }3 la_data_in [127:0] $end
-$var wire 32 ~3 la_write [31:0] $end
-$var wire 1 !4 valid $end
-$var wire 1 "4 wb_rst_i $end
-$var wire 1 R wbs_ack_o $end
-$var wire 32 #4 wbs_adr_i [31:0] $end
-$var wire 1 T wbs_cyc_i $end
-$var wire 32 $4 wbs_dat_i [31:0] $end
-$var wire 32 %4 wbs_dat_o [31:0] $end
-$var wire 4 &4 wbs_sel_i [3:0] $end
-$var wire 1 \ wbs_we_i $end
-$var wire 32 '4 wdata [31:0] $end
-$var wire 4 (4 wstrb [3:0] $end
-$var wire 1 l wbs_stb_i $end
-$var wire 1 )4 wbs_ack_i $end
-$var wire 1 9" wb_clk_i $end
-$var wire 1 *4 rst $end
-$var wire 32 +4 rdata [31:0] $end
-$var wire 128 ,4 la_oen [127:0] $end
-$var wire 128 -4 la_data_out [127:0] $end
-$var wire 32 .4 io_in [31:0] $end
-$var wire 32 /4 count [31:0] $end
-$var wire 1 04 clk $end
-$scope module counter $end
-$var wire 1 04 clk $end
-$var wire 32 14 la_input [31:0] $end
-$var wire 32 24 la_write [31:0] $end
-$var wire 1 *4 reset $end
-$var wire 1 !4 valid $end
-$var wire 32 34 wdata [31:0] $end
-$var wire 4 44 wstrb [3:0] $end
-$var reg 32 54 count [31:0] $end
-$var reg 32 64 rdata [31:0] $end
-$var reg 1 )4 ready $end
-$scope begin genblk1[0] $end
-$upscope $end
-$scope begin genblk1[1] $end
-$upscope $end
-$scope begin genblk1[2] $end
-$upscope $end
-$scope begin genblk1[3] $end
-$upscope $end
-$scope begin genblk1[4] $end
-$upscope $end
-$scope begin genblk1[5] $end
-$upscope $end
-$scope begin genblk1[6] $end
-$upscope $end
-$scope begin genblk1[7] $end
-$upscope $end
-$scope begin genblk1[8] $end
-$upscope $end
-$scope begin genblk1[9] $end
-$upscope $end
-$scope begin genblk1[10] $end
-$upscope $end
-$scope begin genblk1[11] $end
-$upscope $end
-$scope begin genblk1[12] $end
-$upscope $end
-$scope begin genblk1[13] $end
-$upscope $end
-$scope begin genblk1[14] $end
-$upscope $end
-$scope begin genblk1[15] $end
-$upscope $end
-$scope begin genblk1[16] $end
-$upscope $end
-$scope begin genblk1[17] $end
-$upscope $end
-$scope begin genblk1[18] $end
-$upscope $end
-$scope begin genblk1[19] $end
-$upscope $end
-$scope begin genblk1[20] $end
-$upscope $end
-$scope begin genblk1[21] $end
-$upscope $end
-$scope begin genblk1[22] $end
-$upscope $end
-$scope begin genblk1[23] $end
-$upscope $end
-$scope begin genblk1[24] $end
-$upscope $end
-$scope begin genblk1[25] $end
-$upscope $end
-$scope begin genblk1[26] $end
-$upscope $end
-$scope begin genblk1[27] $end
-$upscope $end
-$scope begin genblk1[28] $end
-$upscope $end
-$scope begin genblk1[29] $end
-$upscope $end
-$scope begin genblk1[30] $end
-$upscope $end
-$scope begin genblk1[31] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module padframe $end
-$var wire 1 74 analog_a $end
-$var wire 1 84 analog_b $end
-$var wire 1 N clock $end
-$var wire 1 ) flash_clk $end
-$var wire 1 O flash_clk_ieb_core $end
-$var wire 1 * flash_csb $end
-$var wire 1 P flash_csb_ieb_core $end
-$var wire 1 + flash_io0 $end
-$var wire 1 , flash_io1 $end
-$var wire 1 - gpio $end
-$var wire 32 94 mprj_io [31:0] $end
-$var wire 32 :4 mprj_io_analog_en [31:0] $end
-$var wire 32 ;4 mprj_io_analog_pol [31:0] $end
-$var wire 32 <4 mprj_io_analog_sel [31:0] $end
-$var wire 96 =4 mprj_io_dm [95:0] $end
-$var wire 32 >4 mprj_io_enh [31:0] $end
-$var wire 32 ?4 mprj_io_hldh_n [31:0] $end
-$var wire 32 @4 mprj_io_holdover [31:0] $end
-$var wire 32 A4 mprj_io_ib_mode_sel [31:0] $end
-$var wire 32 B4 mprj_io_inp_dis [31:0] $end
-$var wire 32 C4 mprj_io_oeb_n [31:0] $end
-$var wire 32 D4 mprj_io_out [31:0] $end
-$var wire 32 E4 mprj_io_slow_sel [31:0] $end
-$var wire 32 F4 mprj_io_vtrip_sel [31:0] $end
-$var wire 1 G4 por $end
-$var wire 1 ] resetb $end
-$var wire 1 H4 vdd $end
-$var wire 1 % vdd1v8 $end
-$var wire 1 & vdd3v3 $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vss $end
-$var wire 1 J4 xresloop $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 j porb_h $end
-$var wire 1 k pll_clk16 $end
-$var wire 32 L4 mprj_io_in [31:0] $end
-$var wire 1 M4 loop_gpio $end
-$var wire 1 N4 loop_flash_io1 $end
-$var wire 1 O4 loop_flash_io0 $end
-$var wire 1 P4 loop_flash_csb $end
-$var wire 1 Q4 loop_flash_clk $end
-$var wire 1 R4 loop_clock $end
-$var wire 1 %" gpio_outenb_core $end
-$var wire 1 &" gpio_out_core $end
-$var wire 1 '" gpio_mode1_core $end
-$var wire 1 (" gpio_mode0_core $end
-$var wire 1 )" gpio_inenb_core $end
-$var wire 1 *" gpio_in_core $end
-$var wire 1 +" flash_io1_oeb_core $end
-$var wire 3 S4 flash_io1_mode [2:0] $end
-$var wire 1 ," flash_io1_ieb_core $end
-$var wire 1 -" flash_io1_do_core $end
-$var wire 1 ." flash_io1_di_core $end
-$var wire 1 /" flash_io0_oeb_core $end
-$var wire 3 T4 flash_io0_mode [2:0] $end
-$var wire 1 0" flash_io0_ieb_core $end
-$var wire 1 1" flash_io0_do_core $end
-$var wire 1 2" flash_io0_di_core $end
-$var wire 1 3" flash_csb_oeb_core $end
-$var wire 1 4" flash_csb_core $end
-$var wire 1 5" flash_clk_oeb_core $end
-$var wire 1 6" flash_clk_core $end
-$var wire 3 U4 dm_all [2:0] $end
-$var wire 1 7" clock_core $end
-$scope module clock_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 V4 dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 G4 inp_dis $end
-$var wire 1 % oe_n $end
-$var wire 1 ' out $end
-$var wire 1 N pad $end
-$var wire 1 W4 pad_a_esd_0_h $end
-$var wire 1 X4 pad_a_esd_1_h $end
-$var wire 1 Y4 pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 R4 tie_lo_esd $end
-$var wire 1 Z4 tie_hi_esd $end
-$var wire 1 [4 in_h $end
-$var wire 1 7" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 R4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 \4 event_error_vswitch5 $end
-$var event 1 ]4 event_error_vswitch4 $end
-$var event 1 ^4 event_error_vswitch3 $end
-$var event 1 _4 event_error_vswitch2 $end
-$var event 1 `4 event_error_vswitch1 $end
-$var event 1 a4 event_error_vddio_q2 $end
-$var event 1 b4 event_error_vddio_q1 $end
-$var event 1 c4 event_error_vdda_vddioq_vswitch2 $end
-$var event 1 d4 event_error_vdda3 $end
-$var event 1 e4 event_error_vdda2 $end
-$var event 1 f4 event_error_vdda $end
-$var event 1 g4 event_error_supply_good $end
-$var event 1 h4 event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 i4 dm [2:0] $end
-$var wire 3 j4 dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 k4 error_enable_vddio $end
-$var wire 1 l4 error_supply_good $end
-$var wire 1 m4 error_vdda $end
-$var wire 1 n4 error_vdda2 $end
-$var wire 1 o4 error_vdda3 $end
-$var wire 1 p4 error_vdda_vddioq_vswitch2 $end
-$var wire 1 q4 error_vddio_q1 $end
-$var wire 1 r4 error_vddio_q2 $end
-$var wire 1 s4 error_vswitch1 $end
-$var wire 1 t4 error_vswitch2 $end
-$var wire 1 u4 error_vswitch3 $end
-$var wire 1 v4 error_vswitch4 $end
-$var wire 1 w4 error_vswitch5 $end
-$var wire 1 x4 functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 y4 hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 z4 hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 {4 ib_mode_sel_buf $end
-$var wire 1 G4 inp_dis $end
-$var wire 1 |4 inp_dis_buf $end
-$var wire 1 }4 invalid_controls_amux $end
-$var wire 1 % oe_n $end
-$var wire 1 ~4 oe_n_buf $end
-$var wire 1 ' out $end
-$var wire 1 !5 out_buf $end
-$var wire 1 N pad $end
-$var wire 1 W4 pad_a_esd_0_h $end
-$var wire 1 X4 pad_a_esd_1_h $end
-$var wire 1 Y4 pad_a_noesd_h $end
-$var wire 1 "5 pad_tristate $end
-$var wire 1 #5 pwr_good_active_mode $end
-$var wire 1 $5 pwr_good_active_mode_vdda $end
-$var wire 1 %5 pwr_good_amux $end
-$var wire 1 &5 pwr_good_analog_en_vdda $end
-$var wire 1 '5 pwr_good_analog_en_vddio_q $end
-$var wire 1 (5 pwr_good_analog_en_vswitch $end
-$var wire 1 )5 pwr_good_hold_mode $end
-$var wire 1 *5 pwr_good_hold_mode_vdda $end
-$var wire 1 +5 pwr_good_hold_ovr_mode $end
-$var wire 1 ,5 pwr_good_inpbuff_hv $end
-$var wire 1 -5 pwr_good_inpbuff_lv $end
-$var wire 1 .5 pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 /5 slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 05 vtrip_sel_buf $end
-$var wire 1 15 x_on_analog_en_vdda $end
-$var wire 1 25 x_on_analog_en_vddio_q $end
-$var wire 1 35 x_on_analog_en_vswitch $end
-$var wire 1 45 x_on_in_hv $end
-$var wire 1 55 x_on_in_lv $end
-$var wire 1 65 x_on_pad $end
-$var wire 1 75 zero_on_analog_en_vdda $end
-$var wire 1 85 zero_on_analog_en_vddio_q $end
-$var wire 1 95 zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 R4 tie_lo_esd $end
-$var wire 1 Z4 tie_hi_esd $end
-$var wire 1 :5 pwr_good_amux_vccd $end
-$var wire 1 [4 in_h $end
-$var wire 1 7" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 ;5 enable_pad_vssio_q $end
-$var wire 1 <5 enable_pad_vddio_q $end
-$var wire 1 =5 enable_pad_amuxbus_b $end
-$var wire 1 >5 enable_pad_amuxbus_a $end
-$var wire 1 R4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 ?5 disable_inp_buff_lv $end
-$var wire 1 @5 disable_inp_buff $end
-$var wire 3 A5 amux_select [2:0] $end
-$var reg 1 B5 analog_en_final $end
-$var reg 1 C5 analog_en_vdda $end
-$var reg 1 D5 analog_en_vddio_q $end
-$var reg 1 E5 analog_en_vswitch $end
-$var reg 1 F5 dis_err_msgs $end
-$var reg 3 G5 dm_final [2:0] $end
-$var reg 1 H5 hld_ovr_final $end
-$var reg 1 I5 ib_mode_sel_final $end
-$var reg 1 J5 inp_dis_final $end
-$var reg 1 K5 notifier_dm $end
-$var reg 1 L5 notifier_enable_h $end
-$var reg 1 M5 notifier_hld_ovr $end
-$var reg 1 N5 notifier_ib_mode_sel $end
-$var reg 1 O5 notifier_inp_dis $end
-$var reg 1 P5 notifier_oe_n $end
-$var reg 1 Q5 notifier_out $end
-$var reg 1 R5 notifier_slow $end
-$var reg 1 S5 notifier_vtrip_sel $end
-$var reg 1 T5 oe_n_final $end
-$var reg 1 U5 out_final $end
-$var reg 1 V5 slow_final $end
-$var reg 1 W5 vtrip_sel_final $end
-$var integer 32 X5 msg_count_pad [31:0] $end
-$var integer 32 Y5 msg_count_pad1 [31:0] $end
-$var integer 32 Z5 msg_count_pad10 [31:0] $end
-$var integer 32 [5 msg_count_pad11 [31:0] $end
-$var integer 32 \5 msg_count_pad12 [31:0] $end
-$var integer 32 ]5 msg_count_pad2 [31:0] $end
-$var integer 32 ^5 msg_count_pad3 [31:0] $end
-$var integer 32 _5 msg_count_pad4 [31:0] $end
-$var integer 32 `5 msg_count_pad5 [31:0] $end
-$var integer 32 a5 msg_count_pad6 [31:0] $end
-$var integer 32 b5 msg_count_pad7 [31:0] $end
-$var integer 32 c5 msg_count_pad8 [31:0] $end
-$var integer 32 d5 msg_count_pad9 [31:0] $end
-$var integer 32 e5 slow_0_delay [31:0] $end
-$var integer 32 f5 slow_1_delay [31:0] $end
-$var integer 32 g5 slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module corner[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$scope module corner[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$scope module corner[2] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$scope module corner[3] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$scope module flash_clk_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 h5 dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 O inp_dis $end
-$var wire 1 ) pad $end
-$var wire 1 i5 pad_a_esd_0_h $end
-$var wire 1 j5 pad_a_esd_1_h $end
-$var wire 1 k5 pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 Q4 tie_lo_esd $end
-$var wire 1 l5 tie_hi_esd $end
-$var wire 1 6" out $end
-$var wire 1 5" oe_n $end
-$var wire 1 m5 in_h $end
-$var wire 1 n5 in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 Q4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 o5 event_error_vswitch5 $end
-$var event 1 p5 event_error_vswitch4 $end
-$var event 1 q5 event_error_vswitch3 $end
-$var event 1 r5 event_error_vswitch2 $end
-$var event 1 s5 event_error_vswitch1 $end
-$var event 1 t5 event_error_vddio_q2 $end
-$var event 1 u5 event_error_vddio_q1 $end
-$var event 1 v5 event_error_vdda_vddioq_vswitch2 $end
-$var event 1 w5 event_error_vdda3 $end
-$var event 1 x5 event_error_vdda2 $end
-$var event 1 y5 event_error_vdda $end
-$var event 1 z5 event_error_supply_good $end
-$var event 1 {5 event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 |5 dm [2:0] $end
-$var wire 3 }5 dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ~5 error_enable_vddio $end
-$var wire 1 !6 error_supply_good $end
-$var wire 1 "6 error_vdda $end
-$var wire 1 #6 error_vdda2 $end
-$var wire 1 $6 error_vdda3 $end
-$var wire 1 %6 error_vdda_vddioq_vswitch2 $end
-$var wire 1 &6 error_vddio_q1 $end
-$var wire 1 '6 error_vddio_q2 $end
-$var wire 1 (6 error_vswitch1 $end
-$var wire 1 )6 error_vswitch2 $end
-$var wire 1 *6 error_vswitch3 $end
-$var wire 1 +6 error_vswitch4 $end
-$var wire 1 ,6 error_vswitch5 $end
-$var wire 1 -6 functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 .6 hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 /6 hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 06 ib_mode_sel_buf $end
-$var wire 1 O inp_dis $end
-$var wire 1 16 inp_dis_buf $end
-$var wire 1 26 invalid_controls_amux $end
-$var wire 1 36 oe_n_buf $end
-$var wire 1 46 out_buf $end
-$var wire 1 ) pad $end
-$var wire 1 i5 pad_a_esd_0_h $end
-$var wire 1 j5 pad_a_esd_1_h $end
-$var wire 1 k5 pad_a_noesd_h $end
-$var wire 1 56 pad_tristate $end
-$var wire 1 66 pwr_good_active_mode $end
-$var wire 1 76 pwr_good_active_mode_vdda $end
-$var wire 1 86 pwr_good_amux $end
-$var wire 1 96 pwr_good_analog_en_vdda $end
-$var wire 1 :6 pwr_good_analog_en_vddio_q $end
-$var wire 1 ;6 pwr_good_analog_en_vswitch $end
-$var wire 1 <6 pwr_good_hold_mode $end
-$var wire 1 =6 pwr_good_hold_mode_vdda $end
-$var wire 1 >6 pwr_good_hold_ovr_mode $end
-$var wire 1 ?6 pwr_good_inpbuff_hv $end
-$var wire 1 @6 pwr_good_inpbuff_lv $end
-$var wire 1 A6 pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 B6 slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 C6 vtrip_sel_buf $end
-$var wire 1 D6 x_on_analog_en_vdda $end
-$var wire 1 E6 x_on_analog_en_vddio_q $end
-$var wire 1 F6 x_on_analog_en_vswitch $end
-$var wire 1 G6 x_on_in_hv $end
-$var wire 1 H6 x_on_in_lv $end
-$var wire 1 I6 x_on_pad $end
-$var wire 1 J6 zero_on_analog_en_vdda $end
-$var wire 1 K6 zero_on_analog_en_vddio_q $end
-$var wire 1 L6 zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 Q4 tie_lo_esd $end
-$var wire 1 l5 tie_hi_esd $end
-$var wire 1 M6 pwr_good_amux_vccd $end
-$var wire 1 6" out $end
-$var wire 1 5" oe_n $end
-$var wire 1 m5 in_h $end
-$var wire 1 n5 in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 N6 enable_pad_vssio_q $end
-$var wire 1 O6 enable_pad_vddio_q $end
-$var wire 1 P6 enable_pad_amuxbus_b $end
-$var wire 1 Q6 enable_pad_amuxbus_a $end
-$var wire 1 Q4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 R6 disable_inp_buff_lv $end
-$var wire 1 S6 disable_inp_buff $end
-$var wire 3 T6 amux_select [2:0] $end
-$var reg 1 U6 analog_en_final $end
-$var reg 1 V6 analog_en_vdda $end
-$var reg 1 W6 analog_en_vddio_q $end
-$var reg 1 X6 analog_en_vswitch $end
-$var reg 1 Y6 dis_err_msgs $end
-$var reg 3 Z6 dm_final [2:0] $end
-$var reg 1 [6 hld_ovr_final $end
-$var reg 1 \6 ib_mode_sel_final $end
-$var reg 1 ]6 inp_dis_final $end
-$var reg 1 ^6 notifier_dm $end
-$var reg 1 _6 notifier_enable_h $end
-$var reg 1 `6 notifier_hld_ovr $end
-$var reg 1 a6 notifier_ib_mode_sel $end
-$var reg 1 b6 notifier_inp_dis $end
-$var reg 1 c6 notifier_oe_n $end
-$var reg 1 d6 notifier_out $end
-$var reg 1 e6 notifier_slow $end
-$var reg 1 f6 notifier_vtrip_sel $end
-$var reg 1 g6 oe_n_final $end
-$var reg 1 h6 out_final $end
-$var reg 1 i6 slow_final $end
-$var reg 1 j6 vtrip_sel_final $end
-$var integer 32 k6 msg_count_pad [31:0] $end
-$var integer 32 l6 msg_count_pad1 [31:0] $end
-$var integer 32 m6 msg_count_pad10 [31:0] $end
-$var integer 32 n6 msg_count_pad11 [31:0] $end
-$var integer 32 o6 msg_count_pad12 [31:0] $end
-$var integer 32 p6 msg_count_pad2 [31:0] $end
-$var integer 32 q6 msg_count_pad3 [31:0] $end
-$var integer 32 r6 msg_count_pad4 [31:0] $end
-$var integer 32 s6 msg_count_pad5 [31:0] $end
-$var integer 32 t6 msg_count_pad6 [31:0] $end
-$var integer 32 u6 msg_count_pad7 [31:0] $end
-$var integer 32 v6 msg_count_pad8 [31:0] $end
-$var integer 32 w6 msg_count_pad9 [31:0] $end
-$var integer 32 x6 slow_0_delay [31:0] $end
-$var integer 32 y6 slow_1_delay [31:0] $end
-$var integer 32 z6 slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_csb_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 {6 dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 P inp_dis $end
-$var wire 1 * pad $end
-$var wire 1 |6 pad_a_esd_0_h $end
-$var wire 1 }6 pad_a_esd_1_h $end
-$var wire 1 ~6 pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 P4 tie_lo_esd $end
-$var wire 1 !7 tie_hi_esd $end
-$var wire 1 4" out $end
-$var wire 1 3" oe_n $end
-$var wire 1 "7 in_h $end
-$var wire 1 #7 in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 P4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 $7 event_error_vswitch5 $end
-$var event 1 %7 event_error_vswitch4 $end
-$var event 1 &7 event_error_vswitch3 $end
-$var event 1 '7 event_error_vswitch2 $end
-$var event 1 (7 event_error_vswitch1 $end
-$var event 1 )7 event_error_vddio_q2 $end
-$var event 1 *7 event_error_vddio_q1 $end
-$var event 1 +7 event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ,7 event_error_vdda3 $end
-$var event 1 -7 event_error_vdda2 $end
-$var event 1 .7 event_error_vdda $end
-$var event 1 /7 event_error_supply_good $end
-$var event 1 07 event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 17 dm [2:0] $end
-$var wire 3 27 dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 37 error_enable_vddio $end
-$var wire 1 47 error_supply_good $end
-$var wire 1 57 error_vdda $end
-$var wire 1 67 error_vdda2 $end
-$var wire 1 77 error_vdda3 $end
-$var wire 1 87 error_vdda_vddioq_vswitch2 $end
-$var wire 1 97 error_vddio_q1 $end
-$var wire 1 :7 error_vddio_q2 $end
-$var wire 1 ;7 error_vswitch1 $end
-$var wire 1 <7 error_vswitch2 $end
-$var wire 1 =7 error_vswitch3 $end
-$var wire 1 >7 error_vswitch4 $end
-$var wire 1 ?7 error_vswitch5 $end
-$var wire 1 @7 functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 A7 hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 B7 hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 C7 ib_mode_sel_buf $end
-$var wire 1 P inp_dis $end
-$var wire 1 D7 inp_dis_buf $end
-$var wire 1 E7 invalid_controls_amux $end
-$var wire 1 F7 oe_n_buf $end
-$var wire 1 G7 out_buf $end
-$var wire 1 * pad $end
-$var wire 1 |6 pad_a_esd_0_h $end
-$var wire 1 }6 pad_a_esd_1_h $end
-$var wire 1 ~6 pad_a_noesd_h $end
-$var wire 1 H7 pad_tristate $end
-$var wire 1 I7 pwr_good_active_mode $end
-$var wire 1 J7 pwr_good_active_mode_vdda $end
-$var wire 1 K7 pwr_good_amux $end
-$var wire 1 L7 pwr_good_analog_en_vdda $end
-$var wire 1 M7 pwr_good_analog_en_vddio_q $end
-$var wire 1 N7 pwr_good_analog_en_vswitch $end
-$var wire 1 O7 pwr_good_hold_mode $end
-$var wire 1 P7 pwr_good_hold_mode_vdda $end
-$var wire 1 Q7 pwr_good_hold_ovr_mode $end
-$var wire 1 R7 pwr_good_inpbuff_hv $end
-$var wire 1 S7 pwr_good_inpbuff_lv $end
-$var wire 1 T7 pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 U7 slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 V7 vtrip_sel_buf $end
-$var wire 1 W7 x_on_analog_en_vdda $end
-$var wire 1 X7 x_on_analog_en_vddio_q $end
-$var wire 1 Y7 x_on_analog_en_vswitch $end
-$var wire 1 Z7 x_on_in_hv $end
-$var wire 1 [7 x_on_in_lv $end
-$var wire 1 \7 x_on_pad $end
-$var wire 1 ]7 zero_on_analog_en_vdda $end
-$var wire 1 ^7 zero_on_analog_en_vddio_q $end
-$var wire 1 _7 zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 P4 tie_lo_esd $end
-$var wire 1 !7 tie_hi_esd $end
-$var wire 1 `7 pwr_good_amux_vccd $end
-$var wire 1 4" out $end
-$var wire 1 3" oe_n $end
-$var wire 1 "7 in_h $end
-$var wire 1 #7 in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 a7 enable_pad_vssio_q $end
-$var wire 1 b7 enable_pad_vddio_q $end
-$var wire 1 c7 enable_pad_amuxbus_b $end
-$var wire 1 d7 enable_pad_amuxbus_a $end
-$var wire 1 P4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 e7 disable_inp_buff_lv $end
-$var wire 1 f7 disable_inp_buff $end
-$var wire 3 g7 amux_select [2:0] $end
-$var reg 1 h7 analog_en_final $end
-$var reg 1 i7 analog_en_vdda $end
-$var reg 1 j7 analog_en_vddio_q $end
-$var reg 1 k7 analog_en_vswitch $end
-$var reg 1 l7 dis_err_msgs $end
-$var reg 3 m7 dm_final [2:0] $end
-$var reg 1 n7 hld_ovr_final $end
-$var reg 1 o7 ib_mode_sel_final $end
-$var reg 1 p7 inp_dis_final $end
-$var reg 1 q7 notifier_dm $end
-$var reg 1 r7 notifier_enable_h $end
-$var reg 1 s7 notifier_hld_ovr $end
-$var reg 1 t7 notifier_ib_mode_sel $end
-$var reg 1 u7 notifier_inp_dis $end
-$var reg 1 v7 notifier_oe_n $end
-$var reg 1 w7 notifier_out $end
-$var reg 1 x7 notifier_slow $end
-$var reg 1 y7 notifier_vtrip_sel $end
-$var reg 1 z7 oe_n_final $end
-$var reg 1 {7 out_final $end
-$var reg 1 |7 slow_final $end
-$var reg 1 }7 vtrip_sel_final $end
-$var integer 32 ~7 msg_count_pad [31:0] $end
-$var integer 32 !8 msg_count_pad1 [31:0] $end
-$var integer 32 "8 msg_count_pad10 [31:0] $end
-$var integer 32 #8 msg_count_pad11 [31:0] $end
-$var integer 32 $8 msg_count_pad12 [31:0] $end
-$var integer 32 %8 msg_count_pad2 [31:0] $end
-$var integer 32 &8 msg_count_pad3 [31:0] $end
-$var integer 32 '8 msg_count_pad4 [31:0] $end
-$var integer 32 (8 msg_count_pad5 [31:0] $end
-$var integer 32 )8 msg_count_pad6 [31:0] $end
-$var integer 32 *8 msg_count_pad7 [31:0] $end
-$var integer 32 +8 msg_count_pad8 [31:0] $end
-$var integer 32 ,8 msg_count_pad9 [31:0] $end
-$var integer 32 -8 slow_0_delay [31:0] $end
-$var integer 32 .8 slow_1_delay [31:0] $end
-$var integer 32 /8 slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_io0_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 08 dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 + pad $end
-$var wire 1 18 pad_a_esd_0_h $end
-$var wire 1 28 pad_a_esd_1_h $end
-$var wire 1 38 pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 O4 tie_lo_esd $end
-$var wire 1 48 tie_hi_esd $end
-$var wire 1 1" out $end
-$var wire 1 /" oe_n $end
-$var wire 1 0" inp_dis $end
-$var wire 1 58 in_h $end
-$var wire 1 2" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 O4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 68 event_error_vswitch5 $end
-$var event 1 78 event_error_vswitch4 $end
-$var event 1 88 event_error_vswitch3 $end
-$var event 1 98 event_error_vswitch2 $end
-$var event 1 :8 event_error_vswitch1 $end
-$var event 1 ;8 event_error_vddio_q2 $end
-$var event 1 <8 event_error_vddio_q1 $end
-$var event 1 =8 event_error_vdda_vddioq_vswitch2 $end
-$var event 1 >8 event_error_vdda3 $end
-$var event 1 ?8 event_error_vdda2 $end
-$var event 1 @8 event_error_vdda $end
-$var event 1 A8 event_error_supply_good $end
-$var event 1 B8 event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 C8 dm [2:0] $end
-$var wire 3 D8 dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 E8 error_enable_vddio $end
-$var wire 1 F8 error_supply_good $end
-$var wire 1 G8 error_vdda $end
-$var wire 1 H8 error_vdda2 $end
-$var wire 1 I8 error_vdda3 $end
-$var wire 1 J8 error_vdda_vddioq_vswitch2 $end
-$var wire 1 K8 error_vddio_q1 $end
-$var wire 1 L8 error_vddio_q2 $end
-$var wire 1 M8 error_vswitch1 $end
-$var wire 1 N8 error_vswitch2 $end
-$var wire 1 O8 error_vswitch3 $end
-$var wire 1 P8 error_vswitch4 $end
-$var wire 1 Q8 error_vswitch5 $end
-$var wire 1 R8 functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 S8 hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 T8 hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 U8 ib_mode_sel_buf $end
-$var wire 1 V8 inp_dis_buf $end
-$var wire 1 W8 invalid_controls_amux $end
-$var wire 1 X8 oe_n_buf $end
-$var wire 1 Y8 out_buf $end
-$var wire 1 + pad $end
-$var wire 1 18 pad_a_esd_0_h $end
-$var wire 1 28 pad_a_esd_1_h $end
-$var wire 1 38 pad_a_noesd_h $end
-$var wire 1 Z8 pad_tristate $end
-$var wire 1 [8 pwr_good_active_mode $end
-$var wire 1 \8 pwr_good_active_mode_vdda $end
-$var wire 1 ]8 pwr_good_amux $end
-$var wire 1 ^8 pwr_good_analog_en_vdda $end
-$var wire 1 _8 pwr_good_analog_en_vddio_q $end
-$var wire 1 `8 pwr_good_analog_en_vswitch $end
-$var wire 1 a8 pwr_good_hold_mode $end
-$var wire 1 b8 pwr_good_hold_mode_vdda $end
-$var wire 1 c8 pwr_good_hold_ovr_mode $end
-$var wire 1 d8 pwr_good_inpbuff_hv $end
-$var wire 1 e8 pwr_good_inpbuff_lv $end
-$var wire 1 f8 pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 g8 slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 h8 vtrip_sel_buf $end
-$var wire 1 i8 x_on_analog_en_vdda $end
-$var wire 1 j8 x_on_analog_en_vddio_q $end
-$var wire 1 k8 x_on_analog_en_vswitch $end
-$var wire 1 l8 x_on_in_hv $end
-$var wire 1 m8 x_on_in_lv $end
-$var wire 1 n8 x_on_pad $end
-$var wire 1 o8 zero_on_analog_en_vdda $end
-$var wire 1 p8 zero_on_analog_en_vddio_q $end
-$var wire 1 q8 zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 O4 tie_lo_esd $end
-$var wire 1 48 tie_hi_esd $end
-$var wire 1 r8 pwr_good_amux_vccd $end
-$var wire 1 1" out $end
-$var wire 1 /" oe_n $end
-$var wire 1 0" inp_dis $end
-$var wire 1 58 in_h $end
-$var wire 1 2" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 s8 enable_pad_vssio_q $end
-$var wire 1 t8 enable_pad_vddio_q $end
-$var wire 1 u8 enable_pad_amuxbus_b $end
-$var wire 1 v8 enable_pad_amuxbus_a $end
-$var wire 1 O4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 w8 disable_inp_buff_lv $end
-$var wire 1 x8 disable_inp_buff $end
-$var wire 3 y8 amux_select [2:0] $end
-$var reg 1 z8 analog_en_final $end
-$var reg 1 {8 analog_en_vdda $end
-$var reg 1 |8 analog_en_vddio_q $end
-$var reg 1 }8 analog_en_vswitch $end
-$var reg 1 ~8 dis_err_msgs $end
-$var reg 3 !9 dm_final [2:0] $end
-$var reg 1 "9 hld_ovr_final $end
-$var reg 1 #9 ib_mode_sel_final $end
-$var reg 1 $9 inp_dis_final $end
-$var reg 1 %9 notifier_dm $end
-$var reg 1 &9 notifier_enable_h $end
-$var reg 1 '9 notifier_hld_ovr $end
-$var reg 1 (9 notifier_ib_mode_sel $end
-$var reg 1 )9 notifier_inp_dis $end
-$var reg 1 *9 notifier_oe_n $end
-$var reg 1 +9 notifier_out $end
-$var reg 1 ,9 notifier_slow $end
-$var reg 1 -9 notifier_vtrip_sel $end
-$var reg 1 .9 oe_n_final $end
-$var reg 1 /9 out_final $end
-$var reg 1 09 slow_final $end
-$var reg 1 19 vtrip_sel_final $end
-$var integer 32 29 msg_count_pad [31:0] $end
-$var integer 32 39 msg_count_pad1 [31:0] $end
-$var integer 32 49 msg_count_pad10 [31:0] $end
-$var integer 32 59 msg_count_pad11 [31:0] $end
-$var integer 32 69 msg_count_pad12 [31:0] $end
-$var integer 32 79 msg_count_pad2 [31:0] $end
-$var integer 32 89 msg_count_pad3 [31:0] $end
-$var integer 32 99 msg_count_pad4 [31:0] $end
-$var integer 32 :9 msg_count_pad5 [31:0] $end
-$var integer 32 ;9 msg_count_pad6 [31:0] $end
-$var integer 32 <9 msg_count_pad7 [31:0] $end
-$var integer 32 =9 msg_count_pad8 [31:0] $end
-$var integer 32 >9 msg_count_pad9 [31:0] $end
-$var integer 32 ?9 slow_0_delay [31:0] $end
-$var integer 32 @9 slow_1_delay [31:0] $end
-$var integer 32 A9 slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_io1_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 B9 dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 , pad $end
-$var wire 1 C9 pad_a_esd_0_h $end
-$var wire 1 D9 pad_a_esd_1_h $end
-$var wire 1 E9 pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 N4 tie_lo_esd $end
-$var wire 1 F9 tie_hi_esd $end
-$var wire 1 -" out $end
-$var wire 1 +" oe_n $end
-$var wire 1 ," inp_dis $end
-$var wire 1 G9 in_h $end
-$var wire 1 ." in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 N4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 H9 event_error_vswitch5 $end
-$var event 1 I9 event_error_vswitch4 $end
-$var event 1 J9 event_error_vswitch3 $end
-$var event 1 K9 event_error_vswitch2 $end
-$var event 1 L9 event_error_vswitch1 $end
-$var event 1 M9 event_error_vddio_q2 $end
-$var event 1 N9 event_error_vddio_q1 $end
-$var event 1 O9 event_error_vdda_vddioq_vswitch2 $end
-$var event 1 P9 event_error_vdda3 $end
-$var event 1 Q9 event_error_vdda2 $end
-$var event 1 R9 event_error_vdda $end
-$var event 1 S9 event_error_supply_good $end
-$var event 1 T9 event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 U9 dm [2:0] $end
-$var wire 3 V9 dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 W9 error_enable_vddio $end
-$var wire 1 X9 error_supply_good $end
-$var wire 1 Y9 error_vdda $end
-$var wire 1 Z9 error_vdda2 $end
-$var wire 1 [9 error_vdda3 $end
-$var wire 1 \9 error_vdda_vddioq_vswitch2 $end
-$var wire 1 ]9 error_vddio_q1 $end
-$var wire 1 ^9 error_vddio_q2 $end
-$var wire 1 _9 error_vswitch1 $end
-$var wire 1 `9 error_vswitch2 $end
-$var wire 1 a9 error_vswitch3 $end
-$var wire 1 b9 error_vswitch4 $end
-$var wire 1 c9 error_vswitch5 $end
-$var wire 1 d9 functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 e9 hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 f9 hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 g9 ib_mode_sel_buf $end
-$var wire 1 h9 inp_dis_buf $end
-$var wire 1 i9 invalid_controls_amux $end
-$var wire 1 j9 oe_n_buf $end
-$var wire 1 k9 out_buf $end
-$var wire 1 , pad $end
-$var wire 1 C9 pad_a_esd_0_h $end
-$var wire 1 D9 pad_a_esd_1_h $end
-$var wire 1 E9 pad_a_noesd_h $end
-$var wire 1 l9 pad_tristate $end
-$var wire 1 m9 pwr_good_active_mode $end
-$var wire 1 n9 pwr_good_active_mode_vdda $end
-$var wire 1 o9 pwr_good_amux $end
-$var wire 1 p9 pwr_good_analog_en_vdda $end
-$var wire 1 q9 pwr_good_analog_en_vddio_q $end
-$var wire 1 r9 pwr_good_analog_en_vswitch $end
-$var wire 1 s9 pwr_good_hold_mode $end
-$var wire 1 t9 pwr_good_hold_mode_vdda $end
-$var wire 1 u9 pwr_good_hold_ovr_mode $end
-$var wire 1 v9 pwr_good_inpbuff_hv $end
-$var wire 1 w9 pwr_good_inpbuff_lv $end
-$var wire 1 x9 pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 y9 slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 z9 vtrip_sel_buf $end
-$var wire 1 {9 x_on_analog_en_vdda $end
-$var wire 1 |9 x_on_analog_en_vddio_q $end
-$var wire 1 }9 x_on_analog_en_vswitch $end
-$var wire 1 ~9 x_on_in_hv $end
-$var wire 1 !: x_on_in_lv $end
-$var wire 1 ": x_on_pad $end
-$var wire 1 #: zero_on_analog_en_vdda $end
-$var wire 1 $: zero_on_analog_en_vddio_q $end
-$var wire 1 %: zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 N4 tie_lo_esd $end
-$var wire 1 F9 tie_hi_esd $end
-$var wire 1 &: pwr_good_amux_vccd $end
-$var wire 1 -" out $end
-$var wire 1 +" oe_n $end
-$var wire 1 ," inp_dis $end
-$var wire 1 G9 in_h $end
-$var wire 1 ." in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 ': enable_pad_vssio_q $end
-$var wire 1 (: enable_pad_vddio_q $end
-$var wire 1 ): enable_pad_amuxbus_b $end
-$var wire 1 *: enable_pad_amuxbus_a $end
-$var wire 1 N4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 +: disable_inp_buff_lv $end
-$var wire 1 ,: disable_inp_buff $end
-$var wire 3 -: amux_select [2:0] $end
-$var reg 1 .: analog_en_final $end
-$var reg 1 /: analog_en_vdda $end
-$var reg 1 0: analog_en_vddio_q $end
-$var reg 1 1: analog_en_vswitch $end
-$var reg 1 2: dis_err_msgs $end
-$var reg 3 3: dm_final [2:0] $end
-$var reg 1 4: hld_ovr_final $end
-$var reg 1 5: ib_mode_sel_final $end
-$var reg 1 6: inp_dis_final $end
-$var reg 1 7: notifier_dm $end
-$var reg 1 8: notifier_enable_h $end
-$var reg 1 9: notifier_hld_ovr $end
-$var reg 1 :: notifier_ib_mode_sel $end
-$var reg 1 ;: notifier_inp_dis $end
-$var reg 1 <: notifier_oe_n $end
-$var reg 1 =: notifier_out $end
-$var reg 1 >: notifier_slow $end
-$var reg 1 ?: notifier_vtrip_sel $end
-$var reg 1 @: oe_n_final $end
-$var reg 1 A: out_final $end
-$var reg 1 B: slow_final $end
-$var reg 1 C: vtrip_sel_final $end
-$var integer 32 D: msg_count_pad [31:0] $end
-$var integer 32 E: msg_count_pad1 [31:0] $end
-$var integer 32 F: msg_count_pad10 [31:0] $end
-$var integer 32 G: msg_count_pad11 [31:0] $end
-$var integer 32 H: msg_count_pad12 [31:0] $end
-$var integer 32 I: msg_count_pad2 [31:0] $end
-$var integer 32 J: msg_count_pad3 [31:0] $end
-$var integer 32 K: msg_count_pad4 [31:0] $end
-$var integer 32 L: msg_count_pad5 [31:0] $end
-$var integer 32 M: msg_count_pad6 [31:0] $end
-$var integer 32 N: msg_count_pad7 [31:0] $end
-$var integer 32 O: msg_count_pad8 [31:0] $end
-$var integer 32 P: msg_count_pad9 [31:0] $end
-$var integer 32 Q: slow_0_delay [31:0] $end
-$var integer 32 R: slow_1_delay [31:0] $end
-$var integer 32 S: slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_pad $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 T: dm [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 & hld_h_n $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 - pad $end
-$var wire 1 U: pad_a_esd_0_h $end
-$var wire 1 V: pad_a_esd_1_h $end
-$var wire 1 W: pad_a_noesd_h $end
-$var wire 1 ' slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 M4 tie_lo_esd $end
-$var wire 1 X: tie_hi_esd $end
-$var wire 1 &" out $end
-$var wire 1 %" oe_n $end
-$var wire 1 )" inp_dis $end
-$var wire 1 Y: in_h $end
-$var wire 1 *" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 M4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$scope module gpiov2_base $end
-$var event 1 Z: event_error_vswitch5 $end
-$var event 1 [: event_error_vswitch4 $end
-$var event 1 \: event_error_vswitch3 $end
-$var event 1 ]: event_error_vswitch2 $end
-$var event 1 ^: event_error_vswitch1 $end
-$var event 1 _: event_error_vddio_q2 $end
-$var event 1 `: event_error_vddio_q1 $end
-$var event 1 a: event_error_vdda_vddioq_vswitch2 $end
-$var event 1 b: event_error_vdda3 $end
-$var event 1 c: event_error_vdda2 $end
-$var event 1 d: event_error_vdda $end
-$var event 1 e: event_error_supply_good $end
-$var event 1 f: event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' analog_en $end
-$var wire 1 ' analog_pol $end
-$var wire 1 ' analog_sel $end
-$var wire 3 g: dm [2:0] $end
-$var wire 3 h: dm_buf [2:0] $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 i: error_enable_vddio $end
-$var wire 1 j: error_supply_good $end
-$var wire 1 k: error_vdda $end
-$var wire 1 l: error_vdda2 $end
-$var wire 1 m: error_vdda3 $end
-$var wire 1 n: error_vdda_vddioq_vswitch2 $end
-$var wire 1 o: error_vddio_q1 $end
-$var wire 1 p: error_vddio_q2 $end
-$var wire 1 q: error_vswitch1 $end
-$var wire 1 r: error_vswitch2 $end
-$var wire 1 s: error_vswitch3 $end
-$var wire 1 t: error_vswitch4 $end
-$var wire 1 u: error_vswitch5 $end
-$var wire 1 v: functional_mode_amux $end
-$var wire 1 & hld_h_n $end
-$var wire 1 w: hld_h_n_buf $end
-$var wire 1 ' hld_ovr $end
-$var wire 1 x: hld_ovr_buf $end
-$var wire 1 ' ib_mode_sel $end
-$var wire 1 y: ib_mode_sel_buf $end
-$var wire 1 z: inp_dis_buf $end
-$var wire 1 {: invalid_controls_amux $end
-$var wire 1 |: oe_n_buf $end
-$var wire 1 }: out_buf $end
-$var wire 1 - pad $end
-$var wire 1 U: pad_a_esd_0_h $end
-$var wire 1 V: pad_a_esd_1_h $end
-$var wire 1 W: pad_a_noesd_h $end
-$var wire 1 ~: pad_tristate $end
-$var wire 1 !; pwr_good_active_mode $end
-$var wire 1 "; pwr_good_active_mode_vdda $end
-$var wire 1 #; pwr_good_amux $end
-$var wire 1 $; pwr_good_analog_en_vdda $end
-$var wire 1 %; pwr_good_analog_en_vddio_q $end
-$var wire 1 &; pwr_good_analog_en_vswitch $end
-$var wire 1 '; pwr_good_hold_mode $end
-$var wire 1 (; pwr_good_hold_mode_vdda $end
-$var wire 1 ); pwr_good_hold_ovr_mode $end
-$var wire 1 *; pwr_good_inpbuff_hv $end
-$var wire 1 +; pwr_good_inpbuff_lv $end
-$var wire 1 ,; pwr_good_output_driver $end
-$var wire 1 ' slow $end
-$var wire 1 -; slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ' vtrip_sel $end
-$var wire 1 .; vtrip_sel_buf $end
-$var wire 1 /; x_on_analog_en_vdda $end
-$var wire 1 0; x_on_analog_en_vddio_q $end
-$var wire 1 1; x_on_analog_en_vswitch $end
-$var wire 1 2; x_on_in_hv $end
-$var wire 1 3; x_on_in_lv $end
-$var wire 1 4; x_on_pad $end
-$var wire 1 5; zero_on_analog_en_vdda $end
-$var wire 1 6; zero_on_analog_en_vddio_q $end
-$var wire 1 7; zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 M4 tie_lo_esd $end
-$var wire 1 X: tie_hi_esd $end
-$var wire 1 8; pwr_good_amux_vccd $end
-$var wire 1 &" out $end
-$var wire 1 %" oe_n $end
-$var wire 1 )" inp_dis $end
-$var wire 1 Y: in_h $end
-$var wire 1 *" in $end
-$var wire 1 j enable_vdda_h $end
-$var wire 1 9; enable_pad_vssio_q $end
-$var wire 1 :; enable_pad_vddio_q $end
-$var wire 1 ;; enable_pad_amuxbus_b $end
-$var wire 1 <; enable_pad_amuxbus_a $end
-$var wire 1 M4 enable_inp_h $end
-$var wire 1 j enable_h $end
-$var wire 1 =; disable_inp_buff_lv $end
-$var wire 1 >; disable_inp_buff $end
-$var wire 3 ?; amux_select [2:0] $end
-$var reg 1 @; analog_en_final $end
-$var reg 1 A; analog_en_vdda $end
-$var reg 1 B; analog_en_vddio_q $end
-$var reg 1 C; analog_en_vswitch $end
-$var reg 1 D; dis_err_msgs $end
-$var reg 3 E; dm_final [2:0] $end
-$var reg 1 F; hld_ovr_final $end
-$var reg 1 G; ib_mode_sel_final $end
-$var reg 1 H; inp_dis_final $end
-$var reg 1 I; notifier_dm $end
-$var reg 1 J; notifier_enable_h $end
-$var reg 1 K; notifier_hld_ovr $end
-$var reg 1 L; notifier_ib_mode_sel $end
-$var reg 1 M; notifier_inp_dis $end
-$var reg 1 N; notifier_oe_n $end
-$var reg 1 O; notifier_out $end
-$var reg 1 P; notifier_slow $end
-$var reg 1 Q; notifier_vtrip_sel $end
-$var reg 1 R; oe_n_final $end
-$var reg 1 S; out_final $end
-$var reg 1 T; slow_final $end
-$var reg 1 U; vtrip_sel_final $end
-$var integer 32 V; msg_count_pad [31:0] $end
-$var integer 32 W; msg_count_pad1 [31:0] $end
-$var integer 32 X; msg_count_pad10 [31:0] $end
-$var integer 32 Y; msg_count_pad11 [31:0] $end
-$var integer 32 Z; msg_count_pad12 [31:0] $end
-$var integer 32 [; msg_count_pad2 [31:0] $end
-$var integer 32 \; msg_count_pad3 [31:0] $end
-$var integer 32 ]; msg_count_pad4 [31:0] $end
-$var integer 32 ^; msg_count_pad5 [31:0] $end
-$var integer 32 _; msg_count_pad6 [31:0] $end
-$var integer 32 `; msg_count_pad7 [31:0] $end
-$var integer 32 a; msg_count_pad8 [31:0] $end
-$var integer 32 b; msg_count_pad9 [31:0] $end
-$var integer 32 c; slow_0_delay [31:0] $end
-$var integer 32 d; slow_1_delay [31:0] $end
-$var integer 32 e; slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module mprj_pads $end
-$var wire 1 74 analog_a $end
-$var wire 1 84 analog_b $end
-$var wire 32 f; analog_en [31:0] $end
-$var wire 32 g; analog_pol [31:0] $end
-$var wire 32 h; analog_sel [31:0] $end
-$var wire 96 i; dm [95:0] $end
-$var wire 32 j; enh [31:0] $end
-$var wire 32 k; hldh_n [31:0] $end
-$var wire 1 l; holdolver $end
-$var wire 32 m; holdover [31:0] $end
-$var wire 32 n; ib_mode_sel [31:0] $end
-$var wire 32 o; inp_dis [31:0] $end
-$var wire 32 p; io [31:0] $end
-$var wire 32 q; io_out [31:0] $end
-$var wire 32 r; oeb_n [31:0] $end
-$var wire 1 s; porb_h $end
-$var wire 32 t; slow_sel [31:0] $end
-$var wire 1 & vdd $end
-$var wire 1 % vdd1v8 $end
-$var wire 1 u; vdd3v3 $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vss $end
-$var wire 32 v; vtrip_sel [31:0] $end
-$var wire 1 K4 vssio_q $end
-$var wire 32 w; loop_io [31:0] $end
-$var wire 32 x; io_in [31:0] $end
-$scope module io_pad[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 y; analog_en $end
-$var wire 1 z; analog_pol $end
-$var wire 1 {; analog_sel $end
-$var wire 3 |; dm [2:0] $end
-$var wire 1 }; enable_h $end
-$var wire 1 ~; enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 !< hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 "< ib_mode_sel $end
-$var wire 1 #< inp_dis $end
-$var wire 1 $< oe_n $end
-$var wire 1 %< out $end
-$var wire 1 &< pad $end
-$var wire 1 '< pad_a_esd_0_h $end
-$var wire 1 (< pad_a_esd_1_h $end
-$var wire 1 )< pad_a_noesd_h $end
-$var wire 1 *< slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 +< vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ,< tie_lo_esd $end
-$var wire 1 -< tie_hi_esd $end
-$var wire 1 .< in_h $end
-$var wire 1 /< in $end
-$scope module gpiov2_base $end
-$var event 1 0< event_error_vswitch5 $end
-$var event 1 1< event_error_vswitch4 $end
-$var event 1 2< event_error_vswitch3 $end
-$var event 1 3< event_error_vswitch2 $end
-$var event 1 4< event_error_vswitch1 $end
-$var event 1 5< event_error_vddio_q2 $end
-$var event 1 6< event_error_vddio_q1 $end
-$var event 1 7< event_error_vdda_vddioq_vswitch2 $end
-$var event 1 8< event_error_vdda3 $end
-$var event 1 9< event_error_vdda2 $end
-$var event 1 :< event_error_vdda $end
-$var event 1 ;< event_error_supply_good $end
-$var event 1 << event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 y; analog_en $end
-$var wire 1 z; analog_pol $end
-$var wire 1 {; analog_sel $end
-$var wire 3 =< dm [2:0] $end
-$var wire 3 >< dm_buf [2:0] $end
-$var wire 1 }; enable_h $end
-$var wire 1 ~; enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ?< error_enable_vddio $end
-$var wire 1 @< error_supply_good $end
-$var wire 1 A< error_vdda $end
-$var wire 1 B< error_vdda2 $end
-$var wire 1 C< error_vdda3 $end
-$var wire 1 D< error_vdda_vddioq_vswitch2 $end
-$var wire 1 E< error_vddio_q1 $end
-$var wire 1 F< error_vddio_q2 $end
-$var wire 1 G< error_vswitch1 $end
-$var wire 1 H< error_vswitch2 $end
-$var wire 1 I< error_vswitch3 $end
-$var wire 1 J< error_vswitch4 $end
-$var wire 1 K< error_vswitch5 $end
-$var wire 1 L< functional_mode_amux $end
-$var wire 1 !< hld_h_n $end
-$var wire 1 M< hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 N< hld_ovr_buf $end
-$var wire 1 "< ib_mode_sel $end
-$var wire 1 O< ib_mode_sel_buf $end
-$var wire 1 #< inp_dis $end
-$var wire 1 P< inp_dis_buf $end
-$var wire 1 Q< invalid_controls_amux $end
-$var wire 1 $< oe_n $end
-$var wire 1 R< oe_n_buf $end
-$var wire 1 %< out $end
-$var wire 1 S< out_buf $end
-$var wire 1 &< pad $end
-$var wire 1 '< pad_a_esd_0_h $end
-$var wire 1 (< pad_a_esd_1_h $end
-$var wire 1 )< pad_a_noesd_h $end
-$var wire 1 T< pad_tristate $end
-$var wire 1 U< pwr_good_active_mode $end
-$var wire 1 V< pwr_good_active_mode_vdda $end
-$var wire 1 W< pwr_good_amux $end
-$var wire 1 X< pwr_good_analog_en_vdda $end
-$var wire 1 Y< pwr_good_analog_en_vddio_q $end
-$var wire 1 Z< pwr_good_analog_en_vswitch $end
-$var wire 1 [< pwr_good_hold_mode $end
-$var wire 1 \< pwr_good_hold_mode_vdda $end
-$var wire 1 ]< pwr_good_hold_ovr_mode $end
-$var wire 1 ^< pwr_good_inpbuff_hv $end
-$var wire 1 _< pwr_good_inpbuff_lv $end
-$var wire 1 `< pwr_good_output_driver $end
-$var wire 1 *< slow $end
-$var wire 1 a< slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 +< vtrip_sel $end
-$var wire 1 b< vtrip_sel_buf $end
-$var wire 1 c< x_on_analog_en_vdda $end
-$var wire 1 d< x_on_analog_en_vddio_q $end
-$var wire 1 e< x_on_analog_en_vswitch $end
-$var wire 1 f< x_on_in_hv $end
-$var wire 1 g< x_on_in_lv $end
-$var wire 1 h< x_on_pad $end
-$var wire 1 i< zero_on_analog_en_vdda $end
-$var wire 1 j< zero_on_analog_en_vddio_q $end
-$var wire 1 k< zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ,< tie_lo_esd $end
-$var wire 1 -< tie_hi_esd $end
-$var wire 1 l< pwr_good_amux_vccd $end
-$var wire 1 .< in_h $end
-$var wire 1 /< in $end
-$var wire 1 m< enable_pad_vssio_q $end
-$var wire 1 n< enable_pad_vddio_q $end
-$var wire 1 o< enable_pad_amuxbus_b $end
-$var wire 1 p< enable_pad_amuxbus_a $end
-$var wire 1 q< disable_inp_buff_lv $end
-$var wire 1 r< disable_inp_buff $end
-$var wire 3 s< amux_select [2:0] $end
-$var reg 1 t< analog_en_final $end
-$var reg 1 u< analog_en_vdda $end
-$var reg 1 v< analog_en_vddio_q $end
-$var reg 1 w< analog_en_vswitch $end
-$var reg 1 x< dis_err_msgs $end
-$var reg 3 y< dm_final [2:0] $end
-$var reg 1 z< hld_ovr_final $end
-$var reg 1 {< ib_mode_sel_final $end
-$var reg 1 |< inp_dis_final $end
-$var reg 1 }< notifier_dm $end
-$var reg 1 ~< notifier_enable_h $end
-$var reg 1 != notifier_hld_ovr $end
-$var reg 1 "= notifier_ib_mode_sel $end
-$var reg 1 #= notifier_inp_dis $end
-$var reg 1 $= notifier_oe_n $end
-$var reg 1 %= notifier_out $end
-$var reg 1 &= notifier_slow $end
-$var reg 1 '= notifier_vtrip_sel $end
-$var reg 1 (= oe_n_final $end
-$var reg 1 )= out_final $end
-$var reg 1 *= slow_final $end
-$var reg 1 += vtrip_sel_final $end
-$var integer 32 ,= msg_count_pad [31:0] $end
-$var integer 32 -= msg_count_pad1 [31:0] $end
-$var integer 32 .= msg_count_pad10 [31:0] $end
-$var integer 32 /= msg_count_pad11 [31:0] $end
-$var integer 32 0= msg_count_pad12 [31:0] $end
-$var integer 32 1= msg_count_pad2 [31:0] $end
-$var integer 32 2= msg_count_pad3 [31:0] $end
-$var integer 32 3= msg_count_pad4 [31:0] $end
-$var integer 32 4= msg_count_pad5 [31:0] $end
-$var integer 32 5= msg_count_pad6 [31:0] $end
-$var integer 32 6= msg_count_pad7 [31:0] $end
-$var integer 32 7= msg_count_pad8 [31:0] $end
-$var integer 32 8= msg_count_pad9 [31:0] $end
-$var integer 32 9= slow_0_delay [31:0] $end
-$var integer 32 := slow_1_delay [31:0] $end
-$var integer 32 ;= slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 <= analog_en $end
-$var wire 1 == analog_pol $end
-$var wire 1 >= analog_sel $end
-$var wire 3 ?= dm [2:0] $end
-$var wire 1 @= enable_h $end
-$var wire 1 A= enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 B= hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 C= ib_mode_sel $end
-$var wire 1 D= inp_dis $end
-$var wire 1 E= oe_n $end
-$var wire 1 F= out $end
-$var wire 1 G= pad $end
-$var wire 1 H= pad_a_esd_0_h $end
-$var wire 1 I= pad_a_esd_1_h $end
-$var wire 1 J= pad_a_noesd_h $end
-$var wire 1 K= slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 L= vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 M= tie_lo_esd $end
-$var wire 1 N= tie_hi_esd $end
-$var wire 1 O= in_h $end
-$var wire 1 P= in $end
-$scope module gpiov2_base $end
-$var event 1 Q= event_error_vswitch5 $end
-$var event 1 R= event_error_vswitch4 $end
-$var event 1 S= event_error_vswitch3 $end
-$var event 1 T= event_error_vswitch2 $end
-$var event 1 U= event_error_vswitch1 $end
-$var event 1 V= event_error_vddio_q2 $end
-$var event 1 W= event_error_vddio_q1 $end
-$var event 1 X= event_error_vdda_vddioq_vswitch2 $end
-$var event 1 Y= event_error_vdda3 $end
-$var event 1 Z= event_error_vdda2 $end
-$var event 1 [= event_error_vdda $end
-$var event 1 \= event_error_supply_good $end
-$var event 1 ]= event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 <= analog_en $end
-$var wire 1 == analog_pol $end
-$var wire 1 >= analog_sel $end
-$var wire 3 ^= dm [2:0] $end
-$var wire 3 _= dm_buf [2:0] $end
-$var wire 1 @= enable_h $end
-$var wire 1 A= enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 `= error_enable_vddio $end
-$var wire 1 a= error_supply_good $end
-$var wire 1 b= error_vdda $end
-$var wire 1 c= error_vdda2 $end
-$var wire 1 d= error_vdda3 $end
-$var wire 1 e= error_vdda_vddioq_vswitch2 $end
-$var wire 1 f= error_vddio_q1 $end
-$var wire 1 g= error_vddio_q2 $end
-$var wire 1 h= error_vswitch1 $end
-$var wire 1 i= error_vswitch2 $end
-$var wire 1 j= error_vswitch3 $end
-$var wire 1 k= error_vswitch4 $end
-$var wire 1 l= error_vswitch5 $end
-$var wire 1 m= functional_mode_amux $end
-$var wire 1 B= hld_h_n $end
-$var wire 1 n= hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 o= hld_ovr_buf $end
-$var wire 1 C= ib_mode_sel $end
-$var wire 1 p= ib_mode_sel_buf $end
-$var wire 1 D= inp_dis $end
-$var wire 1 q= inp_dis_buf $end
-$var wire 1 r= invalid_controls_amux $end
-$var wire 1 E= oe_n $end
-$var wire 1 s= oe_n_buf $end
-$var wire 1 F= out $end
-$var wire 1 t= out_buf $end
-$var wire 1 G= pad $end
-$var wire 1 H= pad_a_esd_0_h $end
-$var wire 1 I= pad_a_esd_1_h $end
-$var wire 1 J= pad_a_noesd_h $end
-$var wire 1 u= pad_tristate $end
-$var wire 1 v= pwr_good_active_mode $end
-$var wire 1 w= pwr_good_active_mode_vdda $end
-$var wire 1 x= pwr_good_amux $end
-$var wire 1 y= pwr_good_analog_en_vdda $end
-$var wire 1 z= pwr_good_analog_en_vddio_q $end
-$var wire 1 {= pwr_good_analog_en_vswitch $end
-$var wire 1 |= pwr_good_hold_mode $end
-$var wire 1 }= pwr_good_hold_mode_vdda $end
-$var wire 1 ~= pwr_good_hold_ovr_mode $end
-$var wire 1 !> pwr_good_inpbuff_hv $end
-$var wire 1 "> pwr_good_inpbuff_lv $end
-$var wire 1 #> pwr_good_output_driver $end
-$var wire 1 K= slow $end
-$var wire 1 $> slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 L= vtrip_sel $end
-$var wire 1 %> vtrip_sel_buf $end
-$var wire 1 &> x_on_analog_en_vdda $end
-$var wire 1 '> x_on_analog_en_vddio_q $end
-$var wire 1 (> x_on_analog_en_vswitch $end
-$var wire 1 )> x_on_in_hv $end
-$var wire 1 *> x_on_in_lv $end
-$var wire 1 +> x_on_pad $end
-$var wire 1 ,> zero_on_analog_en_vdda $end
-$var wire 1 -> zero_on_analog_en_vddio_q $end
-$var wire 1 .> zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 M= tie_lo_esd $end
-$var wire 1 N= tie_hi_esd $end
-$var wire 1 /> pwr_good_amux_vccd $end
-$var wire 1 O= in_h $end
-$var wire 1 P= in $end
-$var wire 1 0> enable_pad_vssio_q $end
-$var wire 1 1> enable_pad_vddio_q $end
-$var wire 1 2> enable_pad_amuxbus_b $end
-$var wire 1 3> enable_pad_amuxbus_a $end
-$var wire 1 4> disable_inp_buff_lv $end
-$var wire 1 5> disable_inp_buff $end
-$var wire 3 6> amux_select [2:0] $end
-$var reg 1 7> analog_en_final $end
-$var reg 1 8> analog_en_vdda $end
-$var reg 1 9> analog_en_vddio_q $end
-$var reg 1 :> analog_en_vswitch $end
-$var reg 1 ;> dis_err_msgs $end
-$var reg 3 <> dm_final [2:0] $end
-$var reg 1 => hld_ovr_final $end
-$var reg 1 >> ib_mode_sel_final $end
-$var reg 1 ?> inp_dis_final $end
-$var reg 1 @> notifier_dm $end
-$var reg 1 A> notifier_enable_h $end
-$var reg 1 B> notifier_hld_ovr $end
-$var reg 1 C> notifier_ib_mode_sel $end
-$var reg 1 D> notifier_inp_dis $end
-$var reg 1 E> notifier_oe_n $end
-$var reg 1 F> notifier_out $end
-$var reg 1 G> notifier_slow $end
-$var reg 1 H> notifier_vtrip_sel $end
-$var reg 1 I> oe_n_final $end
-$var reg 1 J> out_final $end
-$var reg 1 K> slow_final $end
-$var reg 1 L> vtrip_sel_final $end
-$var integer 32 M> msg_count_pad [31:0] $end
-$var integer 32 N> msg_count_pad1 [31:0] $end
-$var integer 32 O> msg_count_pad10 [31:0] $end
-$var integer 32 P> msg_count_pad11 [31:0] $end
-$var integer 32 Q> msg_count_pad12 [31:0] $end
-$var integer 32 R> msg_count_pad2 [31:0] $end
-$var integer 32 S> msg_count_pad3 [31:0] $end
-$var integer 32 T> msg_count_pad4 [31:0] $end
-$var integer 32 U> msg_count_pad5 [31:0] $end
-$var integer 32 V> msg_count_pad6 [31:0] $end
-$var integer 32 W> msg_count_pad7 [31:0] $end
-$var integer 32 X> msg_count_pad8 [31:0] $end
-$var integer 32 Y> msg_count_pad9 [31:0] $end
-$var integer 32 Z> slow_0_delay [31:0] $end
-$var integer 32 [> slow_1_delay [31:0] $end
-$var integer 32 \> slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[2] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ]> analog_en $end
-$var wire 1 ^> analog_pol $end
-$var wire 1 _> analog_sel $end
-$var wire 3 `> dm [2:0] $end
-$var wire 1 a> enable_h $end
-$var wire 1 b> enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 c> hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 d> ib_mode_sel $end
-$var wire 1 e> inp_dis $end
-$var wire 1 f> oe_n $end
-$var wire 1 g> out $end
-$var wire 1 h> pad $end
-$var wire 1 i> pad_a_esd_0_h $end
-$var wire 1 j> pad_a_esd_1_h $end
-$var wire 1 k> pad_a_noesd_h $end
-$var wire 1 l> slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 m> vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 n> tie_lo_esd $end
-$var wire 1 o> tie_hi_esd $end
-$var wire 1 p> in_h $end
-$var wire 1 q> in $end
-$scope module gpiov2_base $end
-$var event 1 r> event_error_vswitch5 $end
-$var event 1 s> event_error_vswitch4 $end
-$var event 1 t> event_error_vswitch3 $end
-$var event 1 u> event_error_vswitch2 $end
-$var event 1 v> event_error_vswitch1 $end
-$var event 1 w> event_error_vddio_q2 $end
-$var event 1 x> event_error_vddio_q1 $end
-$var event 1 y> event_error_vdda_vddioq_vswitch2 $end
-$var event 1 z> event_error_vdda3 $end
-$var event 1 {> event_error_vdda2 $end
-$var event 1 |> event_error_vdda $end
-$var event 1 }> event_error_supply_good $end
-$var event 1 ~> event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ]> analog_en $end
-$var wire 1 ^> analog_pol $end
-$var wire 1 _> analog_sel $end
-$var wire 3 !? dm [2:0] $end
-$var wire 3 "? dm_buf [2:0] $end
-$var wire 1 a> enable_h $end
-$var wire 1 b> enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 #? error_enable_vddio $end
-$var wire 1 $? error_supply_good $end
-$var wire 1 %? error_vdda $end
-$var wire 1 &? error_vdda2 $end
-$var wire 1 '? error_vdda3 $end
-$var wire 1 (? error_vdda_vddioq_vswitch2 $end
-$var wire 1 )? error_vddio_q1 $end
-$var wire 1 *? error_vddio_q2 $end
-$var wire 1 +? error_vswitch1 $end
-$var wire 1 ,? error_vswitch2 $end
-$var wire 1 -? error_vswitch3 $end
-$var wire 1 .? error_vswitch4 $end
-$var wire 1 /? error_vswitch5 $end
-$var wire 1 0? functional_mode_amux $end
-$var wire 1 c> hld_h_n $end
-$var wire 1 1? hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 2? hld_ovr_buf $end
-$var wire 1 d> ib_mode_sel $end
-$var wire 1 3? ib_mode_sel_buf $end
-$var wire 1 e> inp_dis $end
-$var wire 1 4? inp_dis_buf $end
-$var wire 1 5? invalid_controls_amux $end
-$var wire 1 f> oe_n $end
-$var wire 1 6? oe_n_buf $end
-$var wire 1 g> out $end
-$var wire 1 7? out_buf $end
-$var wire 1 h> pad $end
-$var wire 1 i> pad_a_esd_0_h $end
-$var wire 1 j> pad_a_esd_1_h $end
-$var wire 1 k> pad_a_noesd_h $end
-$var wire 1 8? pad_tristate $end
-$var wire 1 9? pwr_good_active_mode $end
-$var wire 1 :? pwr_good_active_mode_vdda $end
-$var wire 1 ;? pwr_good_amux $end
-$var wire 1 <? pwr_good_analog_en_vdda $end
-$var wire 1 =? pwr_good_analog_en_vddio_q $end
-$var wire 1 >? pwr_good_analog_en_vswitch $end
-$var wire 1 ?? pwr_good_hold_mode $end
-$var wire 1 @? pwr_good_hold_mode_vdda $end
-$var wire 1 A? pwr_good_hold_ovr_mode $end
-$var wire 1 B? pwr_good_inpbuff_hv $end
-$var wire 1 C? pwr_good_inpbuff_lv $end
-$var wire 1 D? pwr_good_output_driver $end
-$var wire 1 l> slow $end
-$var wire 1 E? slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 m> vtrip_sel $end
-$var wire 1 F? vtrip_sel_buf $end
-$var wire 1 G? x_on_analog_en_vdda $end
-$var wire 1 H? x_on_analog_en_vddio_q $end
-$var wire 1 I? x_on_analog_en_vswitch $end
-$var wire 1 J? x_on_in_hv $end
-$var wire 1 K? x_on_in_lv $end
-$var wire 1 L? x_on_pad $end
-$var wire 1 M? zero_on_analog_en_vdda $end
-$var wire 1 N? zero_on_analog_en_vddio_q $end
-$var wire 1 O? zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 n> tie_lo_esd $end
-$var wire 1 o> tie_hi_esd $end
-$var wire 1 P? pwr_good_amux_vccd $end
-$var wire 1 p> in_h $end
-$var wire 1 q> in $end
-$var wire 1 Q? enable_pad_vssio_q $end
-$var wire 1 R? enable_pad_vddio_q $end
-$var wire 1 S? enable_pad_amuxbus_b $end
-$var wire 1 T? enable_pad_amuxbus_a $end
-$var wire 1 U? disable_inp_buff_lv $end
-$var wire 1 V? disable_inp_buff $end
-$var wire 3 W? amux_select [2:0] $end
-$var reg 1 X? analog_en_final $end
-$var reg 1 Y? analog_en_vdda $end
-$var reg 1 Z? analog_en_vddio_q $end
-$var reg 1 [? analog_en_vswitch $end
-$var reg 1 \? dis_err_msgs $end
-$var reg 3 ]? dm_final [2:0] $end
-$var reg 1 ^? hld_ovr_final $end
-$var reg 1 _? ib_mode_sel_final $end
-$var reg 1 `? inp_dis_final $end
-$var reg 1 a? notifier_dm $end
-$var reg 1 b? notifier_enable_h $end
-$var reg 1 c? notifier_hld_ovr $end
-$var reg 1 d? notifier_ib_mode_sel $end
-$var reg 1 e? notifier_inp_dis $end
-$var reg 1 f? notifier_oe_n $end
-$var reg 1 g? notifier_out $end
-$var reg 1 h? notifier_slow $end
-$var reg 1 i? notifier_vtrip_sel $end
-$var reg 1 j? oe_n_final $end
-$var reg 1 k? out_final $end
-$var reg 1 l? slow_final $end
-$var reg 1 m? vtrip_sel_final $end
-$var integer 32 n? msg_count_pad [31:0] $end
-$var integer 32 o? msg_count_pad1 [31:0] $end
-$var integer 32 p? msg_count_pad10 [31:0] $end
-$var integer 32 q? msg_count_pad11 [31:0] $end
-$var integer 32 r? msg_count_pad12 [31:0] $end
-$var integer 32 s? msg_count_pad2 [31:0] $end
-$var integer 32 t? msg_count_pad3 [31:0] $end
-$var integer 32 u? msg_count_pad4 [31:0] $end
-$var integer 32 v? msg_count_pad5 [31:0] $end
-$var integer 32 w? msg_count_pad6 [31:0] $end
-$var integer 32 x? msg_count_pad7 [31:0] $end
-$var integer 32 y? msg_count_pad8 [31:0] $end
-$var integer 32 z? msg_count_pad9 [31:0] $end
-$var integer 32 {? slow_0_delay [31:0] $end
-$var integer 32 |? slow_1_delay [31:0] $end
-$var integer 32 }? slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[3] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ~? analog_en $end
-$var wire 1 !@ analog_pol $end
-$var wire 1 "@ analog_sel $end
-$var wire 3 #@ dm [2:0] $end
-$var wire 1 $@ enable_h $end
-$var wire 1 %@ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 &@ hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 '@ ib_mode_sel $end
-$var wire 1 (@ inp_dis $end
-$var wire 1 )@ oe_n $end
-$var wire 1 *@ out $end
-$var wire 1 +@ pad $end
-$var wire 1 ,@ pad_a_esd_0_h $end
-$var wire 1 -@ pad_a_esd_1_h $end
-$var wire 1 .@ pad_a_noesd_h $end
-$var wire 1 /@ slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 0@ vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 1@ tie_lo_esd $end
-$var wire 1 2@ tie_hi_esd $end
-$var wire 1 3@ in_h $end
-$var wire 1 4@ in $end
-$scope module gpiov2_base $end
-$var event 1 5@ event_error_vswitch5 $end
-$var event 1 6@ event_error_vswitch4 $end
-$var event 1 7@ event_error_vswitch3 $end
-$var event 1 8@ event_error_vswitch2 $end
-$var event 1 9@ event_error_vswitch1 $end
-$var event 1 :@ event_error_vddio_q2 $end
-$var event 1 ;@ event_error_vddio_q1 $end
-$var event 1 <@ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 =@ event_error_vdda3 $end
-$var event 1 >@ event_error_vdda2 $end
-$var event 1 ?@ event_error_vdda $end
-$var event 1 @@ event_error_supply_good $end
-$var event 1 A@ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ~? analog_en $end
-$var wire 1 !@ analog_pol $end
-$var wire 1 "@ analog_sel $end
-$var wire 3 B@ dm [2:0] $end
-$var wire 3 C@ dm_buf [2:0] $end
-$var wire 1 $@ enable_h $end
-$var wire 1 %@ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 D@ error_enable_vddio $end
-$var wire 1 E@ error_supply_good $end
-$var wire 1 F@ error_vdda $end
-$var wire 1 G@ error_vdda2 $end
-$var wire 1 H@ error_vdda3 $end
-$var wire 1 I@ error_vdda_vddioq_vswitch2 $end
-$var wire 1 J@ error_vddio_q1 $end
-$var wire 1 K@ error_vddio_q2 $end
-$var wire 1 L@ error_vswitch1 $end
-$var wire 1 M@ error_vswitch2 $end
-$var wire 1 N@ error_vswitch3 $end
-$var wire 1 O@ error_vswitch4 $end
-$var wire 1 P@ error_vswitch5 $end
-$var wire 1 Q@ functional_mode_amux $end
-$var wire 1 &@ hld_h_n $end
-$var wire 1 R@ hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 S@ hld_ovr_buf $end
-$var wire 1 '@ ib_mode_sel $end
-$var wire 1 T@ ib_mode_sel_buf $end
-$var wire 1 (@ inp_dis $end
-$var wire 1 U@ inp_dis_buf $end
-$var wire 1 V@ invalid_controls_amux $end
-$var wire 1 )@ oe_n $end
-$var wire 1 W@ oe_n_buf $end
-$var wire 1 *@ out $end
-$var wire 1 X@ out_buf $end
-$var wire 1 +@ pad $end
-$var wire 1 ,@ pad_a_esd_0_h $end
-$var wire 1 -@ pad_a_esd_1_h $end
-$var wire 1 .@ pad_a_noesd_h $end
-$var wire 1 Y@ pad_tristate $end
-$var wire 1 Z@ pwr_good_active_mode $end
-$var wire 1 [@ pwr_good_active_mode_vdda $end
-$var wire 1 \@ pwr_good_amux $end
-$var wire 1 ]@ pwr_good_analog_en_vdda $end
-$var wire 1 ^@ pwr_good_analog_en_vddio_q $end
-$var wire 1 _@ pwr_good_analog_en_vswitch $end
-$var wire 1 `@ pwr_good_hold_mode $end
-$var wire 1 a@ pwr_good_hold_mode_vdda $end
-$var wire 1 b@ pwr_good_hold_ovr_mode $end
-$var wire 1 c@ pwr_good_inpbuff_hv $end
-$var wire 1 d@ pwr_good_inpbuff_lv $end
-$var wire 1 e@ pwr_good_output_driver $end
-$var wire 1 /@ slow $end
-$var wire 1 f@ slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 0@ vtrip_sel $end
-$var wire 1 g@ vtrip_sel_buf $end
-$var wire 1 h@ x_on_analog_en_vdda $end
-$var wire 1 i@ x_on_analog_en_vddio_q $end
-$var wire 1 j@ x_on_analog_en_vswitch $end
-$var wire 1 k@ x_on_in_hv $end
-$var wire 1 l@ x_on_in_lv $end
-$var wire 1 m@ x_on_pad $end
-$var wire 1 n@ zero_on_analog_en_vdda $end
-$var wire 1 o@ zero_on_analog_en_vddio_q $end
-$var wire 1 p@ zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 1@ tie_lo_esd $end
-$var wire 1 2@ tie_hi_esd $end
-$var wire 1 q@ pwr_good_amux_vccd $end
-$var wire 1 3@ in_h $end
-$var wire 1 4@ in $end
-$var wire 1 r@ enable_pad_vssio_q $end
-$var wire 1 s@ enable_pad_vddio_q $end
-$var wire 1 t@ enable_pad_amuxbus_b $end
-$var wire 1 u@ enable_pad_amuxbus_a $end
-$var wire 1 v@ disable_inp_buff_lv $end
-$var wire 1 w@ disable_inp_buff $end
-$var wire 3 x@ amux_select [2:0] $end
-$var reg 1 y@ analog_en_final $end
-$var reg 1 z@ analog_en_vdda $end
-$var reg 1 {@ analog_en_vddio_q $end
-$var reg 1 |@ analog_en_vswitch $end
-$var reg 1 }@ dis_err_msgs $end
-$var reg 3 ~@ dm_final [2:0] $end
-$var reg 1 !A hld_ovr_final $end
-$var reg 1 "A ib_mode_sel_final $end
-$var reg 1 #A inp_dis_final $end
-$var reg 1 $A notifier_dm $end
-$var reg 1 %A notifier_enable_h $end
-$var reg 1 &A notifier_hld_ovr $end
-$var reg 1 'A notifier_ib_mode_sel $end
-$var reg 1 (A notifier_inp_dis $end
-$var reg 1 )A notifier_oe_n $end
-$var reg 1 *A notifier_out $end
-$var reg 1 +A notifier_slow $end
-$var reg 1 ,A notifier_vtrip_sel $end
-$var reg 1 -A oe_n_final $end
-$var reg 1 .A out_final $end
-$var reg 1 /A slow_final $end
-$var reg 1 0A vtrip_sel_final $end
-$var integer 32 1A msg_count_pad [31:0] $end
-$var integer 32 2A msg_count_pad1 [31:0] $end
-$var integer 32 3A msg_count_pad10 [31:0] $end
-$var integer 32 4A msg_count_pad11 [31:0] $end
-$var integer 32 5A msg_count_pad12 [31:0] $end
-$var integer 32 6A msg_count_pad2 [31:0] $end
-$var integer 32 7A msg_count_pad3 [31:0] $end
-$var integer 32 8A msg_count_pad4 [31:0] $end
-$var integer 32 9A msg_count_pad5 [31:0] $end
-$var integer 32 :A msg_count_pad6 [31:0] $end
-$var integer 32 ;A msg_count_pad7 [31:0] $end
-$var integer 32 <A msg_count_pad8 [31:0] $end
-$var integer 32 =A msg_count_pad9 [31:0] $end
-$var integer 32 >A slow_0_delay [31:0] $end
-$var integer 32 ?A slow_1_delay [31:0] $end
-$var integer 32 @A slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[4] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 AA analog_en $end
-$var wire 1 BA analog_pol $end
-$var wire 1 CA analog_sel $end
-$var wire 3 DA dm [2:0] $end
-$var wire 1 EA enable_h $end
-$var wire 1 FA enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 GA hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 HA ib_mode_sel $end
-$var wire 1 IA inp_dis $end
-$var wire 1 JA oe_n $end
-$var wire 1 KA out $end
-$var wire 1 LA pad $end
-$var wire 1 MA pad_a_esd_0_h $end
-$var wire 1 NA pad_a_esd_1_h $end
-$var wire 1 OA pad_a_noesd_h $end
-$var wire 1 PA slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 QA vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 RA tie_lo_esd $end
-$var wire 1 SA tie_hi_esd $end
-$var wire 1 TA in_h $end
-$var wire 1 UA in $end
-$scope module gpiov2_base $end
-$var event 1 VA event_error_vswitch5 $end
-$var event 1 WA event_error_vswitch4 $end
-$var event 1 XA event_error_vswitch3 $end
-$var event 1 YA event_error_vswitch2 $end
-$var event 1 ZA event_error_vswitch1 $end
-$var event 1 [A event_error_vddio_q2 $end
-$var event 1 \A event_error_vddio_q1 $end
-$var event 1 ]A event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ^A event_error_vdda3 $end
-$var event 1 _A event_error_vdda2 $end
-$var event 1 `A event_error_vdda $end
-$var event 1 aA event_error_supply_good $end
-$var event 1 bA event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 AA analog_en $end
-$var wire 1 BA analog_pol $end
-$var wire 1 CA analog_sel $end
-$var wire 3 cA dm [2:0] $end
-$var wire 3 dA dm_buf [2:0] $end
-$var wire 1 EA enable_h $end
-$var wire 1 FA enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 eA error_enable_vddio $end
-$var wire 1 fA error_supply_good $end
-$var wire 1 gA error_vdda $end
-$var wire 1 hA error_vdda2 $end
-$var wire 1 iA error_vdda3 $end
-$var wire 1 jA error_vdda_vddioq_vswitch2 $end
-$var wire 1 kA error_vddio_q1 $end
-$var wire 1 lA error_vddio_q2 $end
-$var wire 1 mA error_vswitch1 $end
-$var wire 1 nA error_vswitch2 $end
-$var wire 1 oA error_vswitch3 $end
-$var wire 1 pA error_vswitch4 $end
-$var wire 1 qA error_vswitch5 $end
-$var wire 1 rA functional_mode_amux $end
-$var wire 1 GA hld_h_n $end
-$var wire 1 sA hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 tA hld_ovr_buf $end
-$var wire 1 HA ib_mode_sel $end
-$var wire 1 uA ib_mode_sel_buf $end
-$var wire 1 IA inp_dis $end
-$var wire 1 vA inp_dis_buf $end
-$var wire 1 wA invalid_controls_amux $end
-$var wire 1 JA oe_n $end
-$var wire 1 xA oe_n_buf $end
-$var wire 1 KA out $end
-$var wire 1 yA out_buf $end
-$var wire 1 LA pad $end
-$var wire 1 MA pad_a_esd_0_h $end
-$var wire 1 NA pad_a_esd_1_h $end
-$var wire 1 OA pad_a_noesd_h $end
-$var wire 1 zA pad_tristate $end
-$var wire 1 {A pwr_good_active_mode $end
-$var wire 1 |A pwr_good_active_mode_vdda $end
-$var wire 1 }A pwr_good_amux $end
-$var wire 1 ~A pwr_good_analog_en_vdda $end
-$var wire 1 !B pwr_good_analog_en_vddio_q $end
-$var wire 1 "B pwr_good_analog_en_vswitch $end
-$var wire 1 #B pwr_good_hold_mode $end
-$var wire 1 $B pwr_good_hold_mode_vdda $end
-$var wire 1 %B pwr_good_hold_ovr_mode $end
-$var wire 1 &B pwr_good_inpbuff_hv $end
-$var wire 1 'B pwr_good_inpbuff_lv $end
-$var wire 1 (B pwr_good_output_driver $end
-$var wire 1 PA slow $end
-$var wire 1 )B slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 QA vtrip_sel $end
-$var wire 1 *B vtrip_sel_buf $end
-$var wire 1 +B x_on_analog_en_vdda $end
-$var wire 1 ,B x_on_analog_en_vddio_q $end
-$var wire 1 -B x_on_analog_en_vswitch $end
-$var wire 1 .B x_on_in_hv $end
-$var wire 1 /B x_on_in_lv $end
-$var wire 1 0B x_on_pad $end
-$var wire 1 1B zero_on_analog_en_vdda $end
-$var wire 1 2B zero_on_analog_en_vddio_q $end
-$var wire 1 3B zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 RA tie_lo_esd $end
-$var wire 1 SA tie_hi_esd $end
-$var wire 1 4B pwr_good_amux_vccd $end
-$var wire 1 TA in_h $end
-$var wire 1 UA in $end
-$var wire 1 5B enable_pad_vssio_q $end
-$var wire 1 6B enable_pad_vddio_q $end
-$var wire 1 7B enable_pad_amuxbus_b $end
-$var wire 1 8B enable_pad_amuxbus_a $end
-$var wire 1 9B disable_inp_buff_lv $end
-$var wire 1 :B disable_inp_buff $end
-$var wire 3 ;B amux_select [2:0] $end
-$var reg 1 <B analog_en_final $end
-$var reg 1 =B analog_en_vdda $end
-$var reg 1 >B analog_en_vddio_q $end
-$var reg 1 ?B analog_en_vswitch $end
-$var reg 1 @B dis_err_msgs $end
-$var reg 3 AB dm_final [2:0] $end
-$var reg 1 BB hld_ovr_final $end
-$var reg 1 CB ib_mode_sel_final $end
-$var reg 1 DB inp_dis_final $end
-$var reg 1 EB notifier_dm $end
-$var reg 1 FB notifier_enable_h $end
-$var reg 1 GB notifier_hld_ovr $end
-$var reg 1 HB notifier_ib_mode_sel $end
-$var reg 1 IB notifier_inp_dis $end
-$var reg 1 JB notifier_oe_n $end
-$var reg 1 KB notifier_out $end
-$var reg 1 LB notifier_slow $end
-$var reg 1 MB notifier_vtrip_sel $end
-$var reg 1 NB oe_n_final $end
-$var reg 1 OB out_final $end
-$var reg 1 PB slow_final $end
-$var reg 1 QB vtrip_sel_final $end
-$var integer 32 RB msg_count_pad [31:0] $end
-$var integer 32 SB msg_count_pad1 [31:0] $end
-$var integer 32 TB msg_count_pad10 [31:0] $end
-$var integer 32 UB msg_count_pad11 [31:0] $end
-$var integer 32 VB msg_count_pad12 [31:0] $end
-$var integer 32 WB msg_count_pad2 [31:0] $end
-$var integer 32 XB msg_count_pad3 [31:0] $end
-$var integer 32 YB msg_count_pad4 [31:0] $end
-$var integer 32 ZB msg_count_pad5 [31:0] $end
-$var integer 32 [B msg_count_pad6 [31:0] $end
-$var integer 32 \B msg_count_pad7 [31:0] $end
-$var integer 32 ]B msg_count_pad8 [31:0] $end
-$var integer 32 ^B msg_count_pad9 [31:0] $end
-$var integer 32 _B slow_0_delay [31:0] $end
-$var integer 32 `B slow_1_delay [31:0] $end
-$var integer 32 aB slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[5] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 bB analog_en $end
-$var wire 1 cB analog_pol $end
-$var wire 1 dB analog_sel $end
-$var wire 3 eB dm [2:0] $end
-$var wire 1 fB enable_h $end
-$var wire 1 gB enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 hB hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 iB ib_mode_sel $end
-$var wire 1 jB inp_dis $end
-$var wire 1 kB oe_n $end
-$var wire 1 lB out $end
-$var wire 1 mB pad $end
-$var wire 1 nB pad_a_esd_0_h $end
-$var wire 1 oB pad_a_esd_1_h $end
-$var wire 1 pB pad_a_noesd_h $end
-$var wire 1 qB slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 rB vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 sB tie_lo_esd $end
-$var wire 1 tB tie_hi_esd $end
-$var wire 1 uB in_h $end
-$var wire 1 vB in $end
-$scope module gpiov2_base $end
-$var event 1 wB event_error_vswitch5 $end
-$var event 1 xB event_error_vswitch4 $end
-$var event 1 yB event_error_vswitch3 $end
-$var event 1 zB event_error_vswitch2 $end
-$var event 1 {B event_error_vswitch1 $end
-$var event 1 |B event_error_vddio_q2 $end
-$var event 1 }B event_error_vddio_q1 $end
-$var event 1 ~B event_error_vdda_vddioq_vswitch2 $end
-$var event 1 !C event_error_vdda3 $end
-$var event 1 "C event_error_vdda2 $end
-$var event 1 #C event_error_vdda $end
-$var event 1 $C event_error_supply_good $end
-$var event 1 %C event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 bB analog_en $end
-$var wire 1 cB analog_pol $end
-$var wire 1 dB analog_sel $end
-$var wire 3 &C dm [2:0] $end
-$var wire 3 'C dm_buf [2:0] $end
-$var wire 1 fB enable_h $end
-$var wire 1 gB enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 (C error_enable_vddio $end
-$var wire 1 )C error_supply_good $end
-$var wire 1 *C error_vdda $end
-$var wire 1 +C error_vdda2 $end
-$var wire 1 ,C error_vdda3 $end
-$var wire 1 -C error_vdda_vddioq_vswitch2 $end
-$var wire 1 .C error_vddio_q1 $end
-$var wire 1 /C error_vddio_q2 $end
-$var wire 1 0C error_vswitch1 $end
-$var wire 1 1C error_vswitch2 $end
-$var wire 1 2C error_vswitch3 $end
-$var wire 1 3C error_vswitch4 $end
-$var wire 1 4C error_vswitch5 $end
-$var wire 1 5C functional_mode_amux $end
-$var wire 1 hB hld_h_n $end
-$var wire 1 6C hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 7C hld_ovr_buf $end
-$var wire 1 iB ib_mode_sel $end
-$var wire 1 8C ib_mode_sel_buf $end
-$var wire 1 jB inp_dis $end
-$var wire 1 9C inp_dis_buf $end
-$var wire 1 :C invalid_controls_amux $end
-$var wire 1 kB oe_n $end
-$var wire 1 ;C oe_n_buf $end
-$var wire 1 lB out $end
-$var wire 1 <C out_buf $end
-$var wire 1 mB pad $end
-$var wire 1 nB pad_a_esd_0_h $end
-$var wire 1 oB pad_a_esd_1_h $end
-$var wire 1 pB pad_a_noesd_h $end
-$var wire 1 =C pad_tristate $end
-$var wire 1 >C pwr_good_active_mode $end
-$var wire 1 ?C pwr_good_active_mode_vdda $end
-$var wire 1 @C pwr_good_amux $end
-$var wire 1 AC pwr_good_analog_en_vdda $end
-$var wire 1 BC pwr_good_analog_en_vddio_q $end
-$var wire 1 CC pwr_good_analog_en_vswitch $end
-$var wire 1 DC pwr_good_hold_mode $end
-$var wire 1 EC pwr_good_hold_mode_vdda $end
-$var wire 1 FC pwr_good_hold_ovr_mode $end
-$var wire 1 GC pwr_good_inpbuff_hv $end
-$var wire 1 HC pwr_good_inpbuff_lv $end
-$var wire 1 IC pwr_good_output_driver $end
-$var wire 1 qB slow $end
-$var wire 1 JC slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 rB vtrip_sel $end
-$var wire 1 KC vtrip_sel_buf $end
-$var wire 1 LC x_on_analog_en_vdda $end
-$var wire 1 MC x_on_analog_en_vddio_q $end
-$var wire 1 NC x_on_analog_en_vswitch $end
-$var wire 1 OC x_on_in_hv $end
-$var wire 1 PC x_on_in_lv $end
-$var wire 1 QC x_on_pad $end
-$var wire 1 RC zero_on_analog_en_vdda $end
-$var wire 1 SC zero_on_analog_en_vddio_q $end
-$var wire 1 TC zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 sB tie_lo_esd $end
-$var wire 1 tB tie_hi_esd $end
-$var wire 1 UC pwr_good_amux_vccd $end
-$var wire 1 uB in_h $end
-$var wire 1 vB in $end
-$var wire 1 VC enable_pad_vssio_q $end
-$var wire 1 WC enable_pad_vddio_q $end
-$var wire 1 XC enable_pad_amuxbus_b $end
-$var wire 1 YC enable_pad_amuxbus_a $end
-$var wire 1 ZC disable_inp_buff_lv $end
-$var wire 1 [C disable_inp_buff $end
-$var wire 3 \C amux_select [2:0] $end
-$var reg 1 ]C analog_en_final $end
-$var reg 1 ^C analog_en_vdda $end
-$var reg 1 _C analog_en_vddio_q $end
-$var reg 1 `C analog_en_vswitch $end
-$var reg 1 aC dis_err_msgs $end
-$var reg 3 bC dm_final [2:0] $end
-$var reg 1 cC hld_ovr_final $end
-$var reg 1 dC ib_mode_sel_final $end
-$var reg 1 eC inp_dis_final $end
-$var reg 1 fC notifier_dm $end
-$var reg 1 gC notifier_enable_h $end
-$var reg 1 hC notifier_hld_ovr $end
-$var reg 1 iC notifier_ib_mode_sel $end
-$var reg 1 jC notifier_inp_dis $end
-$var reg 1 kC notifier_oe_n $end
-$var reg 1 lC notifier_out $end
-$var reg 1 mC notifier_slow $end
-$var reg 1 nC notifier_vtrip_sel $end
-$var reg 1 oC oe_n_final $end
-$var reg 1 pC out_final $end
-$var reg 1 qC slow_final $end
-$var reg 1 rC vtrip_sel_final $end
-$var integer 32 sC msg_count_pad [31:0] $end
-$var integer 32 tC msg_count_pad1 [31:0] $end
-$var integer 32 uC msg_count_pad10 [31:0] $end
-$var integer 32 vC msg_count_pad11 [31:0] $end
-$var integer 32 wC msg_count_pad12 [31:0] $end
-$var integer 32 xC msg_count_pad2 [31:0] $end
-$var integer 32 yC msg_count_pad3 [31:0] $end
-$var integer 32 zC msg_count_pad4 [31:0] $end
-$var integer 32 {C msg_count_pad5 [31:0] $end
-$var integer 32 |C msg_count_pad6 [31:0] $end
-$var integer 32 }C msg_count_pad7 [31:0] $end
-$var integer 32 ~C msg_count_pad8 [31:0] $end
-$var integer 32 !D msg_count_pad9 [31:0] $end
-$var integer 32 "D slow_0_delay [31:0] $end
-$var integer 32 #D slow_1_delay [31:0] $end
-$var integer 32 $D slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[6] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 %D analog_en $end
-$var wire 1 &D analog_pol $end
-$var wire 1 'D analog_sel $end
-$var wire 3 (D dm [2:0] $end
-$var wire 1 )D enable_h $end
-$var wire 1 *D enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 +D hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ,D ib_mode_sel $end
-$var wire 1 -D inp_dis $end
-$var wire 1 .D oe_n $end
-$var wire 1 /D out $end
-$var wire 1 0D pad $end
-$var wire 1 1D pad_a_esd_0_h $end
-$var wire 1 2D pad_a_esd_1_h $end
-$var wire 1 3D pad_a_noesd_h $end
-$var wire 1 4D slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 5D vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 6D tie_lo_esd $end
-$var wire 1 7D tie_hi_esd $end
-$var wire 1 8D in_h $end
-$var wire 1 9D in $end
-$scope module gpiov2_base $end
-$var event 1 :D event_error_vswitch5 $end
-$var event 1 ;D event_error_vswitch4 $end
-$var event 1 <D event_error_vswitch3 $end
-$var event 1 =D event_error_vswitch2 $end
-$var event 1 >D event_error_vswitch1 $end
-$var event 1 ?D event_error_vddio_q2 $end
-$var event 1 @D event_error_vddio_q1 $end
-$var event 1 AD event_error_vdda_vddioq_vswitch2 $end
-$var event 1 BD event_error_vdda3 $end
-$var event 1 CD event_error_vdda2 $end
-$var event 1 DD event_error_vdda $end
-$var event 1 ED event_error_supply_good $end
-$var event 1 FD event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 %D analog_en $end
-$var wire 1 &D analog_pol $end
-$var wire 1 'D analog_sel $end
-$var wire 3 GD dm [2:0] $end
-$var wire 3 HD dm_buf [2:0] $end
-$var wire 1 )D enable_h $end
-$var wire 1 *D enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ID error_enable_vddio $end
-$var wire 1 JD error_supply_good $end
-$var wire 1 KD error_vdda $end
-$var wire 1 LD error_vdda2 $end
-$var wire 1 MD error_vdda3 $end
-$var wire 1 ND error_vdda_vddioq_vswitch2 $end
-$var wire 1 OD error_vddio_q1 $end
-$var wire 1 PD error_vddio_q2 $end
-$var wire 1 QD error_vswitch1 $end
-$var wire 1 RD error_vswitch2 $end
-$var wire 1 SD error_vswitch3 $end
-$var wire 1 TD error_vswitch4 $end
-$var wire 1 UD error_vswitch5 $end
-$var wire 1 VD functional_mode_amux $end
-$var wire 1 +D hld_h_n $end
-$var wire 1 WD hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 XD hld_ovr_buf $end
-$var wire 1 ,D ib_mode_sel $end
-$var wire 1 YD ib_mode_sel_buf $end
-$var wire 1 -D inp_dis $end
-$var wire 1 ZD inp_dis_buf $end
-$var wire 1 [D invalid_controls_amux $end
-$var wire 1 .D oe_n $end
-$var wire 1 \D oe_n_buf $end
-$var wire 1 /D out $end
-$var wire 1 ]D out_buf $end
-$var wire 1 0D pad $end
-$var wire 1 1D pad_a_esd_0_h $end
-$var wire 1 2D pad_a_esd_1_h $end
-$var wire 1 3D pad_a_noesd_h $end
-$var wire 1 ^D pad_tristate $end
-$var wire 1 _D pwr_good_active_mode $end
-$var wire 1 `D pwr_good_active_mode_vdda $end
-$var wire 1 aD pwr_good_amux $end
-$var wire 1 bD pwr_good_analog_en_vdda $end
-$var wire 1 cD pwr_good_analog_en_vddio_q $end
-$var wire 1 dD pwr_good_analog_en_vswitch $end
-$var wire 1 eD pwr_good_hold_mode $end
-$var wire 1 fD pwr_good_hold_mode_vdda $end
-$var wire 1 gD pwr_good_hold_ovr_mode $end
-$var wire 1 hD pwr_good_inpbuff_hv $end
-$var wire 1 iD pwr_good_inpbuff_lv $end
-$var wire 1 jD pwr_good_output_driver $end
-$var wire 1 4D slow $end
-$var wire 1 kD slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 5D vtrip_sel $end
-$var wire 1 lD vtrip_sel_buf $end
-$var wire 1 mD x_on_analog_en_vdda $end
-$var wire 1 nD x_on_analog_en_vddio_q $end
-$var wire 1 oD x_on_analog_en_vswitch $end
-$var wire 1 pD x_on_in_hv $end
-$var wire 1 qD x_on_in_lv $end
-$var wire 1 rD x_on_pad $end
-$var wire 1 sD zero_on_analog_en_vdda $end
-$var wire 1 tD zero_on_analog_en_vddio_q $end
-$var wire 1 uD zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 6D tie_lo_esd $end
-$var wire 1 7D tie_hi_esd $end
-$var wire 1 vD pwr_good_amux_vccd $end
-$var wire 1 8D in_h $end
-$var wire 1 9D in $end
-$var wire 1 wD enable_pad_vssio_q $end
-$var wire 1 xD enable_pad_vddio_q $end
-$var wire 1 yD enable_pad_amuxbus_b $end
-$var wire 1 zD enable_pad_amuxbus_a $end
-$var wire 1 {D disable_inp_buff_lv $end
-$var wire 1 |D disable_inp_buff $end
-$var wire 3 }D amux_select [2:0] $end
-$var reg 1 ~D analog_en_final $end
-$var reg 1 !E analog_en_vdda $end
-$var reg 1 "E analog_en_vddio_q $end
-$var reg 1 #E analog_en_vswitch $end
-$var reg 1 $E dis_err_msgs $end
-$var reg 3 %E dm_final [2:0] $end
-$var reg 1 &E hld_ovr_final $end
-$var reg 1 'E ib_mode_sel_final $end
-$var reg 1 (E inp_dis_final $end
-$var reg 1 )E notifier_dm $end
-$var reg 1 *E notifier_enable_h $end
-$var reg 1 +E notifier_hld_ovr $end
-$var reg 1 ,E notifier_ib_mode_sel $end
-$var reg 1 -E notifier_inp_dis $end
-$var reg 1 .E notifier_oe_n $end
-$var reg 1 /E notifier_out $end
-$var reg 1 0E notifier_slow $end
-$var reg 1 1E notifier_vtrip_sel $end
-$var reg 1 2E oe_n_final $end
-$var reg 1 3E out_final $end
-$var reg 1 4E slow_final $end
-$var reg 1 5E vtrip_sel_final $end
-$var integer 32 6E msg_count_pad [31:0] $end
-$var integer 32 7E msg_count_pad1 [31:0] $end
-$var integer 32 8E msg_count_pad10 [31:0] $end
-$var integer 32 9E msg_count_pad11 [31:0] $end
-$var integer 32 :E msg_count_pad12 [31:0] $end
-$var integer 32 ;E msg_count_pad2 [31:0] $end
-$var integer 32 <E msg_count_pad3 [31:0] $end
-$var integer 32 =E msg_count_pad4 [31:0] $end
-$var integer 32 >E msg_count_pad5 [31:0] $end
-$var integer 32 ?E msg_count_pad6 [31:0] $end
-$var integer 32 @E msg_count_pad7 [31:0] $end
-$var integer 32 AE msg_count_pad8 [31:0] $end
-$var integer 32 BE msg_count_pad9 [31:0] $end
-$var integer 32 CE slow_0_delay [31:0] $end
-$var integer 32 DE slow_1_delay [31:0] $end
-$var integer 32 EE slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[7] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 FE analog_en $end
-$var wire 1 GE analog_pol $end
-$var wire 1 HE analog_sel $end
-$var wire 3 IE dm [2:0] $end
-$var wire 1 JE enable_h $end
-$var wire 1 KE enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 LE hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ME ib_mode_sel $end
-$var wire 1 NE inp_dis $end
-$var wire 1 OE oe_n $end
-$var wire 1 PE out $end
-$var wire 1 QE pad $end
-$var wire 1 RE pad_a_esd_0_h $end
-$var wire 1 SE pad_a_esd_1_h $end
-$var wire 1 TE pad_a_noesd_h $end
-$var wire 1 UE slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 VE vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 WE tie_lo_esd $end
-$var wire 1 XE tie_hi_esd $end
-$var wire 1 YE in_h $end
-$var wire 1 ZE in $end
-$scope module gpiov2_base $end
-$var event 1 [E event_error_vswitch5 $end
-$var event 1 \E event_error_vswitch4 $end
-$var event 1 ]E event_error_vswitch3 $end
-$var event 1 ^E event_error_vswitch2 $end
-$var event 1 _E event_error_vswitch1 $end
-$var event 1 `E event_error_vddio_q2 $end
-$var event 1 aE event_error_vddio_q1 $end
-$var event 1 bE event_error_vdda_vddioq_vswitch2 $end
-$var event 1 cE event_error_vdda3 $end
-$var event 1 dE event_error_vdda2 $end
-$var event 1 eE event_error_vdda $end
-$var event 1 fE event_error_supply_good $end
-$var event 1 gE event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 FE analog_en $end
-$var wire 1 GE analog_pol $end
-$var wire 1 HE analog_sel $end
-$var wire 3 hE dm [2:0] $end
-$var wire 3 iE dm_buf [2:0] $end
-$var wire 1 JE enable_h $end
-$var wire 1 KE enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 jE error_enable_vddio $end
-$var wire 1 kE error_supply_good $end
-$var wire 1 lE error_vdda $end
-$var wire 1 mE error_vdda2 $end
-$var wire 1 nE error_vdda3 $end
-$var wire 1 oE error_vdda_vddioq_vswitch2 $end
-$var wire 1 pE error_vddio_q1 $end
-$var wire 1 qE error_vddio_q2 $end
-$var wire 1 rE error_vswitch1 $end
-$var wire 1 sE error_vswitch2 $end
-$var wire 1 tE error_vswitch3 $end
-$var wire 1 uE error_vswitch4 $end
-$var wire 1 vE error_vswitch5 $end
-$var wire 1 wE functional_mode_amux $end
-$var wire 1 LE hld_h_n $end
-$var wire 1 xE hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 yE hld_ovr_buf $end
-$var wire 1 ME ib_mode_sel $end
-$var wire 1 zE ib_mode_sel_buf $end
-$var wire 1 NE inp_dis $end
-$var wire 1 {E inp_dis_buf $end
-$var wire 1 |E invalid_controls_amux $end
-$var wire 1 OE oe_n $end
-$var wire 1 }E oe_n_buf $end
-$var wire 1 PE out $end
-$var wire 1 ~E out_buf $end
-$var wire 1 QE pad $end
-$var wire 1 RE pad_a_esd_0_h $end
-$var wire 1 SE pad_a_esd_1_h $end
-$var wire 1 TE pad_a_noesd_h $end
-$var wire 1 !F pad_tristate $end
-$var wire 1 "F pwr_good_active_mode $end
-$var wire 1 #F pwr_good_active_mode_vdda $end
-$var wire 1 $F pwr_good_amux $end
-$var wire 1 %F pwr_good_analog_en_vdda $end
-$var wire 1 &F pwr_good_analog_en_vddio_q $end
-$var wire 1 'F pwr_good_analog_en_vswitch $end
-$var wire 1 (F pwr_good_hold_mode $end
-$var wire 1 )F pwr_good_hold_mode_vdda $end
-$var wire 1 *F pwr_good_hold_ovr_mode $end
-$var wire 1 +F pwr_good_inpbuff_hv $end
-$var wire 1 ,F pwr_good_inpbuff_lv $end
-$var wire 1 -F pwr_good_output_driver $end
-$var wire 1 UE slow $end
-$var wire 1 .F slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 VE vtrip_sel $end
-$var wire 1 /F vtrip_sel_buf $end
-$var wire 1 0F x_on_analog_en_vdda $end
-$var wire 1 1F x_on_analog_en_vddio_q $end
-$var wire 1 2F x_on_analog_en_vswitch $end
-$var wire 1 3F x_on_in_hv $end
-$var wire 1 4F x_on_in_lv $end
-$var wire 1 5F x_on_pad $end
-$var wire 1 6F zero_on_analog_en_vdda $end
-$var wire 1 7F zero_on_analog_en_vddio_q $end
-$var wire 1 8F zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 WE tie_lo_esd $end
-$var wire 1 XE tie_hi_esd $end
-$var wire 1 9F pwr_good_amux_vccd $end
-$var wire 1 YE in_h $end
-$var wire 1 ZE in $end
-$var wire 1 :F enable_pad_vssio_q $end
-$var wire 1 ;F enable_pad_vddio_q $end
-$var wire 1 <F enable_pad_amuxbus_b $end
-$var wire 1 =F enable_pad_amuxbus_a $end
-$var wire 1 >F disable_inp_buff_lv $end
-$var wire 1 ?F disable_inp_buff $end
-$var wire 3 @F amux_select [2:0] $end
-$var reg 1 AF analog_en_final $end
-$var reg 1 BF analog_en_vdda $end
-$var reg 1 CF analog_en_vddio_q $end
-$var reg 1 DF analog_en_vswitch $end
-$var reg 1 EF dis_err_msgs $end
-$var reg 3 FF dm_final [2:0] $end
-$var reg 1 GF hld_ovr_final $end
-$var reg 1 HF ib_mode_sel_final $end
-$var reg 1 IF inp_dis_final $end
-$var reg 1 JF notifier_dm $end
-$var reg 1 KF notifier_enable_h $end
-$var reg 1 LF notifier_hld_ovr $end
-$var reg 1 MF notifier_ib_mode_sel $end
-$var reg 1 NF notifier_inp_dis $end
-$var reg 1 OF notifier_oe_n $end
-$var reg 1 PF notifier_out $end
-$var reg 1 QF notifier_slow $end
-$var reg 1 RF notifier_vtrip_sel $end
-$var reg 1 SF oe_n_final $end
-$var reg 1 TF out_final $end
-$var reg 1 UF slow_final $end
-$var reg 1 VF vtrip_sel_final $end
-$var integer 32 WF msg_count_pad [31:0] $end
-$var integer 32 XF msg_count_pad1 [31:0] $end
-$var integer 32 YF msg_count_pad10 [31:0] $end
-$var integer 32 ZF msg_count_pad11 [31:0] $end
-$var integer 32 [F msg_count_pad12 [31:0] $end
-$var integer 32 \F msg_count_pad2 [31:0] $end
-$var integer 32 ]F msg_count_pad3 [31:0] $end
-$var integer 32 ^F msg_count_pad4 [31:0] $end
-$var integer 32 _F msg_count_pad5 [31:0] $end
-$var integer 32 `F msg_count_pad6 [31:0] $end
-$var integer 32 aF msg_count_pad7 [31:0] $end
-$var integer 32 bF msg_count_pad8 [31:0] $end
-$var integer 32 cF msg_count_pad9 [31:0] $end
-$var integer 32 dF slow_0_delay [31:0] $end
-$var integer 32 eF slow_1_delay [31:0] $end
-$var integer 32 fF slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[8] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 gF analog_en $end
-$var wire 1 hF analog_pol $end
-$var wire 1 iF analog_sel $end
-$var wire 3 jF dm [2:0] $end
-$var wire 1 kF enable_h $end
-$var wire 1 lF enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 mF hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 nF ib_mode_sel $end
-$var wire 1 oF inp_dis $end
-$var wire 1 pF oe_n $end
-$var wire 1 qF out $end
-$var wire 1 rF pad $end
-$var wire 1 sF pad_a_esd_0_h $end
-$var wire 1 tF pad_a_esd_1_h $end
-$var wire 1 uF pad_a_noesd_h $end
-$var wire 1 vF slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 wF vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 xF tie_lo_esd $end
-$var wire 1 yF tie_hi_esd $end
-$var wire 1 zF in_h $end
-$var wire 1 {F in $end
-$scope module gpiov2_base $end
-$var event 1 |F event_error_vswitch5 $end
-$var event 1 }F event_error_vswitch4 $end
-$var event 1 ~F event_error_vswitch3 $end
-$var event 1 !G event_error_vswitch2 $end
-$var event 1 "G event_error_vswitch1 $end
-$var event 1 #G event_error_vddio_q2 $end
-$var event 1 $G event_error_vddio_q1 $end
-$var event 1 %G event_error_vdda_vddioq_vswitch2 $end
-$var event 1 &G event_error_vdda3 $end
-$var event 1 'G event_error_vdda2 $end
-$var event 1 (G event_error_vdda $end
-$var event 1 )G event_error_supply_good $end
-$var event 1 *G event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 gF analog_en $end
-$var wire 1 hF analog_pol $end
-$var wire 1 iF analog_sel $end
-$var wire 3 +G dm [2:0] $end
-$var wire 3 ,G dm_buf [2:0] $end
-$var wire 1 kF enable_h $end
-$var wire 1 lF enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 -G error_enable_vddio $end
-$var wire 1 .G error_supply_good $end
-$var wire 1 /G error_vdda $end
-$var wire 1 0G error_vdda2 $end
-$var wire 1 1G error_vdda3 $end
-$var wire 1 2G error_vdda_vddioq_vswitch2 $end
-$var wire 1 3G error_vddio_q1 $end
-$var wire 1 4G error_vddio_q2 $end
-$var wire 1 5G error_vswitch1 $end
-$var wire 1 6G error_vswitch2 $end
-$var wire 1 7G error_vswitch3 $end
-$var wire 1 8G error_vswitch4 $end
-$var wire 1 9G error_vswitch5 $end
-$var wire 1 :G functional_mode_amux $end
-$var wire 1 mF hld_h_n $end
-$var wire 1 ;G hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 <G hld_ovr_buf $end
-$var wire 1 nF ib_mode_sel $end
-$var wire 1 =G ib_mode_sel_buf $end
-$var wire 1 oF inp_dis $end
-$var wire 1 >G inp_dis_buf $end
-$var wire 1 ?G invalid_controls_amux $end
-$var wire 1 pF oe_n $end
-$var wire 1 @G oe_n_buf $end
-$var wire 1 qF out $end
-$var wire 1 AG out_buf $end
-$var wire 1 rF pad $end
-$var wire 1 sF pad_a_esd_0_h $end
-$var wire 1 tF pad_a_esd_1_h $end
-$var wire 1 uF pad_a_noesd_h $end
-$var wire 1 BG pad_tristate $end
-$var wire 1 CG pwr_good_active_mode $end
-$var wire 1 DG pwr_good_active_mode_vdda $end
-$var wire 1 EG pwr_good_amux $end
-$var wire 1 FG pwr_good_analog_en_vdda $end
-$var wire 1 GG pwr_good_analog_en_vddio_q $end
-$var wire 1 HG pwr_good_analog_en_vswitch $end
-$var wire 1 IG pwr_good_hold_mode $end
-$var wire 1 JG pwr_good_hold_mode_vdda $end
-$var wire 1 KG pwr_good_hold_ovr_mode $end
-$var wire 1 LG pwr_good_inpbuff_hv $end
-$var wire 1 MG pwr_good_inpbuff_lv $end
-$var wire 1 NG pwr_good_output_driver $end
-$var wire 1 vF slow $end
-$var wire 1 OG slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 wF vtrip_sel $end
-$var wire 1 PG vtrip_sel_buf $end
-$var wire 1 QG x_on_analog_en_vdda $end
-$var wire 1 RG x_on_analog_en_vddio_q $end
-$var wire 1 SG x_on_analog_en_vswitch $end
-$var wire 1 TG x_on_in_hv $end
-$var wire 1 UG x_on_in_lv $end
-$var wire 1 VG x_on_pad $end
-$var wire 1 WG zero_on_analog_en_vdda $end
-$var wire 1 XG zero_on_analog_en_vddio_q $end
-$var wire 1 YG zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 xF tie_lo_esd $end
-$var wire 1 yF tie_hi_esd $end
-$var wire 1 ZG pwr_good_amux_vccd $end
-$var wire 1 zF in_h $end
-$var wire 1 {F in $end
-$var wire 1 [G enable_pad_vssio_q $end
-$var wire 1 \G enable_pad_vddio_q $end
-$var wire 1 ]G enable_pad_amuxbus_b $end
-$var wire 1 ^G enable_pad_amuxbus_a $end
-$var wire 1 _G disable_inp_buff_lv $end
-$var wire 1 `G disable_inp_buff $end
-$var wire 3 aG amux_select [2:0] $end
-$var reg 1 bG analog_en_final $end
-$var reg 1 cG analog_en_vdda $end
-$var reg 1 dG analog_en_vddio_q $end
-$var reg 1 eG analog_en_vswitch $end
-$var reg 1 fG dis_err_msgs $end
-$var reg 3 gG dm_final [2:0] $end
-$var reg 1 hG hld_ovr_final $end
-$var reg 1 iG ib_mode_sel_final $end
-$var reg 1 jG inp_dis_final $end
-$var reg 1 kG notifier_dm $end
-$var reg 1 lG notifier_enable_h $end
-$var reg 1 mG notifier_hld_ovr $end
-$var reg 1 nG notifier_ib_mode_sel $end
-$var reg 1 oG notifier_inp_dis $end
-$var reg 1 pG notifier_oe_n $end
-$var reg 1 qG notifier_out $end
-$var reg 1 rG notifier_slow $end
-$var reg 1 sG notifier_vtrip_sel $end
-$var reg 1 tG oe_n_final $end
-$var reg 1 uG out_final $end
-$var reg 1 vG slow_final $end
-$var reg 1 wG vtrip_sel_final $end
-$var integer 32 xG msg_count_pad [31:0] $end
-$var integer 32 yG msg_count_pad1 [31:0] $end
-$var integer 32 zG msg_count_pad10 [31:0] $end
-$var integer 32 {G msg_count_pad11 [31:0] $end
-$var integer 32 |G msg_count_pad12 [31:0] $end
-$var integer 32 }G msg_count_pad2 [31:0] $end
-$var integer 32 ~G msg_count_pad3 [31:0] $end
-$var integer 32 !H msg_count_pad4 [31:0] $end
-$var integer 32 "H msg_count_pad5 [31:0] $end
-$var integer 32 #H msg_count_pad6 [31:0] $end
-$var integer 32 $H msg_count_pad7 [31:0] $end
-$var integer 32 %H msg_count_pad8 [31:0] $end
-$var integer 32 &H msg_count_pad9 [31:0] $end
-$var integer 32 'H slow_0_delay [31:0] $end
-$var integer 32 (H slow_1_delay [31:0] $end
-$var integer 32 )H slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[9] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 *H analog_en $end
-$var wire 1 +H analog_pol $end
-$var wire 1 ,H analog_sel $end
-$var wire 3 -H dm [2:0] $end
-$var wire 1 .H enable_h $end
-$var wire 1 /H enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 0H hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 1H ib_mode_sel $end
-$var wire 1 2H inp_dis $end
-$var wire 1 3H oe_n $end
-$var wire 1 4H out $end
-$var wire 1 5H pad $end
-$var wire 1 6H pad_a_esd_0_h $end
-$var wire 1 7H pad_a_esd_1_h $end
-$var wire 1 8H pad_a_noesd_h $end
-$var wire 1 9H slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 :H vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ;H tie_lo_esd $end
-$var wire 1 <H tie_hi_esd $end
-$var wire 1 =H in_h $end
-$var wire 1 >H in $end
-$scope module gpiov2_base $end
-$var event 1 ?H event_error_vswitch5 $end
-$var event 1 @H event_error_vswitch4 $end
-$var event 1 AH event_error_vswitch3 $end
-$var event 1 BH event_error_vswitch2 $end
-$var event 1 CH event_error_vswitch1 $end
-$var event 1 DH event_error_vddio_q2 $end
-$var event 1 EH event_error_vddio_q1 $end
-$var event 1 FH event_error_vdda_vddioq_vswitch2 $end
-$var event 1 GH event_error_vdda3 $end
-$var event 1 HH event_error_vdda2 $end
-$var event 1 IH event_error_vdda $end
-$var event 1 JH event_error_supply_good $end
-$var event 1 KH event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 *H analog_en $end
-$var wire 1 +H analog_pol $end
-$var wire 1 ,H analog_sel $end
-$var wire 3 LH dm [2:0] $end
-$var wire 3 MH dm_buf [2:0] $end
-$var wire 1 .H enable_h $end
-$var wire 1 /H enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 NH error_enable_vddio $end
-$var wire 1 OH error_supply_good $end
-$var wire 1 PH error_vdda $end
-$var wire 1 QH error_vdda2 $end
-$var wire 1 RH error_vdda3 $end
-$var wire 1 SH error_vdda_vddioq_vswitch2 $end
-$var wire 1 TH error_vddio_q1 $end
-$var wire 1 UH error_vddio_q2 $end
-$var wire 1 VH error_vswitch1 $end
-$var wire 1 WH error_vswitch2 $end
-$var wire 1 XH error_vswitch3 $end
-$var wire 1 YH error_vswitch4 $end
-$var wire 1 ZH error_vswitch5 $end
-$var wire 1 [H functional_mode_amux $end
-$var wire 1 0H hld_h_n $end
-$var wire 1 \H hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ]H hld_ovr_buf $end
-$var wire 1 1H ib_mode_sel $end
-$var wire 1 ^H ib_mode_sel_buf $end
-$var wire 1 2H inp_dis $end
-$var wire 1 _H inp_dis_buf $end
-$var wire 1 `H invalid_controls_amux $end
-$var wire 1 3H oe_n $end
-$var wire 1 aH oe_n_buf $end
-$var wire 1 4H out $end
-$var wire 1 bH out_buf $end
-$var wire 1 5H pad $end
-$var wire 1 6H pad_a_esd_0_h $end
-$var wire 1 7H pad_a_esd_1_h $end
-$var wire 1 8H pad_a_noesd_h $end
-$var wire 1 cH pad_tristate $end
-$var wire 1 dH pwr_good_active_mode $end
-$var wire 1 eH pwr_good_active_mode_vdda $end
-$var wire 1 fH pwr_good_amux $end
-$var wire 1 gH pwr_good_analog_en_vdda $end
-$var wire 1 hH pwr_good_analog_en_vddio_q $end
-$var wire 1 iH pwr_good_analog_en_vswitch $end
-$var wire 1 jH pwr_good_hold_mode $end
-$var wire 1 kH pwr_good_hold_mode_vdda $end
-$var wire 1 lH pwr_good_hold_ovr_mode $end
-$var wire 1 mH pwr_good_inpbuff_hv $end
-$var wire 1 nH pwr_good_inpbuff_lv $end
-$var wire 1 oH pwr_good_output_driver $end
-$var wire 1 9H slow $end
-$var wire 1 pH slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 :H vtrip_sel $end
-$var wire 1 qH vtrip_sel_buf $end
-$var wire 1 rH x_on_analog_en_vdda $end
-$var wire 1 sH x_on_analog_en_vddio_q $end
-$var wire 1 tH x_on_analog_en_vswitch $end
-$var wire 1 uH x_on_in_hv $end
-$var wire 1 vH x_on_in_lv $end
-$var wire 1 wH x_on_pad $end
-$var wire 1 xH zero_on_analog_en_vdda $end
-$var wire 1 yH zero_on_analog_en_vddio_q $end
-$var wire 1 zH zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ;H tie_lo_esd $end
-$var wire 1 <H tie_hi_esd $end
-$var wire 1 {H pwr_good_amux_vccd $end
-$var wire 1 =H in_h $end
-$var wire 1 >H in $end
-$var wire 1 |H enable_pad_vssio_q $end
-$var wire 1 }H enable_pad_vddio_q $end
-$var wire 1 ~H enable_pad_amuxbus_b $end
-$var wire 1 !I enable_pad_amuxbus_a $end
-$var wire 1 "I disable_inp_buff_lv $end
-$var wire 1 #I disable_inp_buff $end
-$var wire 3 $I amux_select [2:0] $end
-$var reg 1 %I analog_en_final $end
-$var reg 1 &I analog_en_vdda $end
-$var reg 1 'I analog_en_vddio_q $end
-$var reg 1 (I analog_en_vswitch $end
-$var reg 1 )I dis_err_msgs $end
-$var reg 3 *I dm_final [2:0] $end
-$var reg 1 +I hld_ovr_final $end
-$var reg 1 ,I ib_mode_sel_final $end
-$var reg 1 -I inp_dis_final $end
-$var reg 1 .I notifier_dm $end
-$var reg 1 /I notifier_enable_h $end
-$var reg 1 0I notifier_hld_ovr $end
-$var reg 1 1I notifier_ib_mode_sel $end
-$var reg 1 2I notifier_inp_dis $end
-$var reg 1 3I notifier_oe_n $end
-$var reg 1 4I notifier_out $end
-$var reg 1 5I notifier_slow $end
-$var reg 1 6I notifier_vtrip_sel $end
-$var reg 1 7I oe_n_final $end
-$var reg 1 8I out_final $end
-$var reg 1 9I slow_final $end
-$var reg 1 :I vtrip_sel_final $end
-$var integer 32 ;I msg_count_pad [31:0] $end
-$var integer 32 <I msg_count_pad1 [31:0] $end
-$var integer 32 =I msg_count_pad10 [31:0] $end
-$var integer 32 >I msg_count_pad11 [31:0] $end
-$var integer 32 ?I msg_count_pad12 [31:0] $end
-$var integer 32 @I msg_count_pad2 [31:0] $end
-$var integer 32 AI msg_count_pad3 [31:0] $end
-$var integer 32 BI msg_count_pad4 [31:0] $end
-$var integer 32 CI msg_count_pad5 [31:0] $end
-$var integer 32 DI msg_count_pad6 [31:0] $end
-$var integer 32 EI msg_count_pad7 [31:0] $end
-$var integer 32 FI msg_count_pad8 [31:0] $end
-$var integer 32 GI msg_count_pad9 [31:0] $end
-$var integer 32 HI slow_0_delay [31:0] $end
-$var integer 32 II slow_1_delay [31:0] $end
-$var integer 32 JI slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[10] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 KI analog_en $end
-$var wire 1 LI analog_pol $end
-$var wire 1 MI analog_sel $end
-$var wire 3 NI dm [2:0] $end
-$var wire 1 OI enable_h $end
-$var wire 1 PI enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 QI hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 RI ib_mode_sel $end
-$var wire 1 SI inp_dis $end
-$var wire 1 TI oe_n $end
-$var wire 1 UI out $end
-$var wire 1 VI pad $end
-$var wire 1 WI pad_a_esd_0_h $end
-$var wire 1 XI pad_a_esd_1_h $end
-$var wire 1 YI pad_a_noesd_h $end
-$var wire 1 ZI slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 [I vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 \I tie_lo_esd $end
-$var wire 1 ]I tie_hi_esd $end
-$var wire 1 ^I in_h $end
-$var wire 1 _I in $end
-$scope module gpiov2_base $end
-$var event 1 `I event_error_vswitch5 $end
-$var event 1 aI event_error_vswitch4 $end
-$var event 1 bI event_error_vswitch3 $end
-$var event 1 cI event_error_vswitch2 $end
-$var event 1 dI event_error_vswitch1 $end
-$var event 1 eI event_error_vddio_q2 $end
-$var event 1 fI event_error_vddio_q1 $end
-$var event 1 gI event_error_vdda_vddioq_vswitch2 $end
-$var event 1 hI event_error_vdda3 $end
-$var event 1 iI event_error_vdda2 $end
-$var event 1 jI event_error_vdda $end
-$var event 1 kI event_error_supply_good $end
-$var event 1 lI event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 KI analog_en $end
-$var wire 1 LI analog_pol $end
-$var wire 1 MI analog_sel $end
-$var wire 3 mI dm [2:0] $end
-$var wire 3 nI dm_buf [2:0] $end
-$var wire 1 OI enable_h $end
-$var wire 1 PI enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 oI error_enable_vddio $end
-$var wire 1 pI error_supply_good $end
-$var wire 1 qI error_vdda $end
-$var wire 1 rI error_vdda2 $end
-$var wire 1 sI error_vdda3 $end
-$var wire 1 tI error_vdda_vddioq_vswitch2 $end
-$var wire 1 uI error_vddio_q1 $end
-$var wire 1 vI error_vddio_q2 $end
-$var wire 1 wI error_vswitch1 $end
-$var wire 1 xI error_vswitch2 $end
-$var wire 1 yI error_vswitch3 $end
-$var wire 1 zI error_vswitch4 $end
-$var wire 1 {I error_vswitch5 $end
-$var wire 1 |I functional_mode_amux $end
-$var wire 1 QI hld_h_n $end
-$var wire 1 }I hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ~I hld_ovr_buf $end
-$var wire 1 RI ib_mode_sel $end
-$var wire 1 !J ib_mode_sel_buf $end
-$var wire 1 SI inp_dis $end
-$var wire 1 "J inp_dis_buf $end
-$var wire 1 #J invalid_controls_amux $end
-$var wire 1 TI oe_n $end
-$var wire 1 $J oe_n_buf $end
-$var wire 1 UI out $end
-$var wire 1 %J out_buf $end
-$var wire 1 VI pad $end
-$var wire 1 WI pad_a_esd_0_h $end
-$var wire 1 XI pad_a_esd_1_h $end
-$var wire 1 YI pad_a_noesd_h $end
-$var wire 1 &J pad_tristate $end
-$var wire 1 'J pwr_good_active_mode $end
-$var wire 1 (J pwr_good_active_mode_vdda $end
-$var wire 1 )J pwr_good_amux $end
-$var wire 1 *J pwr_good_analog_en_vdda $end
-$var wire 1 +J pwr_good_analog_en_vddio_q $end
-$var wire 1 ,J pwr_good_analog_en_vswitch $end
-$var wire 1 -J pwr_good_hold_mode $end
-$var wire 1 .J pwr_good_hold_mode_vdda $end
-$var wire 1 /J pwr_good_hold_ovr_mode $end
-$var wire 1 0J pwr_good_inpbuff_hv $end
-$var wire 1 1J pwr_good_inpbuff_lv $end
-$var wire 1 2J pwr_good_output_driver $end
-$var wire 1 ZI slow $end
-$var wire 1 3J slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 [I vtrip_sel $end
-$var wire 1 4J vtrip_sel_buf $end
-$var wire 1 5J x_on_analog_en_vdda $end
-$var wire 1 6J x_on_analog_en_vddio_q $end
-$var wire 1 7J x_on_analog_en_vswitch $end
-$var wire 1 8J x_on_in_hv $end
-$var wire 1 9J x_on_in_lv $end
-$var wire 1 :J x_on_pad $end
-$var wire 1 ;J zero_on_analog_en_vdda $end
-$var wire 1 <J zero_on_analog_en_vddio_q $end
-$var wire 1 =J zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 \I tie_lo_esd $end
-$var wire 1 ]I tie_hi_esd $end
-$var wire 1 >J pwr_good_amux_vccd $end
-$var wire 1 ^I in_h $end
-$var wire 1 _I in $end
-$var wire 1 ?J enable_pad_vssio_q $end
-$var wire 1 @J enable_pad_vddio_q $end
-$var wire 1 AJ enable_pad_amuxbus_b $end
-$var wire 1 BJ enable_pad_amuxbus_a $end
-$var wire 1 CJ disable_inp_buff_lv $end
-$var wire 1 DJ disable_inp_buff $end
-$var wire 3 EJ amux_select [2:0] $end
-$var reg 1 FJ analog_en_final $end
-$var reg 1 GJ analog_en_vdda $end
-$var reg 1 HJ analog_en_vddio_q $end
-$var reg 1 IJ analog_en_vswitch $end
-$var reg 1 JJ dis_err_msgs $end
-$var reg 3 KJ dm_final [2:0] $end
-$var reg 1 LJ hld_ovr_final $end
-$var reg 1 MJ ib_mode_sel_final $end
-$var reg 1 NJ inp_dis_final $end
-$var reg 1 OJ notifier_dm $end
-$var reg 1 PJ notifier_enable_h $end
-$var reg 1 QJ notifier_hld_ovr $end
-$var reg 1 RJ notifier_ib_mode_sel $end
-$var reg 1 SJ notifier_inp_dis $end
-$var reg 1 TJ notifier_oe_n $end
-$var reg 1 UJ notifier_out $end
-$var reg 1 VJ notifier_slow $end
-$var reg 1 WJ notifier_vtrip_sel $end
-$var reg 1 XJ oe_n_final $end
-$var reg 1 YJ out_final $end
-$var reg 1 ZJ slow_final $end
-$var reg 1 [J vtrip_sel_final $end
-$var integer 32 \J msg_count_pad [31:0] $end
-$var integer 32 ]J msg_count_pad1 [31:0] $end
-$var integer 32 ^J msg_count_pad10 [31:0] $end
-$var integer 32 _J msg_count_pad11 [31:0] $end
-$var integer 32 `J msg_count_pad12 [31:0] $end
-$var integer 32 aJ msg_count_pad2 [31:0] $end
-$var integer 32 bJ msg_count_pad3 [31:0] $end
-$var integer 32 cJ msg_count_pad4 [31:0] $end
-$var integer 32 dJ msg_count_pad5 [31:0] $end
-$var integer 32 eJ msg_count_pad6 [31:0] $end
-$var integer 32 fJ msg_count_pad7 [31:0] $end
-$var integer 32 gJ msg_count_pad8 [31:0] $end
-$var integer 32 hJ msg_count_pad9 [31:0] $end
-$var integer 32 iJ slow_0_delay [31:0] $end
-$var integer 32 jJ slow_1_delay [31:0] $end
-$var integer 32 kJ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[11] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 lJ analog_en $end
-$var wire 1 mJ analog_pol $end
-$var wire 1 nJ analog_sel $end
-$var wire 3 oJ dm [2:0] $end
-$var wire 1 pJ enable_h $end
-$var wire 1 qJ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 rJ hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 sJ ib_mode_sel $end
-$var wire 1 tJ inp_dis $end
-$var wire 1 uJ oe_n $end
-$var wire 1 vJ out $end
-$var wire 1 wJ pad $end
-$var wire 1 xJ pad_a_esd_0_h $end
-$var wire 1 yJ pad_a_esd_1_h $end
-$var wire 1 zJ pad_a_noesd_h $end
-$var wire 1 {J slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 |J vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 }J tie_lo_esd $end
-$var wire 1 ~J tie_hi_esd $end
-$var wire 1 !K in_h $end
-$var wire 1 "K in $end
-$scope module gpiov2_base $end
-$var event 1 #K event_error_vswitch5 $end
-$var event 1 $K event_error_vswitch4 $end
-$var event 1 %K event_error_vswitch3 $end
-$var event 1 &K event_error_vswitch2 $end
-$var event 1 'K event_error_vswitch1 $end
-$var event 1 (K event_error_vddio_q2 $end
-$var event 1 )K event_error_vddio_q1 $end
-$var event 1 *K event_error_vdda_vddioq_vswitch2 $end
-$var event 1 +K event_error_vdda3 $end
-$var event 1 ,K event_error_vdda2 $end
-$var event 1 -K event_error_vdda $end
-$var event 1 .K event_error_supply_good $end
-$var event 1 /K event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 lJ analog_en $end
-$var wire 1 mJ analog_pol $end
-$var wire 1 nJ analog_sel $end
-$var wire 3 0K dm [2:0] $end
-$var wire 3 1K dm_buf [2:0] $end
-$var wire 1 pJ enable_h $end
-$var wire 1 qJ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 2K error_enable_vddio $end
-$var wire 1 3K error_supply_good $end
-$var wire 1 4K error_vdda $end
-$var wire 1 5K error_vdda2 $end
-$var wire 1 6K error_vdda3 $end
-$var wire 1 7K error_vdda_vddioq_vswitch2 $end
-$var wire 1 8K error_vddio_q1 $end
-$var wire 1 9K error_vddio_q2 $end
-$var wire 1 :K error_vswitch1 $end
-$var wire 1 ;K error_vswitch2 $end
-$var wire 1 <K error_vswitch3 $end
-$var wire 1 =K error_vswitch4 $end
-$var wire 1 >K error_vswitch5 $end
-$var wire 1 ?K functional_mode_amux $end
-$var wire 1 rJ hld_h_n $end
-$var wire 1 @K hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 AK hld_ovr_buf $end
-$var wire 1 sJ ib_mode_sel $end
-$var wire 1 BK ib_mode_sel_buf $end
-$var wire 1 tJ inp_dis $end
-$var wire 1 CK inp_dis_buf $end
-$var wire 1 DK invalid_controls_amux $end
-$var wire 1 uJ oe_n $end
-$var wire 1 EK oe_n_buf $end
-$var wire 1 vJ out $end
-$var wire 1 FK out_buf $end
-$var wire 1 wJ pad $end
-$var wire 1 xJ pad_a_esd_0_h $end
-$var wire 1 yJ pad_a_esd_1_h $end
-$var wire 1 zJ pad_a_noesd_h $end
-$var wire 1 GK pad_tristate $end
-$var wire 1 HK pwr_good_active_mode $end
-$var wire 1 IK pwr_good_active_mode_vdda $end
-$var wire 1 JK pwr_good_amux $end
-$var wire 1 KK pwr_good_analog_en_vdda $end
-$var wire 1 LK pwr_good_analog_en_vddio_q $end
-$var wire 1 MK pwr_good_analog_en_vswitch $end
-$var wire 1 NK pwr_good_hold_mode $end
-$var wire 1 OK pwr_good_hold_mode_vdda $end
-$var wire 1 PK pwr_good_hold_ovr_mode $end
-$var wire 1 QK pwr_good_inpbuff_hv $end
-$var wire 1 RK pwr_good_inpbuff_lv $end
-$var wire 1 SK pwr_good_output_driver $end
-$var wire 1 {J slow $end
-$var wire 1 TK slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 |J vtrip_sel $end
-$var wire 1 UK vtrip_sel_buf $end
-$var wire 1 VK x_on_analog_en_vdda $end
-$var wire 1 WK x_on_analog_en_vddio_q $end
-$var wire 1 XK x_on_analog_en_vswitch $end
-$var wire 1 YK x_on_in_hv $end
-$var wire 1 ZK x_on_in_lv $end
-$var wire 1 [K x_on_pad $end
-$var wire 1 \K zero_on_analog_en_vdda $end
-$var wire 1 ]K zero_on_analog_en_vddio_q $end
-$var wire 1 ^K zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 }J tie_lo_esd $end
-$var wire 1 ~J tie_hi_esd $end
-$var wire 1 _K pwr_good_amux_vccd $end
-$var wire 1 !K in_h $end
-$var wire 1 "K in $end
-$var wire 1 `K enable_pad_vssio_q $end
-$var wire 1 aK enable_pad_vddio_q $end
-$var wire 1 bK enable_pad_amuxbus_b $end
-$var wire 1 cK enable_pad_amuxbus_a $end
-$var wire 1 dK disable_inp_buff_lv $end
-$var wire 1 eK disable_inp_buff $end
-$var wire 3 fK amux_select [2:0] $end
-$var reg 1 gK analog_en_final $end
-$var reg 1 hK analog_en_vdda $end
-$var reg 1 iK analog_en_vddio_q $end
-$var reg 1 jK analog_en_vswitch $end
-$var reg 1 kK dis_err_msgs $end
-$var reg 3 lK dm_final [2:0] $end
-$var reg 1 mK hld_ovr_final $end
-$var reg 1 nK ib_mode_sel_final $end
-$var reg 1 oK inp_dis_final $end
-$var reg 1 pK notifier_dm $end
-$var reg 1 qK notifier_enable_h $end
-$var reg 1 rK notifier_hld_ovr $end
-$var reg 1 sK notifier_ib_mode_sel $end
-$var reg 1 tK notifier_inp_dis $end
-$var reg 1 uK notifier_oe_n $end
-$var reg 1 vK notifier_out $end
-$var reg 1 wK notifier_slow $end
-$var reg 1 xK notifier_vtrip_sel $end
-$var reg 1 yK oe_n_final $end
-$var reg 1 zK out_final $end
-$var reg 1 {K slow_final $end
-$var reg 1 |K vtrip_sel_final $end
-$var integer 32 }K msg_count_pad [31:0] $end
-$var integer 32 ~K msg_count_pad1 [31:0] $end
-$var integer 32 !L msg_count_pad10 [31:0] $end
-$var integer 32 "L msg_count_pad11 [31:0] $end
-$var integer 32 #L msg_count_pad12 [31:0] $end
-$var integer 32 $L msg_count_pad2 [31:0] $end
-$var integer 32 %L msg_count_pad3 [31:0] $end
-$var integer 32 &L msg_count_pad4 [31:0] $end
-$var integer 32 'L msg_count_pad5 [31:0] $end
-$var integer 32 (L msg_count_pad6 [31:0] $end
-$var integer 32 )L msg_count_pad7 [31:0] $end
-$var integer 32 *L msg_count_pad8 [31:0] $end
-$var integer 32 +L msg_count_pad9 [31:0] $end
-$var integer 32 ,L slow_0_delay [31:0] $end
-$var integer 32 -L slow_1_delay [31:0] $end
-$var integer 32 .L slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[12] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 /L analog_en $end
-$var wire 1 0L analog_pol $end
-$var wire 1 1L analog_sel $end
-$var wire 3 2L dm [2:0] $end
-$var wire 1 3L enable_h $end
-$var wire 1 4L enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 5L hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 6L ib_mode_sel $end
-$var wire 1 7L inp_dis $end
-$var wire 1 8L oe_n $end
-$var wire 1 9L out $end
-$var wire 1 :L pad $end
-$var wire 1 ;L pad_a_esd_0_h $end
-$var wire 1 <L pad_a_esd_1_h $end
-$var wire 1 =L pad_a_noesd_h $end
-$var wire 1 >L slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ?L vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 @L tie_lo_esd $end
-$var wire 1 AL tie_hi_esd $end
-$var wire 1 BL in_h $end
-$var wire 1 CL in $end
-$scope module gpiov2_base $end
-$var event 1 DL event_error_vswitch5 $end
-$var event 1 EL event_error_vswitch4 $end
-$var event 1 FL event_error_vswitch3 $end
-$var event 1 GL event_error_vswitch2 $end
-$var event 1 HL event_error_vswitch1 $end
-$var event 1 IL event_error_vddio_q2 $end
-$var event 1 JL event_error_vddio_q1 $end
-$var event 1 KL event_error_vdda_vddioq_vswitch2 $end
-$var event 1 LL event_error_vdda3 $end
-$var event 1 ML event_error_vdda2 $end
-$var event 1 NL event_error_vdda $end
-$var event 1 OL event_error_supply_good $end
-$var event 1 PL event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 /L analog_en $end
-$var wire 1 0L analog_pol $end
-$var wire 1 1L analog_sel $end
-$var wire 3 QL dm [2:0] $end
-$var wire 3 RL dm_buf [2:0] $end
-$var wire 1 3L enable_h $end
-$var wire 1 4L enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 SL error_enable_vddio $end
-$var wire 1 TL error_supply_good $end
-$var wire 1 UL error_vdda $end
-$var wire 1 VL error_vdda2 $end
-$var wire 1 WL error_vdda3 $end
-$var wire 1 XL error_vdda_vddioq_vswitch2 $end
-$var wire 1 YL error_vddio_q1 $end
-$var wire 1 ZL error_vddio_q2 $end
-$var wire 1 [L error_vswitch1 $end
-$var wire 1 \L error_vswitch2 $end
-$var wire 1 ]L error_vswitch3 $end
-$var wire 1 ^L error_vswitch4 $end
-$var wire 1 _L error_vswitch5 $end
-$var wire 1 `L functional_mode_amux $end
-$var wire 1 5L hld_h_n $end
-$var wire 1 aL hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 bL hld_ovr_buf $end
-$var wire 1 6L ib_mode_sel $end
-$var wire 1 cL ib_mode_sel_buf $end
-$var wire 1 7L inp_dis $end
-$var wire 1 dL inp_dis_buf $end
-$var wire 1 eL invalid_controls_amux $end
-$var wire 1 8L oe_n $end
-$var wire 1 fL oe_n_buf $end
-$var wire 1 9L out $end
-$var wire 1 gL out_buf $end
-$var wire 1 :L pad $end
-$var wire 1 ;L pad_a_esd_0_h $end
-$var wire 1 <L pad_a_esd_1_h $end
-$var wire 1 =L pad_a_noesd_h $end
-$var wire 1 hL pad_tristate $end
-$var wire 1 iL pwr_good_active_mode $end
-$var wire 1 jL pwr_good_active_mode_vdda $end
-$var wire 1 kL pwr_good_amux $end
-$var wire 1 lL pwr_good_analog_en_vdda $end
-$var wire 1 mL pwr_good_analog_en_vddio_q $end
-$var wire 1 nL pwr_good_analog_en_vswitch $end
-$var wire 1 oL pwr_good_hold_mode $end
-$var wire 1 pL pwr_good_hold_mode_vdda $end
-$var wire 1 qL pwr_good_hold_ovr_mode $end
-$var wire 1 rL pwr_good_inpbuff_hv $end
-$var wire 1 sL pwr_good_inpbuff_lv $end
-$var wire 1 tL pwr_good_output_driver $end
-$var wire 1 >L slow $end
-$var wire 1 uL slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ?L vtrip_sel $end
-$var wire 1 vL vtrip_sel_buf $end
-$var wire 1 wL x_on_analog_en_vdda $end
-$var wire 1 xL x_on_analog_en_vddio_q $end
-$var wire 1 yL x_on_analog_en_vswitch $end
-$var wire 1 zL x_on_in_hv $end
-$var wire 1 {L x_on_in_lv $end
-$var wire 1 |L x_on_pad $end
-$var wire 1 }L zero_on_analog_en_vdda $end
-$var wire 1 ~L zero_on_analog_en_vddio_q $end
-$var wire 1 !M zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 @L tie_lo_esd $end
-$var wire 1 AL tie_hi_esd $end
-$var wire 1 "M pwr_good_amux_vccd $end
-$var wire 1 BL in_h $end
-$var wire 1 CL in $end
-$var wire 1 #M enable_pad_vssio_q $end
-$var wire 1 $M enable_pad_vddio_q $end
-$var wire 1 %M enable_pad_amuxbus_b $end
-$var wire 1 &M enable_pad_amuxbus_a $end
-$var wire 1 'M disable_inp_buff_lv $end
-$var wire 1 (M disable_inp_buff $end
-$var wire 3 )M amux_select [2:0] $end
-$var reg 1 *M analog_en_final $end
-$var reg 1 +M analog_en_vdda $end
-$var reg 1 ,M analog_en_vddio_q $end
-$var reg 1 -M analog_en_vswitch $end
-$var reg 1 .M dis_err_msgs $end
-$var reg 3 /M dm_final [2:0] $end
-$var reg 1 0M hld_ovr_final $end
-$var reg 1 1M ib_mode_sel_final $end
-$var reg 1 2M inp_dis_final $end
-$var reg 1 3M notifier_dm $end
-$var reg 1 4M notifier_enable_h $end
-$var reg 1 5M notifier_hld_ovr $end
-$var reg 1 6M notifier_ib_mode_sel $end
-$var reg 1 7M notifier_inp_dis $end
-$var reg 1 8M notifier_oe_n $end
-$var reg 1 9M notifier_out $end
-$var reg 1 :M notifier_slow $end
-$var reg 1 ;M notifier_vtrip_sel $end
-$var reg 1 <M oe_n_final $end
-$var reg 1 =M out_final $end
-$var reg 1 >M slow_final $end
-$var reg 1 ?M vtrip_sel_final $end
-$var integer 32 @M msg_count_pad [31:0] $end
-$var integer 32 AM msg_count_pad1 [31:0] $end
-$var integer 32 BM msg_count_pad10 [31:0] $end
-$var integer 32 CM msg_count_pad11 [31:0] $end
-$var integer 32 DM msg_count_pad12 [31:0] $end
-$var integer 32 EM msg_count_pad2 [31:0] $end
-$var integer 32 FM msg_count_pad3 [31:0] $end
-$var integer 32 GM msg_count_pad4 [31:0] $end
-$var integer 32 HM msg_count_pad5 [31:0] $end
-$var integer 32 IM msg_count_pad6 [31:0] $end
-$var integer 32 JM msg_count_pad7 [31:0] $end
-$var integer 32 KM msg_count_pad8 [31:0] $end
-$var integer 32 LM msg_count_pad9 [31:0] $end
-$var integer 32 MM slow_0_delay [31:0] $end
-$var integer 32 NM slow_1_delay [31:0] $end
-$var integer 32 OM slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[13] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 PM analog_en $end
-$var wire 1 QM analog_pol $end
-$var wire 1 RM analog_sel $end
-$var wire 3 SM dm [2:0] $end
-$var wire 1 TM enable_h $end
-$var wire 1 UM enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 VM hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 WM ib_mode_sel $end
-$var wire 1 XM inp_dis $end
-$var wire 1 YM oe_n $end
-$var wire 1 ZM out $end
-$var wire 1 [M pad $end
-$var wire 1 \M pad_a_esd_0_h $end
-$var wire 1 ]M pad_a_esd_1_h $end
-$var wire 1 ^M pad_a_noesd_h $end
-$var wire 1 _M slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 `M vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 aM tie_lo_esd $end
-$var wire 1 bM tie_hi_esd $end
-$var wire 1 cM in_h $end
-$var wire 1 dM in $end
-$scope module gpiov2_base $end
-$var event 1 eM event_error_vswitch5 $end
-$var event 1 fM event_error_vswitch4 $end
-$var event 1 gM event_error_vswitch3 $end
-$var event 1 hM event_error_vswitch2 $end
-$var event 1 iM event_error_vswitch1 $end
-$var event 1 jM event_error_vddio_q2 $end
-$var event 1 kM event_error_vddio_q1 $end
-$var event 1 lM event_error_vdda_vddioq_vswitch2 $end
-$var event 1 mM event_error_vdda3 $end
-$var event 1 nM event_error_vdda2 $end
-$var event 1 oM event_error_vdda $end
-$var event 1 pM event_error_supply_good $end
-$var event 1 qM event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 PM analog_en $end
-$var wire 1 QM analog_pol $end
-$var wire 1 RM analog_sel $end
-$var wire 3 rM dm [2:0] $end
-$var wire 3 sM dm_buf [2:0] $end
-$var wire 1 TM enable_h $end
-$var wire 1 UM enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 tM error_enable_vddio $end
-$var wire 1 uM error_supply_good $end
-$var wire 1 vM error_vdda $end
-$var wire 1 wM error_vdda2 $end
-$var wire 1 xM error_vdda3 $end
-$var wire 1 yM error_vdda_vddioq_vswitch2 $end
-$var wire 1 zM error_vddio_q1 $end
-$var wire 1 {M error_vddio_q2 $end
-$var wire 1 |M error_vswitch1 $end
-$var wire 1 }M error_vswitch2 $end
-$var wire 1 ~M error_vswitch3 $end
-$var wire 1 !N error_vswitch4 $end
-$var wire 1 "N error_vswitch5 $end
-$var wire 1 #N functional_mode_amux $end
-$var wire 1 VM hld_h_n $end
-$var wire 1 $N hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 %N hld_ovr_buf $end
-$var wire 1 WM ib_mode_sel $end
-$var wire 1 &N ib_mode_sel_buf $end
-$var wire 1 XM inp_dis $end
-$var wire 1 'N inp_dis_buf $end
-$var wire 1 (N invalid_controls_amux $end
-$var wire 1 YM oe_n $end
-$var wire 1 )N oe_n_buf $end
-$var wire 1 ZM out $end
-$var wire 1 *N out_buf $end
-$var wire 1 [M pad $end
-$var wire 1 \M pad_a_esd_0_h $end
-$var wire 1 ]M pad_a_esd_1_h $end
-$var wire 1 ^M pad_a_noesd_h $end
-$var wire 1 +N pad_tristate $end
-$var wire 1 ,N pwr_good_active_mode $end
-$var wire 1 -N pwr_good_active_mode_vdda $end
-$var wire 1 .N pwr_good_amux $end
-$var wire 1 /N pwr_good_analog_en_vdda $end
-$var wire 1 0N pwr_good_analog_en_vddio_q $end
-$var wire 1 1N pwr_good_analog_en_vswitch $end
-$var wire 1 2N pwr_good_hold_mode $end
-$var wire 1 3N pwr_good_hold_mode_vdda $end
-$var wire 1 4N pwr_good_hold_ovr_mode $end
-$var wire 1 5N pwr_good_inpbuff_hv $end
-$var wire 1 6N pwr_good_inpbuff_lv $end
-$var wire 1 7N pwr_good_output_driver $end
-$var wire 1 _M slow $end
-$var wire 1 8N slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 `M vtrip_sel $end
-$var wire 1 9N vtrip_sel_buf $end
-$var wire 1 :N x_on_analog_en_vdda $end
-$var wire 1 ;N x_on_analog_en_vddio_q $end
-$var wire 1 <N x_on_analog_en_vswitch $end
-$var wire 1 =N x_on_in_hv $end
-$var wire 1 >N x_on_in_lv $end
-$var wire 1 ?N x_on_pad $end
-$var wire 1 @N zero_on_analog_en_vdda $end
-$var wire 1 AN zero_on_analog_en_vddio_q $end
-$var wire 1 BN zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 aM tie_lo_esd $end
-$var wire 1 bM tie_hi_esd $end
-$var wire 1 CN pwr_good_amux_vccd $end
-$var wire 1 cM in_h $end
-$var wire 1 dM in $end
-$var wire 1 DN enable_pad_vssio_q $end
-$var wire 1 EN enable_pad_vddio_q $end
-$var wire 1 FN enable_pad_amuxbus_b $end
-$var wire 1 GN enable_pad_amuxbus_a $end
-$var wire 1 HN disable_inp_buff_lv $end
-$var wire 1 IN disable_inp_buff $end
-$var wire 3 JN amux_select [2:0] $end
-$var reg 1 KN analog_en_final $end
-$var reg 1 LN analog_en_vdda $end
-$var reg 1 MN analog_en_vddio_q $end
-$var reg 1 NN analog_en_vswitch $end
-$var reg 1 ON dis_err_msgs $end
-$var reg 3 PN dm_final [2:0] $end
-$var reg 1 QN hld_ovr_final $end
-$var reg 1 RN ib_mode_sel_final $end
-$var reg 1 SN inp_dis_final $end
-$var reg 1 TN notifier_dm $end
-$var reg 1 UN notifier_enable_h $end
-$var reg 1 VN notifier_hld_ovr $end
-$var reg 1 WN notifier_ib_mode_sel $end
-$var reg 1 XN notifier_inp_dis $end
-$var reg 1 YN notifier_oe_n $end
-$var reg 1 ZN notifier_out $end
-$var reg 1 [N notifier_slow $end
-$var reg 1 \N notifier_vtrip_sel $end
-$var reg 1 ]N oe_n_final $end
-$var reg 1 ^N out_final $end
-$var reg 1 _N slow_final $end
-$var reg 1 `N vtrip_sel_final $end
-$var integer 32 aN msg_count_pad [31:0] $end
-$var integer 32 bN msg_count_pad1 [31:0] $end
-$var integer 32 cN msg_count_pad10 [31:0] $end
-$var integer 32 dN msg_count_pad11 [31:0] $end
-$var integer 32 eN msg_count_pad12 [31:0] $end
-$var integer 32 fN msg_count_pad2 [31:0] $end
-$var integer 32 gN msg_count_pad3 [31:0] $end
-$var integer 32 hN msg_count_pad4 [31:0] $end
-$var integer 32 iN msg_count_pad5 [31:0] $end
-$var integer 32 jN msg_count_pad6 [31:0] $end
-$var integer 32 kN msg_count_pad7 [31:0] $end
-$var integer 32 lN msg_count_pad8 [31:0] $end
-$var integer 32 mN msg_count_pad9 [31:0] $end
-$var integer 32 nN slow_0_delay [31:0] $end
-$var integer 32 oN slow_1_delay [31:0] $end
-$var integer 32 pN slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[14] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 qN analog_en $end
-$var wire 1 rN analog_pol $end
-$var wire 1 sN analog_sel $end
-$var wire 3 tN dm [2:0] $end
-$var wire 1 uN enable_h $end
-$var wire 1 vN enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 wN hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 xN ib_mode_sel $end
-$var wire 1 yN inp_dis $end
-$var wire 1 zN oe_n $end
-$var wire 1 {N out $end
-$var wire 1 |N pad $end
-$var wire 1 }N pad_a_esd_0_h $end
-$var wire 1 ~N pad_a_esd_1_h $end
-$var wire 1 !O pad_a_noesd_h $end
-$var wire 1 "O slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 #O vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 $O tie_lo_esd $end
-$var wire 1 %O tie_hi_esd $end
-$var wire 1 &O in_h $end
-$var wire 1 'O in $end
-$scope module gpiov2_base $end
-$var event 1 (O event_error_vswitch5 $end
-$var event 1 )O event_error_vswitch4 $end
-$var event 1 *O event_error_vswitch3 $end
-$var event 1 +O event_error_vswitch2 $end
-$var event 1 ,O event_error_vswitch1 $end
-$var event 1 -O event_error_vddio_q2 $end
-$var event 1 .O event_error_vddio_q1 $end
-$var event 1 /O event_error_vdda_vddioq_vswitch2 $end
-$var event 1 0O event_error_vdda3 $end
-$var event 1 1O event_error_vdda2 $end
-$var event 1 2O event_error_vdda $end
-$var event 1 3O event_error_supply_good $end
-$var event 1 4O event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 qN analog_en $end
-$var wire 1 rN analog_pol $end
-$var wire 1 sN analog_sel $end
-$var wire 3 5O dm [2:0] $end
-$var wire 3 6O dm_buf [2:0] $end
-$var wire 1 uN enable_h $end
-$var wire 1 vN enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 7O error_enable_vddio $end
-$var wire 1 8O error_supply_good $end
-$var wire 1 9O error_vdda $end
-$var wire 1 :O error_vdda2 $end
-$var wire 1 ;O error_vdda3 $end
-$var wire 1 <O error_vdda_vddioq_vswitch2 $end
-$var wire 1 =O error_vddio_q1 $end
-$var wire 1 >O error_vddio_q2 $end
-$var wire 1 ?O error_vswitch1 $end
-$var wire 1 @O error_vswitch2 $end
-$var wire 1 AO error_vswitch3 $end
-$var wire 1 BO error_vswitch4 $end
-$var wire 1 CO error_vswitch5 $end
-$var wire 1 DO functional_mode_amux $end
-$var wire 1 wN hld_h_n $end
-$var wire 1 EO hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 FO hld_ovr_buf $end
-$var wire 1 xN ib_mode_sel $end
-$var wire 1 GO ib_mode_sel_buf $end
-$var wire 1 yN inp_dis $end
-$var wire 1 HO inp_dis_buf $end
-$var wire 1 IO invalid_controls_amux $end
-$var wire 1 zN oe_n $end
-$var wire 1 JO oe_n_buf $end
-$var wire 1 {N out $end
-$var wire 1 KO out_buf $end
-$var wire 1 |N pad $end
-$var wire 1 }N pad_a_esd_0_h $end
-$var wire 1 ~N pad_a_esd_1_h $end
-$var wire 1 !O pad_a_noesd_h $end
-$var wire 1 LO pad_tristate $end
-$var wire 1 MO pwr_good_active_mode $end
-$var wire 1 NO pwr_good_active_mode_vdda $end
-$var wire 1 OO pwr_good_amux $end
-$var wire 1 PO pwr_good_analog_en_vdda $end
-$var wire 1 QO pwr_good_analog_en_vddio_q $end
-$var wire 1 RO pwr_good_analog_en_vswitch $end
-$var wire 1 SO pwr_good_hold_mode $end
-$var wire 1 TO pwr_good_hold_mode_vdda $end
-$var wire 1 UO pwr_good_hold_ovr_mode $end
-$var wire 1 VO pwr_good_inpbuff_hv $end
-$var wire 1 WO pwr_good_inpbuff_lv $end
-$var wire 1 XO pwr_good_output_driver $end
-$var wire 1 "O slow $end
-$var wire 1 YO slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 #O vtrip_sel $end
-$var wire 1 ZO vtrip_sel_buf $end
-$var wire 1 [O x_on_analog_en_vdda $end
-$var wire 1 \O x_on_analog_en_vddio_q $end
-$var wire 1 ]O x_on_analog_en_vswitch $end
-$var wire 1 ^O x_on_in_hv $end
-$var wire 1 _O x_on_in_lv $end
-$var wire 1 `O x_on_pad $end
-$var wire 1 aO zero_on_analog_en_vdda $end
-$var wire 1 bO zero_on_analog_en_vddio_q $end
-$var wire 1 cO zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 $O tie_lo_esd $end
-$var wire 1 %O tie_hi_esd $end
-$var wire 1 dO pwr_good_amux_vccd $end
-$var wire 1 &O in_h $end
-$var wire 1 'O in $end
-$var wire 1 eO enable_pad_vssio_q $end
-$var wire 1 fO enable_pad_vddio_q $end
-$var wire 1 gO enable_pad_amuxbus_b $end
-$var wire 1 hO enable_pad_amuxbus_a $end
-$var wire 1 iO disable_inp_buff_lv $end
-$var wire 1 jO disable_inp_buff $end
-$var wire 3 kO amux_select [2:0] $end
-$var reg 1 lO analog_en_final $end
-$var reg 1 mO analog_en_vdda $end
-$var reg 1 nO analog_en_vddio_q $end
-$var reg 1 oO analog_en_vswitch $end
-$var reg 1 pO dis_err_msgs $end
-$var reg 3 qO dm_final [2:0] $end
-$var reg 1 rO hld_ovr_final $end
-$var reg 1 sO ib_mode_sel_final $end
-$var reg 1 tO inp_dis_final $end
-$var reg 1 uO notifier_dm $end
-$var reg 1 vO notifier_enable_h $end
-$var reg 1 wO notifier_hld_ovr $end
-$var reg 1 xO notifier_ib_mode_sel $end
-$var reg 1 yO notifier_inp_dis $end
-$var reg 1 zO notifier_oe_n $end
-$var reg 1 {O notifier_out $end
-$var reg 1 |O notifier_slow $end
-$var reg 1 }O notifier_vtrip_sel $end
-$var reg 1 ~O oe_n_final $end
-$var reg 1 !P out_final $end
-$var reg 1 "P slow_final $end
-$var reg 1 #P vtrip_sel_final $end
-$var integer 32 $P msg_count_pad [31:0] $end
-$var integer 32 %P msg_count_pad1 [31:0] $end
-$var integer 32 &P msg_count_pad10 [31:0] $end
-$var integer 32 'P msg_count_pad11 [31:0] $end
-$var integer 32 (P msg_count_pad12 [31:0] $end
-$var integer 32 )P msg_count_pad2 [31:0] $end
-$var integer 32 *P msg_count_pad3 [31:0] $end
-$var integer 32 +P msg_count_pad4 [31:0] $end
-$var integer 32 ,P msg_count_pad5 [31:0] $end
-$var integer 32 -P msg_count_pad6 [31:0] $end
-$var integer 32 .P msg_count_pad7 [31:0] $end
-$var integer 32 /P msg_count_pad8 [31:0] $end
-$var integer 32 0P msg_count_pad9 [31:0] $end
-$var integer 32 1P slow_0_delay [31:0] $end
-$var integer 32 2P slow_1_delay [31:0] $end
-$var integer 32 3P slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[15] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 4P analog_en $end
-$var wire 1 5P analog_pol $end
-$var wire 1 6P analog_sel $end
-$var wire 3 7P dm [2:0] $end
-$var wire 1 8P enable_h $end
-$var wire 1 9P enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 :P hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ;P ib_mode_sel $end
-$var wire 1 <P inp_dis $end
-$var wire 1 =P oe_n $end
-$var wire 1 >P out $end
-$var wire 1 ?P pad $end
-$var wire 1 @P pad_a_esd_0_h $end
-$var wire 1 AP pad_a_esd_1_h $end
-$var wire 1 BP pad_a_noesd_h $end
-$var wire 1 CP slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 DP vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 EP tie_lo_esd $end
-$var wire 1 FP tie_hi_esd $end
-$var wire 1 GP in_h $end
-$var wire 1 HP in $end
-$scope module gpiov2_base $end
-$var event 1 IP event_error_vswitch5 $end
-$var event 1 JP event_error_vswitch4 $end
-$var event 1 KP event_error_vswitch3 $end
-$var event 1 LP event_error_vswitch2 $end
-$var event 1 MP event_error_vswitch1 $end
-$var event 1 NP event_error_vddio_q2 $end
-$var event 1 OP event_error_vddio_q1 $end
-$var event 1 PP event_error_vdda_vddioq_vswitch2 $end
-$var event 1 QP event_error_vdda3 $end
-$var event 1 RP event_error_vdda2 $end
-$var event 1 SP event_error_vdda $end
-$var event 1 TP event_error_supply_good $end
-$var event 1 UP event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 4P analog_en $end
-$var wire 1 5P analog_pol $end
-$var wire 1 6P analog_sel $end
-$var wire 3 VP dm [2:0] $end
-$var wire 3 WP dm_buf [2:0] $end
-$var wire 1 8P enable_h $end
-$var wire 1 9P enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 XP error_enable_vddio $end
-$var wire 1 YP error_supply_good $end
-$var wire 1 ZP error_vdda $end
-$var wire 1 [P error_vdda2 $end
-$var wire 1 \P error_vdda3 $end
-$var wire 1 ]P error_vdda_vddioq_vswitch2 $end
-$var wire 1 ^P error_vddio_q1 $end
-$var wire 1 _P error_vddio_q2 $end
-$var wire 1 `P error_vswitch1 $end
-$var wire 1 aP error_vswitch2 $end
-$var wire 1 bP error_vswitch3 $end
-$var wire 1 cP error_vswitch4 $end
-$var wire 1 dP error_vswitch5 $end
-$var wire 1 eP functional_mode_amux $end
-$var wire 1 :P hld_h_n $end
-$var wire 1 fP hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 gP hld_ovr_buf $end
-$var wire 1 ;P ib_mode_sel $end
-$var wire 1 hP ib_mode_sel_buf $end
-$var wire 1 <P inp_dis $end
-$var wire 1 iP inp_dis_buf $end
-$var wire 1 jP invalid_controls_amux $end
-$var wire 1 =P oe_n $end
-$var wire 1 kP oe_n_buf $end
-$var wire 1 >P out $end
-$var wire 1 lP out_buf $end
-$var wire 1 ?P pad $end
-$var wire 1 @P pad_a_esd_0_h $end
-$var wire 1 AP pad_a_esd_1_h $end
-$var wire 1 BP pad_a_noesd_h $end
-$var wire 1 mP pad_tristate $end
-$var wire 1 nP pwr_good_active_mode $end
-$var wire 1 oP pwr_good_active_mode_vdda $end
-$var wire 1 pP pwr_good_amux $end
-$var wire 1 qP pwr_good_analog_en_vdda $end
-$var wire 1 rP pwr_good_analog_en_vddio_q $end
-$var wire 1 sP pwr_good_analog_en_vswitch $end
-$var wire 1 tP pwr_good_hold_mode $end
-$var wire 1 uP pwr_good_hold_mode_vdda $end
-$var wire 1 vP pwr_good_hold_ovr_mode $end
-$var wire 1 wP pwr_good_inpbuff_hv $end
-$var wire 1 xP pwr_good_inpbuff_lv $end
-$var wire 1 yP pwr_good_output_driver $end
-$var wire 1 CP slow $end
-$var wire 1 zP slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 DP vtrip_sel $end
-$var wire 1 {P vtrip_sel_buf $end
-$var wire 1 |P x_on_analog_en_vdda $end
-$var wire 1 }P x_on_analog_en_vddio_q $end
-$var wire 1 ~P x_on_analog_en_vswitch $end
-$var wire 1 !Q x_on_in_hv $end
-$var wire 1 "Q x_on_in_lv $end
-$var wire 1 #Q x_on_pad $end
-$var wire 1 $Q zero_on_analog_en_vdda $end
-$var wire 1 %Q zero_on_analog_en_vddio_q $end
-$var wire 1 &Q zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 EP tie_lo_esd $end
-$var wire 1 FP tie_hi_esd $end
-$var wire 1 'Q pwr_good_amux_vccd $end
-$var wire 1 GP in_h $end
-$var wire 1 HP in $end
-$var wire 1 (Q enable_pad_vssio_q $end
-$var wire 1 )Q enable_pad_vddio_q $end
-$var wire 1 *Q enable_pad_amuxbus_b $end
-$var wire 1 +Q enable_pad_amuxbus_a $end
-$var wire 1 ,Q disable_inp_buff_lv $end
-$var wire 1 -Q disable_inp_buff $end
-$var wire 3 .Q amux_select [2:0] $end
-$var reg 1 /Q analog_en_final $end
-$var reg 1 0Q analog_en_vdda $end
-$var reg 1 1Q analog_en_vddio_q $end
-$var reg 1 2Q analog_en_vswitch $end
-$var reg 1 3Q dis_err_msgs $end
-$var reg 3 4Q dm_final [2:0] $end
-$var reg 1 5Q hld_ovr_final $end
-$var reg 1 6Q ib_mode_sel_final $end
-$var reg 1 7Q inp_dis_final $end
-$var reg 1 8Q notifier_dm $end
-$var reg 1 9Q notifier_enable_h $end
-$var reg 1 :Q notifier_hld_ovr $end
-$var reg 1 ;Q notifier_ib_mode_sel $end
-$var reg 1 <Q notifier_inp_dis $end
-$var reg 1 =Q notifier_oe_n $end
-$var reg 1 >Q notifier_out $end
-$var reg 1 ?Q notifier_slow $end
-$var reg 1 @Q notifier_vtrip_sel $end
-$var reg 1 AQ oe_n_final $end
-$var reg 1 BQ out_final $end
-$var reg 1 CQ slow_final $end
-$var reg 1 DQ vtrip_sel_final $end
-$var integer 32 EQ msg_count_pad [31:0] $end
-$var integer 32 FQ msg_count_pad1 [31:0] $end
-$var integer 32 GQ msg_count_pad10 [31:0] $end
-$var integer 32 HQ msg_count_pad11 [31:0] $end
-$var integer 32 IQ msg_count_pad12 [31:0] $end
-$var integer 32 JQ msg_count_pad2 [31:0] $end
-$var integer 32 KQ msg_count_pad3 [31:0] $end
-$var integer 32 LQ msg_count_pad4 [31:0] $end
-$var integer 32 MQ msg_count_pad5 [31:0] $end
-$var integer 32 NQ msg_count_pad6 [31:0] $end
-$var integer 32 OQ msg_count_pad7 [31:0] $end
-$var integer 32 PQ msg_count_pad8 [31:0] $end
-$var integer 32 QQ msg_count_pad9 [31:0] $end
-$var integer 32 RQ slow_0_delay [31:0] $end
-$var integer 32 SQ slow_1_delay [31:0] $end
-$var integer 32 TQ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[16] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 UQ analog_en $end
-$var wire 1 VQ analog_pol $end
-$var wire 1 WQ analog_sel $end
-$var wire 3 XQ dm [2:0] $end
-$var wire 1 YQ enable_h $end
-$var wire 1 ZQ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 [Q hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 \Q ib_mode_sel $end
-$var wire 1 ]Q inp_dis $end
-$var wire 1 ^Q oe_n $end
-$var wire 1 _Q out $end
-$var wire 1 `Q pad $end
-$var wire 1 aQ pad_a_esd_0_h $end
-$var wire 1 bQ pad_a_esd_1_h $end
-$var wire 1 cQ pad_a_noesd_h $end
-$var wire 1 dQ slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 eQ vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 fQ tie_lo_esd $end
-$var wire 1 gQ tie_hi_esd $end
-$var wire 1 hQ in_h $end
-$var wire 1 iQ in $end
-$scope module gpiov2_base $end
-$var event 1 jQ event_error_vswitch5 $end
-$var event 1 kQ event_error_vswitch4 $end
-$var event 1 lQ event_error_vswitch3 $end
-$var event 1 mQ event_error_vswitch2 $end
-$var event 1 nQ event_error_vswitch1 $end
-$var event 1 oQ event_error_vddio_q2 $end
-$var event 1 pQ event_error_vddio_q1 $end
-$var event 1 qQ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 rQ event_error_vdda3 $end
-$var event 1 sQ event_error_vdda2 $end
-$var event 1 tQ event_error_vdda $end
-$var event 1 uQ event_error_supply_good $end
-$var event 1 vQ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 UQ analog_en $end
-$var wire 1 VQ analog_pol $end
-$var wire 1 WQ analog_sel $end
-$var wire 3 wQ dm [2:0] $end
-$var wire 3 xQ dm_buf [2:0] $end
-$var wire 1 YQ enable_h $end
-$var wire 1 ZQ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 yQ error_enable_vddio $end
-$var wire 1 zQ error_supply_good $end
-$var wire 1 {Q error_vdda $end
-$var wire 1 |Q error_vdda2 $end
-$var wire 1 }Q error_vdda3 $end
-$var wire 1 ~Q error_vdda_vddioq_vswitch2 $end
-$var wire 1 !R error_vddio_q1 $end
-$var wire 1 "R error_vddio_q2 $end
-$var wire 1 #R error_vswitch1 $end
-$var wire 1 $R error_vswitch2 $end
-$var wire 1 %R error_vswitch3 $end
-$var wire 1 &R error_vswitch4 $end
-$var wire 1 'R error_vswitch5 $end
-$var wire 1 (R functional_mode_amux $end
-$var wire 1 [Q hld_h_n $end
-$var wire 1 )R hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 *R hld_ovr_buf $end
-$var wire 1 \Q ib_mode_sel $end
-$var wire 1 +R ib_mode_sel_buf $end
-$var wire 1 ]Q inp_dis $end
-$var wire 1 ,R inp_dis_buf $end
-$var wire 1 -R invalid_controls_amux $end
-$var wire 1 ^Q oe_n $end
-$var wire 1 .R oe_n_buf $end
-$var wire 1 _Q out $end
-$var wire 1 /R out_buf $end
-$var wire 1 `Q pad $end
-$var wire 1 aQ pad_a_esd_0_h $end
-$var wire 1 bQ pad_a_esd_1_h $end
-$var wire 1 cQ pad_a_noesd_h $end
-$var wire 1 0R pad_tristate $end
-$var wire 1 1R pwr_good_active_mode $end
-$var wire 1 2R pwr_good_active_mode_vdda $end
-$var wire 1 3R pwr_good_amux $end
-$var wire 1 4R pwr_good_analog_en_vdda $end
-$var wire 1 5R pwr_good_analog_en_vddio_q $end
-$var wire 1 6R pwr_good_analog_en_vswitch $end
-$var wire 1 7R pwr_good_hold_mode $end
-$var wire 1 8R pwr_good_hold_mode_vdda $end
-$var wire 1 9R pwr_good_hold_ovr_mode $end
-$var wire 1 :R pwr_good_inpbuff_hv $end
-$var wire 1 ;R pwr_good_inpbuff_lv $end
-$var wire 1 <R pwr_good_output_driver $end
-$var wire 1 dQ slow $end
-$var wire 1 =R slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 eQ vtrip_sel $end
-$var wire 1 >R vtrip_sel_buf $end
-$var wire 1 ?R x_on_analog_en_vdda $end
-$var wire 1 @R x_on_analog_en_vddio_q $end
-$var wire 1 AR x_on_analog_en_vswitch $end
-$var wire 1 BR x_on_in_hv $end
-$var wire 1 CR x_on_in_lv $end
-$var wire 1 DR x_on_pad $end
-$var wire 1 ER zero_on_analog_en_vdda $end
-$var wire 1 FR zero_on_analog_en_vddio_q $end
-$var wire 1 GR zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 fQ tie_lo_esd $end
-$var wire 1 gQ tie_hi_esd $end
-$var wire 1 HR pwr_good_amux_vccd $end
-$var wire 1 hQ in_h $end
-$var wire 1 iQ in $end
-$var wire 1 IR enable_pad_vssio_q $end
-$var wire 1 JR enable_pad_vddio_q $end
-$var wire 1 KR enable_pad_amuxbus_b $end
-$var wire 1 LR enable_pad_amuxbus_a $end
-$var wire 1 MR disable_inp_buff_lv $end
-$var wire 1 NR disable_inp_buff $end
-$var wire 3 OR amux_select [2:0] $end
-$var reg 1 PR analog_en_final $end
-$var reg 1 QR analog_en_vdda $end
-$var reg 1 RR analog_en_vddio_q $end
-$var reg 1 SR analog_en_vswitch $end
-$var reg 1 TR dis_err_msgs $end
-$var reg 3 UR dm_final [2:0] $end
-$var reg 1 VR hld_ovr_final $end
-$var reg 1 WR ib_mode_sel_final $end
-$var reg 1 XR inp_dis_final $end
-$var reg 1 YR notifier_dm $end
-$var reg 1 ZR notifier_enable_h $end
-$var reg 1 [R notifier_hld_ovr $end
-$var reg 1 \R notifier_ib_mode_sel $end
-$var reg 1 ]R notifier_inp_dis $end
-$var reg 1 ^R notifier_oe_n $end
-$var reg 1 _R notifier_out $end
-$var reg 1 `R notifier_slow $end
-$var reg 1 aR notifier_vtrip_sel $end
-$var reg 1 bR oe_n_final $end
-$var reg 1 cR out_final $end
-$var reg 1 dR slow_final $end
-$var reg 1 eR vtrip_sel_final $end
-$var integer 32 fR msg_count_pad [31:0] $end
-$var integer 32 gR msg_count_pad1 [31:0] $end
-$var integer 32 hR msg_count_pad10 [31:0] $end
-$var integer 32 iR msg_count_pad11 [31:0] $end
-$var integer 32 jR msg_count_pad12 [31:0] $end
-$var integer 32 kR msg_count_pad2 [31:0] $end
-$var integer 32 lR msg_count_pad3 [31:0] $end
-$var integer 32 mR msg_count_pad4 [31:0] $end
-$var integer 32 nR msg_count_pad5 [31:0] $end
-$var integer 32 oR msg_count_pad6 [31:0] $end
-$var integer 32 pR msg_count_pad7 [31:0] $end
-$var integer 32 qR msg_count_pad8 [31:0] $end
-$var integer 32 rR msg_count_pad9 [31:0] $end
-$var integer 32 sR slow_0_delay [31:0] $end
-$var integer 32 tR slow_1_delay [31:0] $end
-$var integer 32 uR slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[17] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 vR analog_en $end
-$var wire 1 wR analog_pol $end
-$var wire 1 xR analog_sel $end
-$var wire 3 yR dm [2:0] $end
-$var wire 1 zR enable_h $end
-$var wire 1 {R enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 |R hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 }R ib_mode_sel $end
-$var wire 1 ~R inp_dis $end
-$var wire 1 !S oe_n $end
-$var wire 1 "S out $end
-$var wire 1 #S pad $end
-$var wire 1 $S pad_a_esd_0_h $end
-$var wire 1 %S pad_a_esd_1_h $end
-$var wire 1 &S pad_a_noesd_h $end
-$var wire 1 'S slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 (S vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 )S tie_lo_esd $end
-$var wire 1 *S tie_hi_esd $end
-$var wire 1 +S in_h $end
-$var wire 1 ,S in $end
-$scope module gpiov2_base $end
-$var event 1 -S event_error_vswitch5 $end
-$var event 1 .S event_error_vswitch4 $end
-$var event 1 /S event_error_vswitch3 $end
-$var event 1 0S event_error_vswitch2 $end
-$var event 1 1S event_error_vswitch1 $end
-$var event 1 2S event_error_vddio_q2 $end
-$var event 1 3S event_error_vddio_q1 $end
-$var event 1 4S event_error_vdda_vddioq_vswitch2 $end
-$var event 1 5S event_error_vdda3 $end
-$var event 1 6S event_error_vdda2 $end
-$var event 1 7S event_error_vdda $end
-$var event 1 8S event_error_supply_good $end
-$var event 1 9S event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 vR analog_en $end
-$var wire 1 wR analog_pol $end
-$var wire 1 xR analog_sel $end
-$var wire 3 :S dm [2:0] $end
-$var wire 3 ;S dm_buf [2:0] $end
-$var wire 1 zR enable_h $end
-$var wire 1 {R enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 <S error_enable_vddio $end
-$var wire 1 =S error_supply_good $end
-$var wire 1 >S error_vdda $end
-$var wire 1 ?S error_vdda2 $end
-$var wire 1 @S error_vdda3 $end
-$var wire 1 AS error_vdda_vddioq_vswitch2 $end
-$var wire 1 BS error_vddio_q1 $end
-$var wire 1 CS error_vddio_q2 $end
-$var wire 1 DS error_vswitch1 $end
-$var wire 1 ES error_vswitch2 $end
-$var wire 1 FS error_vswitch3 $end
-$var wire 1 GS error_vswitch4 $end
-$var wire 1 HS error_vswitch5 $end
-$var wire 1 IS functional_mode_amux $end
-$var wire 1 |R hld_h_n $end
-$var wire 1 JS hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 KS hld_ovr_buf $end
-$var wire 1 }R ib_mode_sel $end
-$var wire 1 LS ib_mode_sel_buf $end
-$var wire 1 ~R inp_dis $end
-$var wire 1 MS inp_dis_buf $end
-$var wire 1 NS invalid_controls_amux $end
-$var wire 1 !S oe_n $end
-$var wire 1 OS oe_n_buf $end
-$var wire 1 "S out $end
-$var wire 1 PS out_buf $end
-$var wire 1 #S pad $end
-$var wire 1 $S pad_a_esd_0_h $end
-$var wire 1 %S pad_a_esd_1_h $end
-$var wire 1 &S pad_a_noesd_h $end
-$var wire 1 QS pad_tristate $end
-$var wire 1 RS pwr_good_active_mode $end
-$var wire 1 SS pwr_good_active_mode_vdda $end
-$var wire 1 TS pwr_good_amux $end
-$var wire 1 US pwr_good_analog_en_vdda $end
-$var wire 1 VS pwr_good_analog_en_vddio_q $end
-$var wire 1 WS pwr_good_analog_en_vswitch $end
-$var wire 1 XS pwr_good_hold_mode $end
-$var wire 1 YS pwr_good_hold_mode_vdda $end
-$var wire 1 ZS pwr_good_hold_ovr_mode $end
-$var wire 1 [S pwr_good_inpbuff_hv $end
-$var wire 1 \S pwr_good_inpbuff_lv $end
-$var wire 1 ]S pwr_good_output_driver $end
-$var wire 1 'S slow $end
-$var wire 1 ^S slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 (S vtrip_sel $end
-$var wire 1 _S vtrip_sel_buf $end
-$var wire 1 `S x_on_analog_en_vdda $end
-$var wire 1 aS x_on_analog_en_vddio_q $end
-$var wire 1 bS x_on_analog_en_vswitch $end
-$var wire 1 cS x_on_in_hv $end
-$var wire 1 dS x_on_in_lv $end
-$var wire 1 eS x_on_pad $end
-$var wire 1 fS zero_on_analog_en_vdda $end
-$var wire 1 gS zero_on_analog_en_vddio_q $end
-$var wire 1 hS zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 )S tie_lo_esd $end
-$var wire 1 *S tie_hi_esd $end
-$var wire 1 iS pwr_good_amux_vccd $end
-$var wire 1 +S in_h $end
-$var wire 1 ,S in $end
-$var wire 1 jS enable_pad_vssio_q $end
-$var wire 1 kS enable_pad_vddio_q $end
-$var wire 1 lS enable_pad_amuxbus_b $end
-$var wire 1 mS enable_pad_amuxbus_a $end
-$var wire 1 nS disable_inp_buff_lv $end
-$var wire 1 oS disable_inp_buff $end
-$var wire 3 pS amux_select [2:0] $end
-$var reg 1 qS analog_en_final $end
-$var reg 1 rS analog_en_vdda $end
-$var reg 1 sS analog_en_vddio_q $end
-$var reg 1 tS analog_en_vswitch $end
-$var reg 1 uS dis_err_msgs $end
-$var reg 3 vS dm_final [2:0] $end
-$var reg 1 wS hld_ovr_final $end
-$var reg 1 xS ib_mode_sel_final $end
-$var reg 1 yS inp_dis_final $end
-$var reg 1 zS notifier_dm $end
-$var reg 1 {S notifier_enable_h $end
-$var reg 1 |S notifier_hld_ovr $end
-$var reg 1 }S notifier_ib_mode_sel $end
-$var reg 1 ~S notifier_inp_dis $end
-$var reg 1 !T notifier_oe_n $end
-$var reg 1 "T notifier_out $end
-$var reg 1 #T notifier_slow $end
-$var reg 1 $T notifier_vtrip_sel $end
-$var reg 1 %T oe_n_final $end
-$var reg 1 &T out_final $end
-$var reg 1 'T slow_final $end
-$var reg 1 (T vtrip_sel_final $end
-$var integer 32 )T msg_count_pad [31:0] $end
-$var integer 32 *T msg_count_pad1 [31:0] $end
-$var integer 32 +T msg_count_pad10 [31:0] $end
-$var integer 32 ,T msg_count_pad11 [31:0] $end
-$var integer 32 -T msg_count_pad12 [31:0] $end
-$var integer 32 .T msg_count_pad2 [31:0] $end
-$var integer 32 /T msg_count_pad3 [31:0] $end
-$var integer 32 0T msg_count_pad4 [31:0] $end
-$var integer 32 1T msg_count_pad5 [31:0] $end
-$var integer 32 2T msg_count_pad6 [31:0] $end
-$var integer 32 3T msg_count_pad7 [31:0] $end
-$var integer 32 4T msg_count_pad8 [31:0] $end
-$var integer 32 5T msg_count_pad9 [31:0] $end
-$var integer 32 6T slow_0_delay [31:0] $end
-$var integer 32 7T slow_1_delay [31:0] $end
-$var integer 32 8T slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[18] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 9T analog_en $end
-$var wire 1 :T analog_pol $end
-$var wire 1 ;T analog_sel $end
-$var wire 3 <T dm [2:0] $end
-$var wire 1 =T enable_h $end
-$var wire 1 >T enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ?T hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 @T ib_mode_sel $end
-$var wire 1 AT inp_dis $end
-$var wire 1 BT oe_n $end
-$var wire 1 CT out $end
-$var wire 1 DT pad $end
-$var wire 1 ET pad_a_esd_0_h $end
-$var wire 1 FT pad_a_esd_1_h $end
-$var wire 1 GT pad_a_noesd_h $end
-$var wire 1 HT slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 IT vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 JT tie_lo_esd $end
-$var wire 1 KT tie_hi_esd $end
-$var wire 1 LT in_h $end
-$var wire 1 MT in $end
-$scope module gpiov2_base $end
-$var event 1 NT event_error_vswitch5 $end
-$var event 1 OT event_error_vswitch4 $end
-$var event 1 PT event_error_vswitch3 $end
-$var event 1 QT event_error_vswitch2 $end
-$var event 1 RT event_error_vswitch1 $end
-$var event 1 ST event_error_vddio_q2 $end
-$var event 1 TT event_error_vddio_q1 $end
-$var event 1 UT event_error_vdda_vddioq_vswitch2 $end
-$var event 1 VT event_error_vdda3 $end
-$var event 1 WT event_error_vdda2 $end
-$var event 1 XT event_error_vdda $end
-$var event 1 YT event_error_supply_good $end
-$var event 1 ZT event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 9T analog_en $end
-$var wire 1 :T analog_pol $end
-$var wire 1 ;T analog_sel $end
-$var wire 3 [T dm [2:0] $end
-$var wire 3 \T dm_buf [2:0] $end
-$var wire 1 =T enable_h $end
-$var wire 1 >T enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ]T error_enable_vddio $end
-$var wire 1 ^T error_supply_good $end
-$var wire 1 _T error_vdda $end
-$var wire 1 `T error_vdda2 $end
-$var wire 1 aT error_vdda3 $end
-$var wire 1 bT error_vdda_vddioq_vswitch2 $end
-$var wire 1 cT error_vddio_q1 $end
-$var wire 1 dT error_vddio_q2 $end
-$var wire 1 eT error_vswitch1 $end
-$var wire 1 fT error_vswitch2 $end
-$var wire 1 gT error_vswitch3 $end
-$var wire 1 hT error_vswitch4 $end
-$var wire 1 iT error_vswitch5 $end
-$var wire 1 jT functional_mode_amux $end
-$var wire 1 ?T hld_h_n $end
-$var wire 1 kT hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 lT hld_ovr_buf $end
-$var wire 1 @T ib_mode_sel $end
-$var wire 1 mT ib_mode_sel_buf $end
-$var wire 1 AT inp_dis $end
-$var wire 1 nT inp_dis_buf $end
-$var wire 1 oT invalid_controls_amux $end
-$var wire 1 BT oe_n $end
-$var wire 1 pT oe_n_buf $end
-$var wire 1 CT out $end
-$var wire 1 qT out_buf $end
-$var wire 1 DT pad $end
-$var wire 1 ET pad_a_esd_0_h $end
-$var wire 1 FT pad_a_esd_1_h $end
-$var wire 1 GT pad_a_noesd_h $end
-$var wire 1 rT pad_tristate $end
-$var wire 1 sT pwr_good_active_mode $end
-$var wire 1 tT pwr_good_active_mode_vdda $end
-$var wire 1 uT pwr_good_amux $end
-$var wire 1 vT pwr_good_analog_en_vdda $end
-$var wire 1 wT pwr_good_analog_en_vddio_q $end
-$var wire 1 xT pwr_good_analog_en_vswitch $end
-$var wire 1 yT pwr_good_hold_mode $end
-$var wire 1 zT pwr_good_hold_mode_vdda $end
-$var wire 1 {T pwr_good_hold_ovr_mode $end
-$var wire 1 |T pwr_good_inpbuff_hv $end
-$var wire 1 }T pwr_good_inpbuff_lv $end
-$var wire 1 ~T pwr_good_output_driver $end
-$var wire 1 HT slow $end
-$var wire 1 !U slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 IT vtrip_sel $end
-$var wire 1 "U vtrip_sel_buf $end
-$var wire 1 #U x_on_analog_en_vdda $end
-$var wire 1 $U x_on_analog_en_vddio_q $end
-$var wire 1 %U x_on_analog_en_vswitch $end
-$var wire 1 &U x_on_in_hv $end
-$var wire 1 'U x_on_in_lv $end
-$var wire 1 (U x_on_pad $end
-$var wire 1 )U zero_on_analog_en_vdda $end
-$var wire 1 *U zero_on_analog_en_vddio_q $end
-$var wire 1 +U zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 JT tie_lo_esd $end
-$var wire 1 KT tie_hi_esd $end
-$var wire 1 ,U pwr_good_amux_vccd $end
-$var wire 1 LT in_h $end
-$var wire 1 MT in $end
-$var wire 1 -U enable_pad_vssio_q $end
-$var wire 1 .U enable_pad_vddio_q $end
-$var wire 1 /U enable_pad_amuxbus_b $end
-$var wire 1 0U enable_pad_amuxbus_a $end
-$var wire 1 1U disable_inp_buff_lv $end
-$var wire 1 2U disable_inp_buff $end
-$var wire 3 3U amux_select [2:0] $end
-$var reg 1 4U analog_en_final $end
-$var reg 1 5U analog_en_vdda $end
-$var reg 1 6U analog_en_vddio_q $end
-$var reg 1 7U analog_en_vswitch $end
-$var reg 1 8U dis_err_msgs $end
-$var reg 3 9U dm_final [2:0] $end
-$var reg 1 :U hld_ovr_final $end
-$var reg 1 ;U ib_mode_sel_final $end
-$var reg 1 <U inp_dis_final $end
-$var reg 1 =U notifier_dm $end
-$var reg 1 >U notifier_enable_h $end
-$var reg 1 ?U notifier_hld_ovr $end
-$var reg 1 @U notifier_ib_mode_sel $end
-$var reg 1 AU notifier_inp_dis $end
-$var reg 1 BU notifier_oe_n $end
-$var reg 1 CU notifier_out $end
-$var reg 1 DU notifier_slow $end
-$var reg 1 EU notifier_vtrip_sel $end
-$var reg 1 FU oe_n_final $end
-$var reg 1 GU out_final $end
-$var reg 1 HU slow_final $end
-$var reg 1 IU vtrip_sel_final $end
-$var integer 32 JU msg_count_pad [31:0] $end
-$var integer 32 KU msg_count_pad1 [31:0] $end
-$var integer 32 LU msg_count_pad10 [31:0] $end
-$var integer 32 MU msg_count_pad11 [31:0] $end
-$var integer 32 NU msg_count_pad12 [31:0] $end
-$var integer 32 OU msg_count_pad2 [31:0] $end
-$var integer 32 PU msg_count_pad3 [31:0] $end
-$var integer 32 QU msg_count_pad4 [31:0] $end
-$var integer 32 RU msg_count_pad5 [31:0] $end
-$var integer 32 SU msg_count_pad6 [31:0] $end
-$var integer 32 TU msg_count_pad7 [31:0] $end
-$var integer 32 UU msg_count_pad8 [31:0] $end
-$var integer 32 VU msg_count_pad9 [31:0] $end
-$var integer 32 WU slow_0_delay [31:0] $end
-$var integer 32 XU slow_1_delay [31:0] $end
-$var integer 32 YU slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[19] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ZU analog_en $end
-$var wire 1 [U analog_pol $end
-$var wire 1 \U analog_sel $end
-$var wire 3 ]U dm [2:0] $end
-$var wire 1 ^U enable_h $end
-$var wire 1 _U enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 `U hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 aU ib_mode_sel $end
-$var wire 1 bU inp_dis $end
-$var wire 1 cU oe_n $end
-$var wire 1 dU out $end
-$var wire 1 eU pad $end
-$var wire 1 fU pad_a_esd_0_h $end
-$var wire 1 gU pad_a_esd_1_h $end
-$var wire 1 hU pad_a_noesd_h $end
-$var wire 1 iU slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 jU vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 kU tie_lo_esd $end
-$var wire 1 lU tie_hi_esd $end
-$var wire 1 mU in_h $end
-$var wire 1 nU in $end
-$scope module gpiov2_base $end
-$var event 1 oU event_error_vswitch5 $end
-$var event 1 pU event_error_vswitch4 $end
-$var event 1 qU event_error_vswitch3 $end
-$var event 1 rU event_error_vswitch2 $end
-$var event 1 sU event_error_vswitch1 $end
-$var event 1 tU event_error_vddio_q2 $end
-$var event 1 uU event_error_vddio_q1 $end
-$var event 1 vU event_error_vdda_vddioq_vswitch2 $end
-$var event 1 wU event_error_vdda3 $end
-$var event 1 xU event_error_vdda2 $end
-$var event 1 yU event_error_vdda $end
-$var event 1 zU event_error_supply_good $end
-$var event 1 {U event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ZU analog_en $end
-$var wire 1 [U analog_pol $end
-$var wire 1 \U analog_sel $end
-$var wire 3 |U dm [2:0] $end
-$var wire 3 }U dm_buf [2:0] $end
-$var wire 1 ^U enable_h $end
-$var wire 1 _U enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ~U error_enable_vddio $end
-$var wire 1 !V error_supply_good $end
-$var wire 1 "V error_vdda $end
-$var wire 1 #V error_vdda2 $end
-$var wire 1 $V error_vdda3 $end
-$var wire 1 %V error_vdda_vddioq_vswitch2 $end
-$var wire 1 &V error_vddio_q1 $end
-$var wire 1 'V error_vddio_q2 $end
-$var wire 1 (V error_vswitch1 $end
-$var wire 1 )V error_vswitch2 $end
-$var wire 1 *V error_vswitch3 $end
-$var wire 1 +V error_vswitch4 $end
-$var wire 1 ,V error_vswitch5 $end
-$var wire 1 -V functional_mode_amux $end
-$var wire 1 `U hld_h_n $end
-$var wire 1 .V hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 /V hld_ovr_buf $end
-$var wire 1 aU ib_mode_sel $end
-$var wire 1 0V ib_mode_sel_buf $end
-$var wire 1 bU inp_dis $end
-$var wire 1 1V inp_dis_buf $end
-$var wire 1 2V invalid_controls_amux $end
-$var wire 1 cU oe_n $end
-$var wire 1 3V oe_n_buf $end
-$var wire 1 dU out $end
-$var wire 1 4V out_buf $end
-$var wire 1 eU pad $end
-$var wire 1 fU pad_a_esd_0_h $end
-$var wire 1 gU pad_a_esd_1_h $end
-$var wire 1 hU pad_a_noesd_h $end
-$var wire 1 5V pad_tristate $end
-$var wire 1 6V pwr_good_active_mode $end
-$var wire 1 7V pwr_good_active_mode_vdda $end
-$var wire 1 8V pwr_good_amux $end
-$var wire 1 9V pwr_good_analog_en_vdda $end
-$var wire 1 :V pwr_good_analog_en_vddio_q $end
-$var wire 1 ;V pwr_good_analog_en_vswitch $end
-$var wire 1 <V pwr_good_hold_mode $end
-$var wire 1 =V pwr_good_hold_mode_vdda $end
-$var wire 1 >V pwr_good_hold_ovr_mode $end
-$var wire 1 ?V pwr_good_inpbuff_hv $end
-$var wire 1 @V pwr_good_inpbuff_lv $end
-$var wire 1 AV pwr_good_output_driver $end
-$var wire 1 iU slow $end
-$var wire 1 BV slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 jU vtrip_sel $end
-$var wire 1 CV vtrip_sel_buf $end
-$var wire 1 DV x_on_analog_en_vdda $end
-$var wire 1 EV x_on_analog_en_vddio_q $end
-$var wire 1 FV x_on_analog_en_vswitch $end
-$var wire 1 GV x_on_in_hv $end
-$var wire 1 HV x_on_in_lv $end
-$var wire 1 IV x_on_pad $end
-$var wire 1 JV zero_on_analog_en_vdda $end
-$var wire 1 KV zero_on_analog_en_vddio_q $end
-$var wire 1 LV zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 kU tie_lo_esd $end
-$var wire 1 lU tie_hi_esd $end
-$var wire 1 MV pwr_good_amux_vccd $end
-$var wire 1 mU in_h $end
-$var wire 1 nU in $end
-$var wire 1 NV enable_pad_vssio_q $end
-$var wire 1 OV enable_pad_vddio_q $end
-$var wire 1 PV enable_pad_amuxbus_b $end
-$var wire 1 QV enable_pad_amuxbus_a $end
-$var wire 1 RV disable_inp_buff_lv $end
-$var wire 1 SV disable_inp_buff $end
-$var wire 3 TV amux_select [2:0] $end
-$var reg 1 UV analog_en_final $end
-$var reg 1 VV analog_en_vdda $end
-$var reg 1 WV analog_en_vddio_q $end
-$var reg 1 XV analog_en_vswitch $end
-$var reg 1 YV dis_err_msgs $end
-$var reg 3 ZV dm_final [2:0] $end
-$var reg 1 [V hld_ovr_final $end
-$var reg 1 \V ib_mode_sel_final $end
-$var reg 1 ]V inp_dis_final $end
-$var reg 1 ^V notifier_dm $end
-$var reg 1 _V notifier_enable_h $end
-$var reg 1 `V notifier_hld_ovr $end
-$var reg 1 aV notifier_ib_mode_sel $end
-$var reg 1 bV notifier_inp_dis $end
-$var reg 1 cV notifier_oe_n $end
-$var reg 1 dV notifier_out $end
-$var reg 1 eV notifier_slow $end
-$var reg 1 fV notifier_vtrip_sel $end
-$var reg 1 gV oe_n_final $end
-$var reg 1 hV out_final $end
-$var reg 1 iV slow_final $end
-$var reg 1 jV vtrip_sel_final $end
-$var integer 32 kV msg_count_pad [31:0] $end
-$var integer 32 lV msg_count_pad1 [31:0] $end
-$var integer 32 mV msg_count_pad10 [31:0] $end
-$var integer 32 nV msg_count_pad11 [31:0] $end
-$var integer 32 oV msg_count_pad12 [31:0] $end
-$var integer 32 pV msg_count_pad2 [31:0] $end
-$var integer 32 qV msg_count_pad3 [31:0] $end
-$var integer 32 rV msg_count_pad4 [31:0] $end
-$var integer 32 sV msg_count_pad5 [31:0] $end
-$var integer 32 tV msg_count_pad6 [31:0] $end
-$var integer 32 uV msg_count_pad7 [31:0] $end
-$var integer 32 vV msg_count_pad8 [31:0] $end
-$var integer 32 wV msg_count_pad9 [31:0] $end
-$var integer 32 xV slow_0_delay [31:0] $end
-$var integer 32 yV slow_1_delay [31:0] $end
-$var integer 32 zV slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[20] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 {V analog_en $end
-$var wire 1 |V analog_pol $end
-$var wire 1 }V analog_sel $end
-$var wire 3 ~V dm [2:0] $end
-$var wire 1 !W enable_h $end
-$var wire 1 "W enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 #W hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 $W ib_mode_sel $end
-$var wire 1 %W inp_dis $end
-$var wire 1 &W oe_n $end
-$var wire 1 'W out $end
-$var wire 1 (W pad $end
-$var wire 1 )W pad_a_esd_0_h $end
-$var wire 1 *W pad_a_esd_1_h $end
-$var wire 1 +W pad_a_noesd_h $end
-$var wire 1 ,W slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 -W vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 .W tie_lo_esd $end
-$var wire 1 /W tie_hi_esd $end
-$var wire 1 0W in_h $end
-$var wire 1 1W in $end
-$scope module gpiov2_base $end
-$var event 1 2W event_error_vswitch5 $end
-$var event 1 3W event_error_vswitch4 $end
-$var event 1 4W event_error_vswitch3 $end
-$var event 1 5W event_error_vswitch2 $end
-$var event 1 6W event_error_vswitch1 $end
-$var event 1 7W event_error_vddio_q2 $end
-$var event 1 8W event_error_vddio_q1 $end
-$var event 1 9W event_error_vdda_vddioq_vswitch2 $end
-$var event 1 :W event_error_vdda3 $end
-$var event 1 ;W event_error_vdda2 $end
-$var event 1 <W event_error_vdda $end
-$var event 1 =W event_error_supply_good $end
-$var event 1 >W event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 {V analog_en $end
-$var wire 1 |V analog_pol $end
-$var wire 1 }V analog_sel $end
-$var wire 3 ?W dm [2:0] $end
-$var wire 3 @W dm_buf [2:0] $end
-$var wire 1 !W enable_h $end
-$var wire 1 "W enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 AW error_enable_vddio $end
-$var wire 1 BW error_supply_good $end
-$var wire 1 CW error_vdda $end
-$var wire 1 DW error_vdda2 $end
-$var wire 1 EW error_vdda3 $end
-$var wire 1 FW error_vdda_vddioq_vswitch2 $end
-$var wire 1 GW error_vddio_q1 $end
-$var wire 1 HW error_vddio_q2 $end
-$var wire 1 IW error_vswitch1 $end
-$var wire 1 JW error_vswitch2 $end
-$var wire 1 KW error_vswitch3 $end
-$var wire 1 LW error_vswitch4 $end
-$var wire 1 MW error_vswitch5 $end
-$var wire 1 NW functional_mode_amux $end
-$var wire 1 #W hld_h_n $end
-$var wire 1 OW hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 PW hld_ovr_buf $end
-$var wire 1 $W ib_mode_sel $end
-$var wire 1 QW ib_mode_sel_buf $end
-$var wire 1 %W inp_dis $end
-$var wire 1 RW inp_dis_buf $end
-$var wire 1 SW invalid_controls_amux $end
-$var wire 1 &W oe_n $end
-$var wire 1 TW oe_n_buf $end
-$var wire 1 'W out $end
-$var wire 1 UW out_buf $end
-$var wire 1 (W pad $end
-$var wire 1 )W pad_a_esd_0_h $end
-$var wire 1 *W pad_a_esd_1_h $end
-$var wire 1 +W pad_a_noesd_h $end
-$var wire 1 VW pad_tristate $end
-$var wire 1 WW pwr_good_active_mode $end
-$var wire 1 XW pwr_good_active_mode_vdda $end
-$var wire 1 YW pwr_good_amux $end
-$var wire 1 ZW pwr_good_analog_en_vdda $end
-$var wire 1 [W pwr_good_analog_en_vddio_q $end
-$var wire 1 \W pwr_good_analog_en_vswitch $end
-$var wire 1 ]W pwr_good_hold_mode $end
-$var wire 1 ^W pwr_good_hold_mode_vdda $end
-$var wire 1 _W pwr_good_hold_ovr_mode $end
-$var wire 1 `W pwr_good_inpbuff_hv $end
-$var wire 1 aW pwr_good_inpbuff_lv $end
-$var wire 1 bW pwr_good_output_driver $end
-$var wire 1 ,W slow $end
-$var wire 1 cW slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 -W vtrip_sel $end
-$var wire 1 dW vtrip_sel_buf $end
-$var wire 1 eW x_on_analog_en_vdda $end
-$var wire 1 fW x_on_analog_en_vddio_q $end
-$var wire 1 gW x_on_analog_en_vswitch $end
-$var wire 1 hW x_on_in_hv $end
-$var wire 1 iW x_on_in_lv $end
-$var wire 1 jW x_on_pad $end
-$var wire 1 kW zero_on_analog_en_vdda $end
-$var wire 1 lW zero_on_analog_en_vddio_q $end
-$var wire 1 mW zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 .W tie_lo_esd $end
-$var wire 1 /W tie_hi_esd $end
-$var wire 1 nW pwr_good_amux_vccd $end
-$var wire 1 0W in_h $end
-$var wire 1 1W in $end
-$var wire 1 oW enable_pad_vssio_q $end
-$var wire 1 pW enable_pad_vddio_q $end
-$var wire 1 qW enable_pad_amuxbus_b $end
-$var wire 1 rW enable_pad_amuxbus_a $end
-$var wire 1 sW disable_inp_buff_lv $end
-$var wire 1 tW disable_inp_buff $end
-$var wire 3 uW amux_select [2:0] $end
-$var reg 1 vW analog_en_final $end
-$var reg 1 wW analog_en_vdda $end
-$var reg 1 xW analog_en_vddio_q $end
-$var reg 1 yW analog_en_vswitch $end
-$var reg 1 zW dis_err_msgs $end
-$var reg 3 {W dm_final [2:0] $end
-$var reg 1 |W hld_ovr_final $end
-$var reg 1 }W ib_mode_sel_final $end
-$var reg 1 ~W inp_dis_final $end
-$var reg 1 !X notifier_dm $end
-$var reg 1 "X notifier_enable_h $end
-$var reg 1 #X notifier_hld_ovr $end
-$var reg 1 $X notifier_ib_mode_sel $end
-$var reg 1 %X notifier_inp_dis $end
-$var reg 1 &X notifier_oe_n $end
-$var reg 1 'X notifier_out $end
-$var reg 1 (X notifier_slow $end
-$var reg 1 )X notifier_vtrip_sel $end
-$var reg 1 *X oe_n_final $end
-$var reg 1 +X out_final $end
-$var reg 1 ,X slow_final $end
-$var reg 1 -X vtrip_sel_final $end
-$var integer 32 .X msg_count_pad [31:0] $end
-$var integer 32 /X msg_count_pad1 [31:0] $end
-$var integer 32 0X msg_count_pad10 [31:0] $end
-$var integer 32 1X msg_count_pad11 [31:0] $end
-$var integer 32 2X msg_count_pad12 [31:0] $end
-$var integer 32 3X msg_count_pad2 [31:0] $end
-$var integer 32 4X msg_count_pad3 [31:0] $end
-$var integer 32 5X msg_count_pad4 [31:0] $end
-$var integer 32 6X msg_count_pad5 [31:0] $end
-$var integer 32 7X msg_count_pad6 [31:0] $end
-$var integer 32 8X msg_count_pad7 [31:0] $end
-$var integer 32 9X msg_count_pad8 [31:0] $end
-$var integer 32 :X msg_count_pad9 [31:0] $end
-$var integer 32 ;X slow_0_delay [31:0] $end
-$var integer 32 <X slow_1_delay [31:0] $end
-$var integer 32 =X slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[21] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 >X analog_en $end
-$var wire 1 ?X analog_pol $end
-$var wire 1 @X analog_sel $end
-$var wire 3 AX dm [2:0] $end
-$var wire 1 BX enable_h $end
-$var wire 1 CX enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 DX hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 EX ib_mode_sel $end
-$var wire 1 FX inp_dis $end
-$var wire 1 GX oe_n $end
-$var wire 1 HX out $end
-$var wire 1 IX pad $end
-$var wire 1 JX pad_a_esd_0_h $end
-$var wire 1 KX pad_a_esd_1_h $end
-$var wire 1 LX pad_a_noesd_h $end
-$var wire 1 MX slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 NX vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 OX tie_lo_esd $end
-$var wire 1 PX tie_hi_esd $end
-$var wire 1 QX in_h $end
-$var wire 1 RX in $end
-$scope module gpiov2_base $end
-$var event 1 SX event_error_vswitch5 $end
-$var event 1 TX event_error_vswitch4 $end
-$var event 1 UX event_error_vswitch3 $end
-$var event 1 VX event_error_vswitch2 $end
-$var event 1 WX event_error_vswitch1 $end
-$var event 1 XX event_error_vddio_q2 $end
-$var event 1 YX event_error_vddio_q1 $end
-$var event 1 ZX event_error_vdda_vddioq_vswitch2 $end
-$var event 1 [X event_error_vdda3 $end
-$var event 1 \X event_error_vdda2 $end
-$var event 1 ]X event_error_vdda $end
-$var event 1 ^X event_error_supply_good $end
-$var event 1 _X event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 >X analog_en $end
-$var wire 1 ?X analog_pol $end
-$var wire 1 @X analog_sel $end
-$var wire 3 `X dm [2:0] $end
-$var wire 3 aX dm_buf [2:0] $end
-$var wire 1 BX enable_h $end
-$var wire 1 CX enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 bX error_enable_vddio $end
-$var wire 1 cX error_supply_good $end
-$var wire 1 dX error_vdda $end
-$var wire 1 eX error_vdda2 $end
-$var wire 1 fX error_vdda3 $end
-$var wire 1 gX error_vdda_vddioq_vswitch2 $end
-$var wire 1 hX error_vddio_q1 $end
-$var wire 1 iX error_vddio_q2 $end
-$var wire 1 jX error_vswitch1 $end
-$var wire 1 kX error_vswitch2 $end
-$var wire 1 lX error_vswitch3 $end
-$var wire 1 mX error_vswitch4 $end
-$var wire 1 nX error_vswitch5 $end
-$var wire 1 oX functional_mode_amux $end
-$var wire 1 DX hld_h_n $end
-$var wire 1 pX hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 qX hld_ovr_buf $end
-$var wire 1 EX ib_mode_sel $end
-$var wire 1 rX ib_mode_sel_buf $end
-$var wire 1 FX inp_dis $end
-$var wire 1 sX inp_dis_buf $end
-$var wire 1 tX invalid_controls_amux $end
-$var wire 1 GX oe_n $end
-$var wire 1 uX oe_n_buf $end
-$var wire 1 HX out $end
-$var wire 1 vX out_buf $end
-$var wire 1 IX pad $end
-$var wire 1 JX pad_a_esd_0_h $end
-$var wire 1 KX pad_a_esd_1_h $end
-$var wire 1 LX pad_a_noesd_h $end
-$var wire 1 wX pad_tristate $end
-$var wire 1 xX pwr_good_active_mode $end
-$var wire 1 yX pwr_good_active_mode_vdda $end
-$var wire 1 zX pwr_good_amux $end
-$var wire 1 {X pwr_good_analog_en_vdda $end
-$var wire 1 |X pwr_good_analog_en_vddio_q $end
-$var wire 1 }X pwr_good_analog_en_vswitch $end
-$var wire 1 ~X pwr_good_hold_mode $end
-$var wire 1 !Y pwr_good_hold_mode_vdda $end
-$var wire 1 "Y pwr_good_hold_ovr_mode $end
-$var wire 1 #Y pwr_good_inpbuff_hv $end
-$var wire 1 $Y pwr_good_inpbuff_lv $end
-$var wire 1 %Y pwr_good_output_driver $end
-$var wire 1 MX slow $end
-$var wire 1 &Y slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 NX vtrip_sel $end
-$var wire 1 'Y vtrip_sel_buf $end
-$var wire 1 (Y x_on_analog_en_vdda $end
-$var wire 1 )Y x_on_analog_en_vddio_q $end
-$var wire 1 *Y x_on_analog_en_vswitch $end
-$var wire 1 +Y x_on_in_hv $end
-$var wire 1 ,Y x_on_in_lv $end
-$var wire 1 -Y x_on_pad $end
-$var wire 1 .Y zero_on_analog_en_vdda $end
-$var wire 1 /Y zero_on_analog_en_vddio_q $end
-$var wire 1 0Y zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 OX tie_lo_esd $end
-$var wire 1 PX tie_hi_esd $end
-$var wire 1 1Y pwr_good_amux_vccd $end
-$var wire 1 QX in_h $end
-$var wire 1 RX in $end
-$var wire 1 2Y enable_pad_vssio_q $end
-$var wire 1 3Y enable_pad_vddio_q $end
-$var wire 1 4Y enable_pad_amuxbus_b $end
-$var wire 1 5Y enable_pad_amuxbus_a $end
-$var wire 1 6Y disable_inp_buff_lv $end
-$var wire 1 7Y disable_inp_buff $end
-$var wire 3 8Y amux_select [2:0] $end
-$var reg 1 9Y analog_en_final $end
-$var reg 1 :Y analog_en_vdda $end
-$var reg 1 ;Y analog_en_vddio_q $end
-$var reg 1 <Y analog_en_vswitch $end
-$var reg 1 =Y dis_err_msgs $end
-$var reg 3 >Y dm_final [2:0] $end
-$var reg 1 ?Y hld_ovr_final $end
-$var reg 1 @Y ib_mode_sel_final $end
-$var reg 1 AY inp_dis_final $end
-$var reg 1 BY notifier_dm $end
-$var reg 1 CY notifier_enable_h $end
-$var reg 1 DY notifier_hld_ovr $end
-$var reg 1 EY notifier_ib_mode_sel $end
-$var reg 1 FY notifier_inp_dis $end
-$var reg 1 GY notifier_oe_n $end
-$var reg 1 HY notifier_out $end
-$var reg 1 IY notifier_slow $end
-$var reg 1 JY notifier_vtrip_sel $end
-$var reg 1 KY oe_n_final $end
-$var reg 1 LY out_final $end
-$var reg 1 MY slow_final $end
-$var reg 1 NY vtrip_sel_final $end
-$var integer 32 OY msg_count_pad [31:0] $end
-$var integer 32 PY msg_count_pad1 [31:0] $end
-$var integer 32 QY msg_count_pad10 [31:0] $end
-$var integer 32 RY msg_count_pad11 [31:0] $end
-$var integer 32 SY msg_count_pad12 [31:0] $end
-$var integer 32 TY msg_count_pad2 [31:0] $end
-$var integer 32 UY msg_count_pad3 [31:0] $end
-$var integer 32 VY msg_count_pad4 [31:0] $end
-$var integer 32 WY msg_count_pad5 [31:0] $end
-$var integer 32 XY msg_count_pad6 [31:0] $end
-$var integer 32 YY msg_count_pad7 [31:0] $end
-$var integer 32 ZY msg_count_pad8 [31:0] $end
-$var integer 32 [Y msg_count_pad9 [31:0] $end
-$var integer 32 \Y slow_0_delay [31:0] $end
-$var integer 32 ]Y slow_1_delay [31:0] $end
-$var integer 32 ^Y slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[22] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 _Y analog_en $end
-$var wire 1 `Y analog_pol $end
-$var wire 1 aY analog_sel $end
-$var wire 3 bY dm [2:0] $end
-$var wire 1 cY enable_h $end
-$var wire 1 dY enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 eY hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 fY ib_mode_sel $end
-$var wire 1 gY inp_dis $end
-$var wire 1 hY oe_n $end
-$var wire 1 iY out $end
-$var wire 1 jY pad $end
-$var wire 1 kY pad_a_esd_0_h $end
-$var wire 1 lY pad_a_esd_1_h $end
-$var wire 1 mY pad_a_noesd_h $end
-$var wire 1 nY slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 oY vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 pY tie_lo_esd $end
-$var wire 1 qY tie_hi_esd $end
-$var wire 1 rY in_h $end
-$var wire 1 sY in $end
-$scope module gpiov2_base $end
-$var event 1 tY event_error_vswitch5 $end
-$var event 1 uY event_error_vswitch4 $end
-$var event 1 vY event_error_vswitch3 $end
-$var event 1 wY event_error_vswitch2 $end
-$var event 1 xY event_error_vswitch1 $end
-$var event 1 yY event_error_vddio_q2 $end
-$var event 1 zY event_error_vddio_q1 $end
-$var event 1 {Y event_error_vdda_vddioq_vswitch2 $end
-$var event 1 |Y event_error_vdda3 $end
-$var event 1 }Y event_error_vdda2 $end
-$var event 1 ~Y event_error_vdda $end
-$var event 1 !Z event_error_supply_good $end
-$var event 1 "Z event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 _Y analog_en $end
-$var wire 1 `Y analog_pol $end
-$var wire 1 aY analog_sel $end
-$var wire 3 #Z dm [2:0] $end
-$var wire 3 $Z dm_buf [2:0] $end
-$var wire 1 cY enable_h $end
-$var wire 1 dY enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 %Z error_enable_vddio $end
-$var wire 1 &Z error_supply_good $end
-$var wire 1 'Z error_vdda $end
-$var wire 1 (Z error_vdda2 $end
-$var wire 1 )Z error_vdda3 $end
-$var wire 1 *Z error_vdda_vddioq_vswitch2 $end
-$var wire 1 +Z error_vddio_q1 $end
-$var wire 1 ,Z error_vddio_q2 $end
-$var wire 1 -Z error_vswitch1 $end
-$var wire 1 .Z error_vswitch2 $end
-$var wire 1 /Z error_vswitch3 $end
-$var wire 1 0Z error_vswitch4 $end
-$var wire 1 1Z error_vswitch5 $end
-$var wire 1 2Z functional_mode_amux $end
-$var wire 1 eY hld_h_n $end
-$var wire 1 3Z hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 4Z hld_ovr_buf $end
-$var wire 1 fY ib_mode_sel $end
-$var wire 1 5Z ib_mode_sel_buf $end
-$var wire 1 gY inp_dis $end
-$var wire 1 6Z inp_dis_buf $end
-$var wire 1 7Z invalid_controls_amux $end
-$var wire 1 hY oe_n $end
-$var wire 1 8Z oe_n_buf $end
-$var wire 1 iY out $end
-$var wire 1 9Z out_buf $end
-$var wire 1 jY pad $end
-$var wire 1 kY pad_a_esd_0_h $end
-$var wire 1 lY pad_a_esd_1_h $end
-$var wire 1 mY pad_a_noesd_h $end
-$var wire 1 :Z pad_tristate $end
-$var wire 1 ;Z pwr_good_active_mode $end
-$var wire 1 <Z pwr_good_active_mode_vdda $end
-$var wire 1 =Z pwr_good_amux $end
-$var wire 1 >Z pwr_good_analog_en_vdda $end
-$var wire 1 ?Z pwr_good_analog_en_vddio_q $end
-$var wire 1 @Z pwr_good_analog_en_vswitch $end
-$var wire 1 AZ pwr_good_hold_mode $end
-$var wire 1 BZ pwr_good_hold_mode_vdda $end
-$var wire 1 CZ pwr_good_hold_ovr_mode $end
-$var wire 1 DZ pwr_good_inpbuff_hv $end
-$var wire 1 EZ pwr_good_inpbuff_lv $end
-$var wire 1 FZ pwr_good_output_driver $end
-$var wire 1 nY slow $end
-$var wire 1 GZ slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 oY vtrip_sel $end
-$var wire 1 HZ vtrip_sel_buf $end
-$var wire 1 IZ x_on_analog_en_vdda $end
-$var wire 1 JZ x_on_analog_en_vddio_q $end
-$var wire 1 KZ x_on_analog_en_vswitch $end
-$var wire 1 LZ x_on_in_hv $end
-$var wire 1 MZ x_on_in_lv $end
-$var wire 1 NZ x_on_pad $end
-$var wire 1 OZ zero_on_analog_en_vdda $end
-$var wire 1 PZ zero_on_analog_en_vddio_q $end
-$var wire 1 QZ zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 pY tie_lo_esd $end
-$var wire 1 qY tie_hi_esd $end
-$var wire 1 RZ pwr_good_amux_vccd $end
-$var wire 1 rY in_h $end
-$var wire 1 sY in $end
-$var wire 1 SZ enable_pad_vssio_q $end
-$var wire 1 TZ enable_pad_vddio_q $end
-$var wire 1 UZ enable_pad_amuxbus_b $end
-$var wire 1 VZ enable_pad_amuxbus_a $end
-$var wire 1 WZ disable_inp_buff_lv $end
-$var wire 1 XZ disable_inp_buff $end
-$var wire 3 YZ amux_select [2:0] $end
-$var reg 1 ZZ analog_en_final $end
-$var reg 1 [Z analog_en_vdda $end
-$var reg 1 \Z analog_en_vddio_q $end
-$var reg 1 ]Z analog_en_vswitch $end
-$var reg 1 ^Z dis_err_msgs $end
-$var reg 3 _Z dm_final [2:0] $end
-$var reg 1 `Z hld_ovr_final $end
-$var reg 1 aZ ib_mode_sel_final $end
-$var reg 1 bZ inp_dis_final $end
-$var reg 1 cZ notifier_dm $end
-$var reg 1 dZ notifier_enable_h $end
-$var reg 1 eZ notifier_hld_ovr $end
-$var reg 1 fZ notifier_ib_mode_sel $end
-$var reg 1 gZ notifier_inp_dis $end
-$var reg 1 hZ notifier_oe_n $end
-$var reg 1 iZ notifier_out $end
-$var reg 1 jZ notifier_slow $end
-$var reg 1 kZ notifier_vtrip_sel $end
-$var reg 1 lZ oe_n_final $end
-$var reg 1 mZ out_final $end
-$var reg 1 nZ slow_final $end
-$var reg 1 oZ vtrip_sel_final $end
-$var integer 32 pZ msg_count_pad [31:0] $end
-$var integer 32 qZ msg_count_pad1 [31:0] $end
-$var integer 32 rZ msg_count_pad10 [31:0] $end
-$var integer 32 sZ msg_count_pad11 [31:0] $end
-$var integer 32 tZ msg_count_pad12 [31:0] $end
-$var integer 32 uZ msg_count_pad2 [31:0] $end
-$var integer 32 vZ msg_count_pad3 [31:0] $end
-$var integer 32 wZ msg_count_pad4 [31:0] $end
-$var integer 32 xZ msg_count_pad5 [31:0] $end
-$var integer 32 yZ msg_count_pad6 [31:0] $end
-$var integer 32 zZ msg_count_pad7 [31:0] $end
-$var integer 32 {Z msg_count_pad8 [31:0] $end
-$var integer 32 |Z msg_count_pad9 [31:0] $end
-$var integer 32 }Z slow_0_delay [31:0] $end
-$var integer 32 ~Z slow_1_delay [31:0] $end
-$var integer 32 ![ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[23] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 "[ analog_en $end
-$var wire 1 #[ analog_pol $end
-$var wire 1 $[ analog_sel $end
-$var wire 3 %[ dm [2:0] $end
-$var wire 1 &[ enable_h $end
-$var wire 1 '[ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 ([ hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 )[ ib_mode_sel $end
-$var wire 1 *[ inp_dis $end
-$var wire 1 +[ oe_n $end
-$var wire 1 ,[ out $end
-$var wire 1 -[ pad $end
-$var wire 1 .[ pad_a_esd_0_h $end
-$var wire 1 /[ pad_a_esd_1_h $end
-$var wire 1 0[ pad_a_noesd_h $end
-$var wire 1 1[ slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 2[ vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 3[ tie_lo_esd $end
-$var wire 1 4[ tie_hi_esd $end
-$var wire 1 5[ in_h $end
-$var wire 1 6[ in $end
-$scope module gpiov2_base $end
-$var event 1 7[ event_error_vswitch5 $end
-$var event 1 8[ event_error_vswitch4 $end
-$var event 1 9[ event_error_vswitch3 $end
-$var event 1 :[ event_error_vswitch2 $end
-$var event 1 ;[ event_error_vswitch1 $end
-$var event 1 <[ event_error_vddio_q2 $end
-$var event 1 =[ event_error_vddio_q1 $end
-$var event 1 >[ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ?[ event_error_vdda3 $end
-$var event 1 @[ event_error_vdda2 $end
-$var event 1 A[ event_error_vdda $end
-$var event 1 B[ event_error_supply_good $end
-$var event 1 C[ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 "[ analog_en $end
-$var wire 1 #[ analog_pol $end
-$var wire 1 $[ analog_sel $end
-$var wire 3 D[ dm [2:0] $end
-$var wire 3 E[ dm_buf [2:0] $end
-$var wire 1 &[ enable_h $end
-$var wire 1 '[ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 F[ error_enable_vddio $end
-$var wire 1 G[ error_supply_good $end
-$var wire 1 H[ error_vdda $end
-$var wire 1 I[ error_vdda2 $end
-$var wire 1 J[ error_vdda3 $end
-$var wire 1 K[ error_vdda_vddioq_vswitch2 $end
-$var wire 1 L[ error_vddio_q1 $end
-$var wire 1 M[ error_vddio_q2 $end
-$var wire 1 N[ error_vswitch1 $end
-$var wire 1 O[ error_vswitch2 $end
-$var wire 1 P[ error_vswitch3 $end
-$var wire 1 Q[ error_vswitch4 $end
-$var wire 1 R[ error_vswitch5 $end
-$var wire 1 S[ functional_mode_amux $end
-$var wire 1 ([ hld_h_n $end
-$var wire 1 T[ hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 U[ hld_ovr_buf $end
-$var wire 1 )[ ib_mode_sel $end
-$var wire 1 V[ ib_mode_sel_buf $end
-$var wire 1 *[ inp_dis $end
-$var wire 1 W[ inp_dis_buf $end
-$var wire 1 X[ invalid_controls_amux $end
-$var wire 1 +[ oe_n $end
-$var wire 1 Y[ oe_n_buf $end
-$var wire 1 ,[ out $end
-$var wire 1 Z[ out_buf $end
-$var wire 1 -[ pad $end
-$var wire 1 .[ pad_a_esd_0_h $end
-$var wire 1 /[ pad_a_esd_1_h $end
-$var wire 1 0[ pad_a_noesd_h $end
-$var wire 1 [[ pad_tristate $end
-$var wire 1 \[ pwr_good_active_mode $end
-$var wire 1 ][ pwr_good_active_mode_vdda $end
-$var wire 1 ^[ pwr_good_amux $end
-$var wire 1 _[ pwr_good_analog_en_vdda $end
-$var wire 1 `[ pwr_good_analog_en_vddio_q $end
-$var wire 1 a[ pwr_good_analog_en_vswitch $end
-$var wire 1 b[ pwr_good_hold_mode $end
-$var wire 1 c[ pwr_good_hold_mode_vdda $end
-$var wire 1 d[ pwr_good_hold_ovr_mode $end
-$var wire 1 e[ pwr_good_inpbuff_hv $end
-$var wire 1 f[ pwr_good_inpbuff_lv $end
-$var wire 1 g[ pwr_good_output_driver $end
-$var wire 1 1[ slow $end
-$var wire 1 h[ slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 2[ vtrip_sel $end
-$var wire 1 i[ vtrip_sel_buf $end
-$var wire 1 j[ x_on_analog_en_vdda $end
-$var wire 1 k[ x_on_analog_en_vddio_q $end
-$var wire 1 l[ x_on_analog_en_vswitch $end
-$var wire 1 m[ x_on_in_hv $end
-$var wire 1 n[ x_on_in_lv $end
-$var wire 1 o[ x_on_pad $end
-$var wire 1 p[ zero_on_analog_en_vdda $end
-$var wire 1 q[ zero_on_analog_en_vddio_q $end
-$var wire 1 r[ zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 3[ tie_lo_esd $end
-$var wire 1 4[ tie_hi_esd $end
-$var wire 1 s[ pwr_good_amux_vccd $end
-$var wire 1 5[ in_h $end
-$var wire 1 6[ in $end
-$var wire 1 t[ enable_pad_vssio_q $end
-$var wire 1 u[ enable_pad_vddio_q $end
-$var wire 1 v[ enable_pad_amuxbus_b $end
-$var wire 1 w[ enable_pad_amuxbus_a $end
-$var wire 1 x[ disable_inp_buff_lv $end
-$var wire 1 y[ disable_inp_buff $end
-$var wire 3 z[ amux_select [2:0] $end
-$var reg 1 {[ analog_en_final $end
-$var reg 1 |[ analog_en_vdda $end
-$var reg 1 }[ analog_en_vddio_q $end
-$var reg 1 ~[ analog_en_vswitch $end
-$var reg 1 !\ dis_err_msgs $end
-$var reg 3 "\ dm_final [2:0] $end
-$var reg 1 #\ hld_ovr_final $end
-$var reg 1 $\ ib_mode_sel_final $end
-$var reg 1 %\ inp_dis_final $end
-$var reg 1 &\ notifier_dm $end
-$var reg 1 '\ notifier_enable_h $end
-$var reg 1 (\ notifier_hld_ovr $end
-$var reg 1 )\ notifier_ib_mode_sel $end
-$var reg 1 *\ notifier_inp_dis $end
-$var reg 1 +\ notifier_oe_n $end
-$var reg 1 ,\ notifier_out $end
-$var reg 1 -\ notifier_slow $end
-$var reg 1 .\ notifier_vtrip_sel $end
-$var reg 1 /\ oe_n_final $end
-$var reg 1 0\ out_final $end
-$var reg 1 1\ slow_final $end
-$var reg 1 2\ vtrip_sel_final $end
-$var integer 32 3\ msg_count_pad [31:0] $end
-$var integer 32 4\ msg_count_pad1 [31:0] $end
-$var integer 32 5\ msg_count_pad10 [31:0] $end
-$var integer 32 6\ msg_count_pad11 [31:0] $end
-$var integer 32 7\ msg_count_pad12 [31:0] $end
-$var integer 32 8\ msg_count_pad2 [31:0] $end
-$var integer 32 9\ msg_count_pad3 [31:0] $end
-$var integer 32 :\ msg_count_pad4 [31:0] $end
-$var integer 32 ;\ msg_count_pad5 [31:0] $end
-$var integer 32 <\ msg_count_pad6 [31:0] $end
-$var integer 32 =\ msg_count_pad7 [31:0] $end
-$var integer 32 >\ msg_count_pad8 [31:0] $end
-$var integer 32 ?\ msg_count_pad9 [31:0] $end
-$var integer 32 @\ slow_0_delay [31:0] $end
-$var integer 32 A\ slow_1_delay [31:0] $end
-$var integer 32 B\ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[24] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 C\ analog_en $end
-$var wire 1 D\ analog_pol $end
-$var wire 1 E\ analog_sel $end
-$var wire 3 F\ dm [2:0] $end
-$var wire 1 G\ enable_h $end
-$var wire 1 H\ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 I\ hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 J\ ib_mode_sel $end
-$var wire 1 K\ inp_dis $end
-$var wire 1 L\ oe_n $end
-$var wire 1 M\ out $end
-$var wire 1 N\ pad $end
-$var wire 1 O\ pad_a_esd_0_h $end
-$var wire 1 P\ pad_a_esd_1_h $end
-$var wire 1 Q\ pad_a_noesd_h $end
-$var wire 1 R\ slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 S\ vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 T\ tie_lo_esd $end
-$var wire 1 U\ tie_hi_esd $end
-$var wire 1 V\ in_h $end
-$var wire 1 W\ in $end
-$scope module gpiov2_base $end
-$var event 1 X\ event_error_vswitch5 $end
-$var event 1 Y\ event_error_vswitch4 $end
-$var event 1 Z\ event_error_vswitch3 $end
-$var event 1 [\ event_error_vswitch2 $end
-$var event 1 \\ event_error_vswitch1 $end
-$var event 1 ]\ event_error_vddio_q2 $end
-$var event 1 ^\ event_error_vddio_q1 $end
-$var event 1 _\ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 `\ event_error_vdda3 $end
-$var event 1 a\ event_error_vdda2 $end
-$var event 1 b\ event_error_vdda $end
-$var event 1 c\ event_error_supply_good $end
-$var event 1 d\ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 C\ analog_en $end
-$var wire 1 D\ analog_pol $end
-$var wire 1 E\ analog_sel $end
-$var wire 3 e\ dm [2:0] $end
-$var wire 3 f\ dm_buf [2:0] $end
-$var wire 1 G\ enable_h $end
-$var wire 1 H\ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 g\ error_enable_vddio $end
-$var wire 1 h\ error_supply_good $end
-$var wire 1 i\ error_vdda $end
-$var wire 1 j\ error_vdda2 $end
-$var wire 1 k\ error_vdda3 $end
-$var wire 1 l\ error_vdda_vddioq_vswitch2 $end
-$var wire 1 m\ error_vddio_q1 $end
-$var wire 1 n\ error_vddio_q2 $end
-$var wire 1 o\ error_vswitch1 $end
-$var wire 1 p\ error_vswitch2 $end
-$var wire 1 q\ error_vswitch3 $end
-$var wire 1 r\ error_vswitch4 $end
-$var wire 1 s\ error_vswitch5 $end
-$var wire 1 t\ functional_mode_amux $end
-$var wire 1 I\ hld_h_n $end
-$var wire 1 u\ hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 v\ hld_ovr_buf $end
-$var wire 1 J\ ib_mode_sel $end
-$var wire 1 w\ ib_mode_sel_buf $end
-$var wire 1 K\ inp_dis $end
-$var wire 1 x\ inp_dis_buf $end
-$var wire 1 y\ invalid_controls_amux $end
-$var wire 1 L\ oe_n $end
-$var wire 1 z\ oe_n_buf $end
-$var wire 1 M\ out $end
-$var wire 1 {\ out_buf $end
-$var wire 1 N\ pad $end
-$var wire 1 O\ pad_a_esd_0_h $end
-$var wire 1 P\ pad_a_esd_1_h $end
-$var wire 1 Q\ pad_a_noesd_h $end
-$var wire 1 |\ pad_tristate $end
-$var wire 1 }\ pwr_good_active_mode $end
-$var wire 1 ~\ pwr_good_active_mode_vdda $end
-$var wire 1 !] pwr_good_amux $end
-$var wire 1 "] pwr_good_analog_en_vdda $end
-$var wire 1 #] pwr_good_analog_en_vddio_q $end
-$var wire 1 $] pwr_good_analog_en_vswitch $end
-$var wire 1 %] pwr_good_hold_mode $end
-$var wire 1 &] pwr_good_hold_mode_vdda $end
-$var wire 1 '] pwr_good_hold_ovr_mode $end
-$var wire 1 (] pwr_good_inpbuff_hv $end
-$var wire 1 )] pwr_good_inpbuff_lv $end
-$var wire 1 *] pwr_good_output_driver $end
-$var wire 1 R\ slow $end
-$var wire 1 +] slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 S\ vtrip_sel $end
-$var wire 1 ,] vtrip_sel_buf $end
-$var wire 1 -] x_on_analog_en_vdda $end
-$var wire 1 .] x_on_analog_en_vddio_q $end
-$var wire 1 /] x_on_analog_en_vswitch $end
-$var wire 1 0] x_on_in_hv $end
-$var wire 1 1] x_on_in_lv $end
-$var wire 1 2] x_on_pad $end
-$var wire 1 3] zero_on_analog_en_vdda $end
-$var wire 1 4] zero_on_analog_en_vddio_q $end
-$var wire 1 5] zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 T\ tie_lo_esd $end
-$var wire 1 U\ tie_hi_esd $end
-$var wire 1 6] pwr_good_amux_vccd $end
-$var wire 1 V\ in_h $end
-$var wire 1 W\ in $end
-$var wire 1 7] enable_pad_vssio_q $end
-$var wire 1 8] enable_pad_vddio_q $end
-$var wire 1 9] enable_pad_amuxbus_b $end
-$var wire 1 :] enable_pad_amuxbus_a $end
-$var wire 1 ;] disable_inp_buff_lv $end
-$var wire 1 <] disable_inp_buff $end
-$var wire 3 =] amux_select [2:0] $end
-$var reg 1 >] analog_en_final $end
-$var reg 1 ?] analog_en_vdda $end
-$var reg 1 @] analog_en_vddio_q $end
-$var reg 1 A] analog_en_vswitch $end
-$var reg 1 B] dis_err_msgs $end
-$var reg 3 C] dm_final [2:0] $end
-$var reg 1 D] hld_ovr_final $end
-$var reg 1 E] ib_mode_sel_final $end
-$var reg 1 F] inp_dis_final $end
-$var reg 1 G] notifier_dm $end
-$var reg 1 H] notifier_enable_h $end
-$var reg 1 I] notifier_hld_ovr $end
-$var reg 1 J] notifier_ib_mode_sel $end
-$var reg 1 K] notifier_inp_dis $end
-$var reg 1 L] notifier_oe_n $end
-$var reg 1 M] notifier_out $end
-$var reg 1 N] notifier_slow $end
-$var reg 1 O] notifier_vtrip_sel $end
-$var reg 1 P] oe_n_final $end
-$var reg 1 Q] out_final $end
-$var reg 1 R] slow_final $end
-$var reg 1 S] vtrip_sel_final $end
-$var integer 32 T] msg_count_pad [31:0] $end
-$var integer 32 U] msg_count_pad1 [31:0] $end
-$var integer 32 V] msg_count_pad10 [31:0] $end
-$var integer 32 W] msg_count_pad11 [31:0] $end
-$var integer 32 X] msg_count_pad12 [31:0] $end
-$var integer 32 Y] msg_count_pad2 [31:0] $end
-$var integer 32 Z] msg_count_pad3 [31:0] $end
-$var integer 32 [] msg_count_pad4 [31:0] $end
-$var integer 32 \] msg_count_pad5 [31:0] $end
-$var integer 32 ]] msg_count_pad6 [31:0] $end
-$var integer 32 ^] msg_count_pad7 [31:0] $end
-$var integer 32 _] msg_count_pad8 [31:0] $end
-$var integer 32 `] msg_count_pad9 [31:0] $end
-$var integer 32 a] slow_0_delay [31:0] $end
-$var integer 32 b] slow_1_delay [31:0] $end
-$var integer 32 c] slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[25] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 d] analog_en $end
-$var wire 1 e] analog_pol $end
-$var wire 1 f] analog_sel $end
-$var wire 3 g] dm [2:0] $end
-$var wire 1 h] enable_h $end
-$var wire 1 i] enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 j] hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 k] ib_mode_sel $end
-$var wire 1 l] inp_dis $end
-$var wire 1 m] oe_n $end
-$var wire 1 n] out $end
-$var wire 1 o] pad $end
-$var wire 1 p] pad_a_esd_0_h $end
-$var wire 1 q] pad_a_esd_1_h $end
-$var wire 1 r] pad_a_noesd_h $end
-$var wire 1 s] slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 t] vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 u] tie_lo_esd $end
-$var wire 1 v] tie_hi_esd $end
-$var wire 1 w] in_h $end
-$var wire 1 x] in $end
-$scope module gpiov2_base $end
-$var event 1 y] event_error_vswitch5 $end
-$var event 1 z] event_error_vswitch4 $end
-$var event 1 {] event_error_vswitch3 $end
-$var event 1 |] event_error_vswitch2 $end
-$var event 1 }] event_error_vswitch1 $end
-$var event 1 ~] event_error_vddio_q2 $end
-$var event 1 !^ event_error_vddio_q1 $end
-$var event 1 "^ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 #^ event_error_vdda3 $end
-$var event 1 $^ event_error_vdda2 $end
-$var event 1 %^ event_error_vdda $end
-$var event 1 &^ event_error_supply_good $end
-$var event 1 '^ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 d] analog_en $end
-$var wire 1 e] analog_pol $end
-$var wire 1 f] analog_sel $end
-$var wire 3 (^ dm [2:0] $end
-$var wire 3 )^ dm_buf [2:0] $end
-$var wire 1 h] enable_h $end
-$var wire 1 i] enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 *^ error_enable_vddio $end
-$var wire 1 +^ error_supply_good $end
-$var wire 1 ,^ error_vdda $end
-$var wire 1 -^ error_vdda2 $end
-$var wire 1 .^ error_vdda3 $end
-$var wire 1 /^ error_vdda_vddioq_vswitch2 $end
-$var wire 1 0^ error_vddio_q1 $end
-$var wire 1 1^ error_vddio_q2 $end
-$var wire 1 2^ error_vswitch1 $end
-$var wire 1 3^ error_vswitch2 $end
-$var wire 1 4^ error_vswitch3 $end
-$var wire 1 5^ error_vswitch4 $end
-$var wire 1 6^ error_vswitch5 $end
-$var wire 1 7^ functional_mode_amux $end
-$var wire 1 j] hld_h_n $end
-$var wire 1 8^ hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 9^ hld_ovr_buf $end
-$var wire 1 k] ib_mode_sel $end
-$var wire 1 :^ ib_mode_sel_buf $end
-$var wire 1 l] inp_dis $end
-$var wire 1 ;^ inp_dis_buf $end
-$var wire 1 <^ invalid_controls_amux $end
-$var wire 1 m] oe_n $end
-$var wire 1 =^ oe_n_buf $end
-$var wire 1 n] out $end
-$var wire 1 >^ out_buf $end
-$var wire 1 o] pad $end
-$var wire 1 p] pad_a_esd_0_h $end
-$var wire 1 q] pad_a_esd_1_h $end
-$var wire 1 r] pad_a_noesd_h $end
-$var wire 1 ?^ pad_tristate $end
-$var wire 1 @^ pwr_good_active_mode $end
-$var wire 1 A^ pwr_good_active_mode_vdda $end
-$var wire 1 B^ pwr_good_amux $end
-$var wire 1 C^ pwr_good_analog_en_vdda $end
-$var wire 1 D^ pwr_good_analog_en_vddio_q $end
-$var wire 1 E^ pwr_good_analog_en_vswitch $end
-$var wire 1 F^ pwr_good_hold_mode $end
-$var wire 1 G^ pwr_good_hold_mode_vdda $end
-$var wire 1 H^ pwr_good_hold_ovr_mode $end
-$var wire 1 I^ pwr_good_inpbuff_hv $end
-$var wire 1 J^ pwr_good_inpbuff_lv $end
-$var wire 1 K^ pwr_good_output_driver $end
-$var wire 1 s] slow $end
-$var wire 1 L^ slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 t] vtrip_sel $end
-$var wire 1 M^ vtrip_sel_buf $end
-$var wire 1 N^ x_on_analog_en_vdda $end
-$var wire 1 O^ x_on_analog_en_vddio_q $end
-$var wire 1 P^ x_on_analog_en_vswitch $end
-$var wire 1 Q^ x_on_in_hv $end
-$var wire 1 R^ x_on_in_lv $end
-$var wire 1 S^ x_on_pad $end
-$var wire 1 T^ zero_on_analog_en_vdda $end
-$var wire 1 U^ zero_on_analog_en_vddio_q $end
-$var wire 1 V^ zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 u] tie_lo_esd $end
-$var wire 1 v] tie_hi_esd $end
-$var wire 1 W^ pwr_good_amux_vccd $end
-$var wire 1 w] in_h $end
-$var wire 1 x] in $end
-$var wire 1 X^ enable_pad_vssio_q $end
-$var wire 1 Y^ enable_pad_vddio_q $end
-$var wire 1 Z^ enable_pad_amuxbus_b $end
-$var wire 1 [^ enable_pad_amuxbus_a $end
-$var wire 1 \^ disable_inp_buff_lv $end
-$var wire 1 ]^ disable_inp_buff $end
-$var wire 3 ^^ amux_select [2:0] $end
-$var reg 1 _^ analog_en_final $end
-$var reg 1 `^ analog_en_vdda $end
-$var reg 1 a^ analog_en_vddio_q $end
-$var reg 1 b^ analog_en_vswitch $end
-$var reg 1 c^ dis_err_msgs $end
-$var reg 3 d^ dm_final [2:0] $end
-$var reg 1 e^ hld_ovr_final $end
-$var reg 1 f^ ib_mode_sel_final $end
-$var reg 1 g^ inp_dis_final $end
-$var reg 1 h^ notifier_dm $end
-$var reg 1 i^ notifier_enable_h $end
-$var reg 1 j^ notifier_hld_ovr $end
-$var reg 1 k^ notifier_ib_mode_sel $end
-$var reg 1 l^ notifier_inp_dis $end
-$var reg 1 m^ notifier_oe_n $end
-$var reg 1 n^ notifier_out $end
-$var reg 1 o^ notifier_slow $end
-$var reg 1 p^ notifier_vtrip_sel $end
-$var reg 1 q^ oe_n_final $end
-$var reg 1 r^ out_final $end
-$var reg 1 s^ slow_final $end
-$var reg 1 t^ vtrip_sel_final $end
-$var integer 32 u^ msg_count_pad [31:0] $end
-$var integer 32 v^ msg_count_pad1 [31:0] $end
-$var integer 32 w^ msg_count_pad10 [31:0] $end
-$var integer 32 x^ msg_count_pad11 [31:0] $end
-$var integer 32 y^ msg_count_pad12 [31:0] $end
-$var integer 32 z^ msg_count_pad2 [31:0] $end
-$var integer 32 {^ msg_count_pad3 [31:0] $end
-$var integer 32 |^ msg_count_pad4 [31:0] $end
-$var integer 32 }^ msg_count_pad5 [31:0] $end
-$var integer 32 ~^ msg_count_pad6 [31:0] $end
-$var integer 32 !_ msg_count_pad7 [31:0] $end
-$var integer 32 "_ msg_count_pad8 [31:0] $end
-$var integer 32 #_ msg_count_pad9 [31:0] $end
-$var integer 32 $_ slow_0_delay [31:0] $end
-$var integer 32 %_ slow_1_delay [31:0] $end
-$var integer 32 &_ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[26] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 '_ analog_en $end
-$var wire 1 (_ analog_pol $end
-$var wire 1 )_ analog_sel $end
-$var wire 3 *_ dm [2:0] $end
-$var wire 1 +_ enable_h $end
-$var wire 1 ,_ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 -_ hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ._ ib_mode_sel $end
-$var wire 1 /_ inp_dis $end
-$var wire 1 0_ oe_n $end
-$var wire 1 1_ out $end
-$var wire 1 2_ pad $end
-$var wire 1 3_ pad_a_esd_0_h $end
-$var wire 1 4_ pad_a_esd_1_h $end
-$var wire 1 5_ pad_a_noesd_h $end
-$var wire 1 6_ slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 7_ vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 8_ tie_lo_esd $end
-$var wire 1 9_ tie_hi_esd $end
-$var wire 1 :_ in_h $end
-$var wire 1 ;_ in $end
-$scope module gpiov2_base $end
-$var event 1 <_ event_error_vswitch5 $end
-$var event 1 =_ event_error_vswitch4 $end
-$var event 1 >_ event_error_vswitch3 $end
-$var event 1 ?_ event_error_vswitch2 $end
-$var event 1 @_ event_error_vswitch1 $end
-$var event 1 A_ event_error_vddio_q2 $end
-$var event 1 B_ event_error_vddio_q1 $end
-$var event 1 C_ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 D_ event_error_vdda3 $end
-$var event 1 E_ event_error_vdda2 $end
-$var event 1 F_ event_error_vdda $end
-$var event 1 G_ event_error_supply_good $end
-$var event 1 H_ event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 '_ analog_en $end
-$var wire 1 (_ analog_pol $end
-$var wire 1 )_ analog_sel $end
-$var wire 3 I_ dm [2:0] $end
-$var wire 3 J_ dm_buf [2:0] $end
-$var wire 1 +_ enable_h $end
-$var wire 1 ,_ enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 K_ error_enable_vddio $end
-$var wire 1 L_ error_supply_good $end
-$var wire 1 M_ error_vdda $end
-$var wire 1 N_ error_vdda2 $end
-$var wire 1 O_ error_vdda3 $end
-$var wire 1 P_ error_vdda_vddioq_vswitch2 $end
-$var wire 1 Q_ error_vddio_q1 $end
-$var wire 1 R_ error_vddio_q2 $end
-$var wire 1 S_ error_vswitch1 $end
-$var wire 1 T_ error_vswitch2 $end
-$var wire 1 U_ error_vswitch3 $end
-$var wire 1 V_ error_vswitch4 $end
-$var wire 1 W_ error_vswitch5 $end
-$var wire 1 X_ functional_mode_amux $end
-$var wire 1 -_ hld_h_n $end
-$var wire 1 Y_ hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 Z_ hld_ovr_buf $end
-$var wire 1 ._ ib_mode_sel $end
-$var wire 1 [_ ib_mode_sel_buf $end
-$var wire 1 /_ inp_dis $end
-$var wire 1 \_ inp_dis_buf $end
-$var wire 1 ]_ invalid_controls_amux $end
-$var wire 1 0_ oe_n $end
-$var wire 1 ^_ oe_n_buf $end
-$var wire 1 1_ out $end
-$var wire 1 __ out_buf $end
-$var wire 1 2_ pad $end
-$var wire 1 3_ pad_a_esd_0_h $end
-$var wire 1 4_ pad_a_esd_1_h $end
-$var wire 1 5_ pad_a_noesd_h $end
-$var wire 1 `_ pad_tristate $end
-$var wire 1 a_ pwr_good_active_mode $end
-$var wire 1 b_ pwr_good_active_mode_vdda $end
-$var wire 1 c_ pwr_good_amux $end
-$var wire 1 d_ pwr_good_analog_en_vdda $end
-$var wire 1 e_ pwr_good_analog_en_vddio_q $end
-$var wire 1 f_ pwr_good_analog_en_vswitch $end
-$var wire 1 g_ pwr_good_hold_mode $end
-$var wire 1 h_ pwr_good_hold_mode_vdda $end
-$var wire 1 i_ pwr_good_hold_ovr_mode $end
-$var wire 1 j_ pwr_good_inpbuff_hv $end
-$var wire 1 k_ pwr_good_inpbuff_lv $end
-$var wire 1 l_ pwr_good_output_driver $end
-$var wire 1 6_ slow $end
-$var wire 1 m_ slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 7_ vtrip_sel $end
-$var wire 1 n_ vtrip_sel_buf $end
-$var wire 1 o_ x_on_analog_en_vdda $end
-$var wire 1 p_ x_on_analog_en_vddio_q $end
-$var wire 1 q_ x_on_analog_en_vswitch $end
-$var wire 1 r_ x_on_in_hv $end
-$var wire 1 s_ x_on_in_lv $end
-$var wire 1 t_ x_on_pad $end
-$var wire 1 u_ zero_on_analog_en_vdda $end
-$var wire 1 v_ zero_on_analog_en_vddio_q $end
-$var wire 1 w_ zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 8_ tie_lo_esd $end
-$var wire 1 9_ tie_hi_esd $end
-$var wire 1 x_ pwr_good_amux_vccd $end
-$var wire 1 :_ in_h $end
-$var wire 1 ;_ in $end
-$var wire 1 y_ enable_pad_vssio_q $end
-$var wire 1 z_ enable_pad_vddio_q $end
-$var wire 1 {_ enable_pad_amuxbus_b $end
-$var wire 1 |_ enable_pad_amuxbus_a $end
-$var wire 1 }_ disable_inp_buff_lv $end
-$var wire 1 ~_ disable_inp_buff $end
-$var wire 3 !` amux_select [2:0] $end
-$var reg 1 "` analog_en_final $end
-$var reg 1 #` analog_en_vdda $end
-$var reg 1 $` analog_en_vddio_q $end
-$var reg 1 %` analog_en_vswitch $end
-$var reg 1 &` dis_err_msgs $end
-$var reg 3 '` dm_final [2:0] $end
-$var reg 1 (` hld_ovr_final $end
-$var reg 1 )` ib_mode_sel_final $end
-$var reg 1 *` inp_dis_final $end
-$var reg 1 +` notifier_dm $end
-$var reg 1 ,` notifier_enable_h $end
-$var reg 1 -` notifier_hld_ovr $end
-$var reg 1 .` notifier_ib_mode_sel $end
-$var reg 1 /` notifier_inp_dis $end
-$var reg 1 0` notifier_oe_n $end
-$var reg 1 1` notifier_out $end
-$var reg 1 2` notifier_slow $end
-$var reg 1 3` notifier_vtrip_sel $end
-$var reg 1 4` oe_n_final $end
-$var reg 1 5` out_final $end
-$var reg 1 6` slow_final $end
-$var reg 1 7` vtrip_sel_final $end
-$var integer 32 8` msg_count_pad [31:0] $end
-$var integer 32 9` msg_count_pad1 [31:0] $end
-$var integer 32 :` msg_count_pad10 [31:0] $end
-$var integer 32 ;` msg_count_pad11 [31:0] $end
-$var integer 32 <` msg_count_pad12 [31:0] $end
-$var integer 32 =` msg_count_pad2 [31:0] $end
-$var integer 32 >` msg_count_pad3 [31:0] $end
-$var integer 32 ?` msg_count_pad4 [31:0] $end
-$var integer 32 @` msg_count_pad5 [31:0] $end
-$var integer 32 A` msg_count_pad6 [31:0] $end
-$var integer 32 B` msg_count_pad7 [31:0] $end
-$var integer 32 C` msg_count_pad8 [31:0] $end
-$var integer 32 D` msg_count_pad9 [31:0] $end
-$var integer 32 E` slow_0_delay [31:0] $end
-$var integer 32 F` slow_1_delay [31:0] $end
-$var integer 32 G` slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[27] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 H` analog_en $end
-$var wire 1 I` analog_pol $end
-$var wire 1 J` analog_sel $end
-$var wire 3 K` dm [2:0] $end
-$var wire 1 L` enable_h $end
-$var wire 1 M` enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 N` hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 O` ib_mode_sel $end
-$var wire 1 P` inp_dis $end
-$var wire 1 Q` oe_n $end
-$var wire 1 R` out $end
-$var wire 1 S` pad $end
-$var wire 1 T` pad_a_esd_0_h $end
-$var wire 1 U` pad_a_esd_1_h $end
-$var wire 1 V` pad_a_noesd_h $end
-$var wire 1 W` slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 X` vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 Y` tie_lo_esd $end
-$var wire 1 Z` tie_hi_esd $end
-$var wire 1 [` in_h $end
-$var wire 1 \` in $end
-$scope module gpiov2_base $end
-$var event 1 ]` event_error_vswitch5 $end
-$var event 1 ^` event_error_vswitch4 $end
-$var event 1 _` event_error_vswitch3 $end
-$var event 1 `` event_error_vswitch2 $end
-$var event 1 a` event_error_vswitch1 $end
-$var event 1 b` event_error_vddio_q2 $end
-$var event 1 c` event_error_vddio_q1 $end
-$var event 1 d` event_error_vdda_vddioq_vswitch2 $end
-$var event 1 e` event_error_vdda3 $end
-$var event 1 f` event_error_vdda2 $end
-$var event 1 g` event_error_vdda $end
-$var event 1 h` event_error_supply_good $end
-$var event 1 i` event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 H` analog_en $end
-$var wire 1 I` analog_pol $end
-$var wire 1 J` analog_sel $end
-$var wire 3 j` dm [2:0] $end
-$var wire 3 k` dm_buf [2:0] $end
-$var wire 1 L` enable_h $end
-$var wire 1 M` enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 l` error_enable_vddio $end
-$var wire 1 m` error_supply_good $end
-$var wire 1 n` error_vdda $end
-$var wire 1 o` error_vdda2 $end
-$var wire 1 p` error_vdda3 $end
-$var wire 1 q` error_vdda_vddioq_vswitch2 $end
-$var wire 1 r` error_vddio_q1 $end
-$var wire 1 s` error_vddio_q2 $end
-$var wire 1 t` error_vswitch1 $end
-$var wire 1 u` error_vswitch2 $end
-$var wire 1 v` error_vswitch3 $end
-$var wire 1 w` error_vswitch4 $end
-$var wire 1 x` error_vswitch5 $end
-$var wire 1 y` functional_mode_amux $end
-$var wire 1 N` hld_h_n $end
-$var wire 1 z` hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 {` hld_ovr_buf $end
-$var wire 1 O` ib_mode_sel $end
-$var wire 1 |` ib_mode_sel_buf $end
-$var wire 1 P` inp_dis $end
-$var wire 1 }` inp_dis_buf $end
-$var wire 1 ~` invalid_controls_amux $end
-$var wire 1 Q` oe_n $end
-$var wire 1 !a oe_n_buf $end
-$var wire 1 R` out $end
-$var wire 1 "a out_buf $end
-$var wire 1 S` pad $end
-$var wire 1 T` pad_a_esd_0_h $end
-$var wire 1 U` pad_a_esd_1_h $end
-$var wire 1 V` pad_a_noesd_h $end
-$var wire 1 #a pad_tristate $end
-$var wire 1 $a pwr_good_active_mode $end
-$var wire 1 %a pwr_good_active_mode_vdda $end
-$var wire 1 &a pwr_good_amux $end
-$var wire 1 'a pwr_good_analog_en_vdda $end
-$var wire 1 (a pwr_good_analog_en_vddio_q $end
-$var wire 1 )a pwr_good_analog_en_vswitch $end
-$var wire 1 *a pwr_good_hold_mode $end
-$var wire 1 +a pwr_good_hold_mode_vdda $end
-$var wire 1 ,a pwr_good_hold_ovr_mode $end
-$var wire 1 -a pwr_good_inpbuff_hv $end
-$var wire 1 .a pwr_good_inpbuff_lv $end
-$var wire 1 /a pwr_good_output_driver $end
-$var wire 1 W` slow $end
-$var wire 1 0a slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 X` vtrip_sel $end
-$var wire 1 1a vtrip_sel_buf $end
-$var wire 1 2a x_on_analog_en_vdda $end
-$var wire 1 3a x_on_analog_en_vddio_q $end
-$var wire 1 4a x_on_analog_en_vswitch $end
-$var wire 1 5a x_on_in_hv $end
-$var wire 1 6a x_on_in_lv $end
-$var wire 1 7a x_on_pad $end
-$var wire 1 8a zero_on_analog_en_vdda $end
-$var wire 1 9a zero_on_analog_en_vddio_q $end
-$var wire 1 :a zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 Y` tie_lo_esd $end
-$var wire 1 Z` tie_hi_esd $end
-$var wire 1 ;a pwr_good_amux_vccd $end
-$var wire 1 [` in_h $end
-$var wire 1 \` in $end
-$var wire 1 <a enable_pad_vssio_q $end
-$var wire 1 =a enable_pad_vddio_q $end
-$var wire 1 >a enable_pad_amuxbus_b $end
-$var wire 1 ?a enable_pad_amuxbus_a $end
-$var wire 1 @a disable_inp_buff_lv $end
-$var wire 1 Aa disable_inp_buff $end
-$var wire 3 Ba amux_select [2:0] $end
-$var reg 1 Ca analog_en_final $end
-$var reg 1 Da analog_en_vdda $end
-$var reg 1 Ea analog_en_vddio_q $end
-$var reg 1 Fa analog_en_vswitch $end
-$var reg 1 Ga dis_err_msgs $end
-$var reg 3 Ha dm_final [2:0] $end
-$var reg 1 Ia hld_ovr_final $end
-$var reg 1 Ja ib_mode_sel_final $end
-$var reg 1 Ka inp_dis_final $end
-$var reg 1 La notifier_dm $end
-$var reg 1 Ma notifier_enable_h $end
-$var reg 1 Na notifier_hld_ovr $end
-$var reg 1 Oa notifier_ib_mode_sel $end
-$var reg 1 Pa notifier_inp_dis $end
-$var reg 1 Qa notifier_oe_n $end
-$var reg 1 Ra notifier_out $end
-$var reg 1 Sa notifier_slow $end
-$var reg 1 Ta notifier_vtrip_sel $end
-$var reg 1 Ua oe_n_final $end
-$var reg 1 Va out_final $end
-$var reg 1 Wa slow_final $end
-$var reg 1 Xa vtrip_sel_final $end
-$var integer 32 Ya msg_count_pad [31:0] $end
-$var integer 32 Za msg_count_pad1 [31:0] $end
-$var integer 32 [a msg_count_pad10 [31:0] $end
-$var integer 32 \a msg_count_pad11 [31:0] $end
-$var integer 32 ]a msg_count_pad12 [31:0] $end
-$var integer 32 ^a msg_count_pad2 [31:0] $end
-$var integer 32 _a msg_count_pad3 [31:0] $end
-$var integer 32 `a msg_count_pad4 [31:0] $end
-$var integer 32 aa msg_count_pad5 [31:0] $end
-$var integer 32 ba msg_count_pad6 [31:0] $end
-$var integer 32 ca msg_count_pad7 [31:0] $end
-$var integer 32 da msg_count_pad8 [31:0] $end
-$var integer 32 ea msg_count_pad9 [31:0] $end
-$var integer 32 fa slow_0_delay [31:0] $end
-$var integer 32 ga slow_1_delay [31:0] $end
-$var integer 32 ha slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[28] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ia analog_en $end
-$var wire 1 ja analog_pol $end
-$var wire 1 ka analog_sel $end
-$var wire 3 la dm [2:0] $end
-$var wire 1 ma enable_h $end
-$var wire 1 na enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 oa hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 pa ib_mode_sel $end
-$var wire 1 qa inp_dis $end
-$var wire 1 ra oe_n $end
-$var wire 1 sa out $end
-$var wire 1 ta pad $end
-$var wire 1 ua pad_a_esd_0_h $end
-$var wire 1 va pad_a_esd_1_h $end
-$var wire 1 wa pad_a_noesd_h $end
-$var wire 1 xa slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ya vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 za tie_lo_esd $end
-$var wire 1 {a tie_hi_esd $end
-$var wire 1 |a in_h $end
-$var wire 1 }a in $end
-$scope module gpiov2_base $end
-$var event 1 ~a event_error_vswitch5 $end
-$var event 1 !b event_error_vswitch4 $end
-$var event 1 "b event_error_vswitch3 $end
-$var event 1 #b event_error_vswitch2 $end
-$var event 1 $b event_error_vswitch1 $end
-$var event 1 %b event_error_vddio_q2 $end
-$var event 1 &b event_error_vddio_q1 $end
-$var event 1 'b event_error_vdda_vddioq_vswitch2 $end
-$var event 1 (b event_error_vdda3 $end
-$var event 1 )b event_error_vdda2 $end
-$var event 1 *b event_error_vdda $end
-$var event 1 +b event_error_supply_good $end
-$var event 1 ,b event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ia analog_en $end
-$var wire 1 ja analog_pol $end
-$var wire 1 ka analog_sel $end
-$var wire 3 -b dm [2:0] $end
-$var wire 3 .b dm_buf [2:0] $end
-$var wire 1 ma enable_h $end
-$var wire 1 na enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 /b error_enable_vddio $end
-$var wire 1 0b error_supply_good $end
-$var wire 1 1b error_vdda $end
-$var wire 1 2b error_vdda2 $end
-$var wire 1 3b error_vdda3 $end
-$var wire 1 4b error_vdda_vddioq_vswitch2 $end
-$var wire 1 5b error_vddio_q1 $end
-$var wire 1 6b error_vddio_q2 $end
-$var wire 1 7b error_vswitch1 $end
-$var wire 1 8b error_vswitch2 $end
-$var wire 1 9b error_vswitch3 $end
-$var wire 1 :b error_vswitch4 $end
-$var wire 1 ;b error_vswitch5 $end
-$var wire 1 <b functional_mode_amux $end
-$var wire 1 oa hld_h_n $end
-$var wire 1 =b hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 >b hld_ovr_buf $end
-$var wire 1 pa ib_mode_sel $end
-$var wire 1 ?b ib_mode_sel_buf $end
-$var wire 1 qa inp_dis $end
-$var wire 1 @b inp_dis_buf $end
-$var wire 1 Ab invalid_controls_amux $end
-$var wire 1 ra oe_n $end
-$var wire 1 Bb oe_n_buf $end
-$var wire 1 sa out $end
-$var wire 1 Cb out_buf $end
-$var wire 1 ta pad $end
-$var wire 1 ua pad_a_esd_0_h $end
-$var wire 1 va pad_a_esd_1_h $end
-$var wire 1 wa pad_a_noesd_h $end
-$var wire 1 Db pad_tristate $end
-$var wire 1 Eb pwr_good_active_mode $end
-$var wire 1 Fb pwr_good_active_mode_vdda $end
-$var wire 1 Gb pwr_good_amux $end
-$var wire 1 Hb pwr_good_analog_en_vdda $end
-$var wire 1 Ib pwr_good_analog_en_vddio_q $end
-$var wire 1 Jb pwr_good_analog_en_vswitch $end
-$var wire 1 Kb pwr_good_hold_mode $end
-$var wire 1 Lb pwr_good_hold_mode_vdda $end
-$var wire 1 Mb pwr_good_hold_ovr_mode $end
-$var wire 1 Nb pwr_good_inpbuff_hv $end
-$var wire 1 Ob pwr_good_inpbuff_lv $end
-$var wire 1 Pb pwr_good_output_driver $end
-$var wire 1 xa slow $end
-$var wire 1 Qb slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ya vtrip_sel $end
-$var wire 1 Rb vtrip_sel_buf $end
-$var wire 1 Sb x_on_analog_en_vdda $end
-$var wire 1 Tb x_on_analog_en_vddio_q $end
-$var wire 1 Ub x_on_analog_en_vswitch $end
-$var wire 1 Vb x_on_in_hv $end
-$var wire 1 Wb x_on_in_lv $end
-$var wire 1 Xb x_on_pad $end
-$var wire 1 Yb zero_on_analog_en_vdda $end
-$var wire 1 Zb zero_on_analog_en_vddio_q $end
-$var wire 1 [b zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 za tie_lo_esd $end
-$var wire 1 {a tie_hi_esd $end
-$var wire 1 \b pwr_good_amux_vccd $end
-$var wire 1 |a in_h $end
-$var wire 1 }a in $end
-$var wire 1 ]b enable_pad_vssio_q $end
-$var wire 1 ^b enable_pad_vddio_q $end
-$var wire 1 _b enable_pad_amuxbus_b $end
-$var wire 1 `b enable_pad_amuxbus_a $end
-$var wire 1 ab disable_inp_buff_lv $end
-$var wire 1 bb disable_inp_buff $end
-$var wire 3 cb amux_select [2:0] $end
-$var reg 1 db analog_en_final $end
-$var reg 1 eb analog_en_vdda $end
-$var reg 1 fb analog_en_vddio_q $end
-$var reg 1 gb analog_en_vswitch $end
-$var reg 1 hb dis_err_msgs $end
-$var reg 3 ib dm_final [2:0] $end
-$var reg 1 jb hld_ovr_final $end
-$var reg 1 kb ib_mode_sel_final $end
-$var reg 1 lb inp_dis_final $end
-$var reg 1 mb notifier_dm $end
-$var reg 1 nb notifier_enable_h $end
-$var reg 1 ob notifier_hld_ovr $end
-$var reg 1 pb notifier_ib_mode_sel $end
-$var reg 1 qb notifier_inp_dis $end
-$var reg 1 rb notifier_oe_n $end
-$var reg 1 sb notifier_out $end
-$var reg 1 tb notifier_slow $end
-$var reg 1 ub notifier_vtrip_sel $end
-$var reg 1 vb oe_n_final $end
-$var reg 1 wb out_final $end
-$var reg 1 xb slow_final $end
-$var reg 1 yb vtrip_sel_final $end
-$var integer 32 zb msg_count_pad [31:0] $end
-$var integer 32 {b msg_count_pad1 [31:0] $end
-$var integer 32 |b msg_count_pad10 [31:0] $end
-$var integer 32 }b msg_count_pad11 [31:0] $end
-$var integer 32 ~b msg_count_pad12 [31:0] $end
-$var integer 32 !c msg_count_pad2 [31:0] $end
-$var integer 32 "c msg_count_pad3 [31:0] $end
-$var integer 32 #c msg_count_pad4 [31:0] $end
-$var integer 32 $c msg_count_pad5 [31:0] $end
-$var integer 32 %c msg_count_pad6 [31:0] $end
-$var integer 32 &c msg_count_pad7 [31:0] $end
-$var integer 32 'c msg_count_pad8 [31:0] $end
-$var integer 32 (c msg_count_pad9 [31:0] $end
-$var integer 32 )c slow_0_delay [31:0] $end
-$var integer 32 *c slow_1_delay [31:0] $end
-$var integer 32 +c slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[29] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ,c analog_en $end
-$var wire 1 -c analog_pol $end
-$var wire 1 .c analog_sel $end
-$var wire 3 /c dm [2:0] $end
-$var wire 1 0c enable_h $end
-$var wire 1 1c enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 2c hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 3c ib_mode_sel $end
-$var wire 1 4c inp_dis $end
-$var wire 1 5c oe_n $end
-$var wire 1 6c out $end
-$var wire 1 7c pad $end
-$var wire 1 8c pad_a_esd_0_h $end
-$var wire 1 9c pad_a_esd_1_h $end
-$var wire 1 :c pad_a_noesd_h $end
-$var wire 1 ;c slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 <c vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 =c tie_lo_esd $end
-$var wire 1 >c tie_hi_esd $end
-$var wire 1 ?c in_h $end
-$var wire 1 @c in $end
-$scope module gpiov2_base $end
-$var event 1 Ac event_error_vswitch5 $end
-$var event 1 Bc event_error_vswitch4 $end
-$var event 1 Cc event_error_vswitch3 $end
-$var event 1 Dc event_error_vswitch2 $end
-$var event 1 Ec event_error_vswitch1 $end
-$var event 1 Fc event_error_vddio_q2 $end
-$var event 1 Gc event_error_vddio_q1 $end
-$var event 1 Hc event_error_vdda_vddioq_vswitch2 $end
-$var event 1 Ic event_error_vdda3 $end
-$var event 1 Jc event_error_vdda2 $end
-$var event 1 Kc event_error_vdda $end
-$var event 1 Lc event_error_supply_good $end
-$var event 1 Mc event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ,c analog_en $end
-$var wire 1 -c analog_pol $end
-$var wire 1 .c analog_sel $end
-$var wire 3 Nc dm [2:0] $end
-$var wire 3 Oc dm_buf [2:0] $end
-$var wire 1 0c enable_h $end
-$var wire 1 1c enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 Pc error_enable_vddio $end
-$var wire 1 Qc error_supply_good $end
-$var wire 1 Rc error_vdda $end
-$var wire 1 Sc error_vdda2 $end
-$var wire 1 Tc error_vdda3 $end
-$var wire 1 Uc error_vdda_vddioq_vswitch2 $end
-$var wire 1 Vc error_vddio_q1 $end
-$var wire 1 Wc error_vddio_q2 $end
-$var wire 1 Xc error_vswitch1 $end
-$var wire 1 Yc error_vswitch2 $end
-$var wire 1 Zc error_vswitch3 $end
-$var wire 1 [c error_vswitch4 $end
-$var wire 1 \c error_vswitch5 $end
-$var wire 1 ]c functional_mode_amux $end
-$var wire 1 2c hld_h_n $end
-$var wire 1 ^c hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 _c hld_ovr_buf $end
-$var wire 1 3c ib_mode_sel $end
-$var wire 1 `c ib_mode_sel_buf $end
-$var wire 1 4c inp_dis $end
-$var wire 1 ac inp_dis_buf $end
-$var wire 1 bc invalid_controls_amux $end
-$var wire 1 5c oe_n $end
-$var wire 1 cc oe_n_buf $end
-$var wire 1 6c out $end
-$var wire 1 dc out_buf $end
-$var wire 1 7c pad $end
-$var wire 1 8c pad_a_esd_0_h $end
-$var wire 1 9c pad_a_esd_1_h $end
-$var wire 1 :c pad_a_noesd_h $end
-$var wire 1 ec pad_tristate $end
-$var wire 1 fc pwr_good_active_mode $end
-$var wire 1 gc pwr_good_active_mode_vdda $end
-$var wire 1 hc pwr_good_amux $end
-$var wire 1 ic pwr_good_analog_en_vdda $end
-$var wire 1 jc pwr_good_analog_en_vddio_q $end
-$var wire 1 kc pwr_good_analog_en_vswitch $end
-$var wire 1 lc pwr_good_hold_mode $end
-$var wire 1 mc pwr_good_hold_mode_vdda $end
-$var wire 1 nc pwr_good_hold_ovr_mode $end
-$var wire 1 oc pwr_good_inpbuff_hv $end
-$var wire 1 pc pwr_good_inpbuff_lv $end
-$var wire 1 qc pwr_good_output_driver $end
-$var wire 1 ;c slow $end
-$var wire 1 rc slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 <c vtrip_sel $end
-$var wire 1 sc vtrip_sel_buf $end
-$var wire 1 tc x_on_analog_en_vdda $end
-$var wire 1 uc x_on_analog_en_vddio_q $end
-$var wire 1 vc x_on_analog_en_vswitch $end
-$var wire 1 wc x_on_in_hv $end
-$var wire 1 xc x_on_in_lv $end
-$var wire 1 yc x_on_pad $end
-$var wire 1 zc zero_on_analog_en_vdda $end
-$var wire 1 {c zero_on_analog_en_vddio_q $end
-$var wire 1 |c zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 =c tie_lo_esd $end
-$var wire 1 >c tie_hi_esd $end
-$var wire 1 }c pwr_good_amux_vccd $end
-$var wire 1 ?c in_h $end
-$var wire 1 @c in $end
-$var wire 1 ~c enable_pad_vssio_q $end
-$var wire 1 !d enable_pad_vddio_q $end
-$var wire 1 "d enable_pad_amuxbus_b $end
-$var wire 1 #d enable_pad_amuxbus_a $end
-$var wire 1 $d disable_inp_buff_lv $end
-$var wire 1 %d disable_inp_buff $end
-$var wire 3 &d amux_select [2:0] $end
-$var reg 1 'd analog_en_final $end
-$var reg 1 (d analog_en_vdda $end
-$var reg 1 )d analog_en_vddio_q $end
-$var reg 1 *d analog_en_vswitch $end
-$var reg 1 +d dis_err_msgs $end
-$var reg 3 ,d dm_final [2:0] $end
-$var reg 1 -d hld_ovr_final $end
-$var reg 1 .d ib_mode_sel_final $end
-$var reg 1 /d inp_dis_final $end
-$var reg 1 0d notifier_dm $end
-$var reg 1 1d notifier_enable_h $end
-$var reg 1 2d notifier_hld_ovr $end
-$var reg 1 3d notifier_ib_mode_sel $end
-$var reg 1 4d notifier_inp_dis $end
-$var reg 1 5d notifier_oe_n $end
-$var reg 1 6d notifier_out $end
-$var reg 1 7d notifier_slow $end
-$var reg 1 8d notifier_vtrip_sel $end
-$var reg 1 9d oe_n_final $end
-$var reg 1 :d out_final $end
-$var reg 1 ;d slow_final $end
-$var reg 1 <d vtrip_sel_final $end
-$var integer 32 =d msg_count_pad [31:0] $end
-$var integer 32 >d msg_count_pad1 [31:0] $end
-$var integer 32 ?d msg_count_pad10 [31:0] $end
-$var integer 32 @d msg_count_pad11 [31:0] $end
-$var integer 32 Ad msg_count_pad12 [31:0] $end
-$var integer 32 Bd msg_count_pad2 [31:0] $end
-$var integer 32 Cd msg_count_pad3 [31:0] $end
-$var integer 32 Dd msg_count_pad4 [31:0] $end
-$var integer 32 Ed msg_count_pad5 [31:0] $end
-$var integer 32 Fd msg_count_pad6 [31:0] $end
-$var integer 32 Gd msg_count_pad7 [31:0] $end
-$var integer 32 Hd msg_count_pad8 [31:0] $end
-$var integer 32 Id msg_count_pad9 [31:0] $end
-$var integer 32 Jd slow_0_delay [31:0] $end
-$var integer 32 Kd slow_1_delay [31:0] $end
-$var integer 32 Ld slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[30] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Md analog_en $end
-$var wire 1 Nd analog_pol $end
-$var wire 1 Od analog_sel $end
-$var wire 3 Pd dm [2:0] $end
-$var wire 1 Qd enable_h $end
-$var wire 1 Rd enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 Sd hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 Td ib_mode_sel $end
-$var wire 1 Ud inp_dis $end
-$var wire 1 Vd oe_n $end
-$var wire 1 Wd out $end
-$var wire 1 Xd pad $end
-$var wire 1 Yd pad_a_esd_0_h $end
-$var wire 1 Zd pad_a_esd_1_h $end
-$var wire 1 [d pad_a_noesd_h $end
-$var wire 1 \d slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ]d vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ^d tie_lo_esd $end
-$var wire 1 _d tie_hi_esd $end
-$var wire 1 `d in_h $end
-$var wire 1 ad in $end
-$scope module gpiov2_base $end
-$var event 1 bd event_error_vswitch5 $end
-$var event 1 cd event_error_vswitch4 $end
-$var event 1 dd event_error_vswitch3 $end
-$var event 1 ed event_error_vswitch2 $end
-$var event 1 fd event_error_vswitch1 $end
-$var event 1 gd event_error_vddio_q2 $end
-$var event 1 hd event_error_vddio_q1 $end
-$var event 1 id event_error_vdda_vddioq_vswitch2 $end
-$var event 1 jd event_error_vdda3 $end
-$var event 1 kd event_error_vdda2 $end
-$var event 1 ld event_error_vdda $end
-$var event 1 md event_error_supply_good $end
-$var event 1 nd event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Md analog_en $end
-$var wire 1 Nd analog_pol $end
-$var wire 1 Od analog_sel $end
-$var wire 3 od dm [2:0] $end
-$var wire 3 pd dm_buf [2:0] $end
-$var wire 1 Qd enable_h $end
-$var wire 1 Rd enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 qd error_enable_vddio $end
-$var wire 1 rd error_supply_good $end
-$var wire 1 sd error_vdda $end
-$var wire 1 td error_vdda2 $end
-$var wire 1 ud error_vdda3 $end
-$var wire 1 vd error_vdda_vddioq_vswitch2 $end
-$var wire 1 wd error_vddio_q1 $end
-$var wire 1 xd error_vddio_q2 $end
-$var wire 1 yd error_vswitch1 $end
-$var wire 1 zd error_vswitch2 $end
-$var wire 1 {d error_vswitch3 $end
-$var wire 1 |d error_vswitch4 $end
-$var wire 1 }d error_vswitch5 $end
-$var wire 1 ~d functional_mode_amux $end
-$var wire 1 Sd hld_h_n $end
-$var wire 1 !e hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 "e hld_ovr_buf $end
-$var wire 1 Td ib_mode_sel $end
-$var wire 1 #e ib_mode_sel_buf $end
-$var wire 1 Ud inp_dis $end
-$var wire 1 $e inp_dis_buf $end
-$var wire 1 %e invalid_controls_amux $end
-$var wire 1 Vd oe_n $end
-$var wire 1 &e oe_n_buf $end
-$var wire 1 Wd out $end
-$var wire 1 'e out_buf $end
-$var wire 1 Xd pad $end
-$var wire 1 Yd pad_a_esd_0_h $end
-$var wire 1 Zd pad_a_esd_1_h $end
-$var wire 1 [d pad_a_noesd_h $end
-$var wire 1 (e pad_tristate $end
-$var wire 1 )e pwr_good_active_mode $end
-$var wire 1 *e pwr_good_active_mode_vdda $end
-$var wire 1 +e pwr_good_amux $end
-$var wire 1 ,e pwr_good_analog_en_vdda $end
-$var wire 1 -e pwr_good_analog_en_vddio_q $end
-$var wire 1 .e pwr_good_analog_en_vswitch $end
-$var wire 1 /e pwr_good_hold_mode $end
-$var wire 1 0e pwr_good_hold_mode_vdda $end
-$var wire 1 1e pwr_good_hold_ovr_mode $end
-$var wire 1 2e pwr_good_inpbuff_hv $end
-$var wire 1 3e pwr_good_inpbuff_lv $end
-$var wire 1 4e pwr_good_output_driver $end
-$var wire 1 \d slow $end
-$var wire 1 5e slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ]d vtrip_sel $end
-$var wire 1 6e vtrip_sel_buf $end
-$var wire 1 7e x_on_analog_en_vdda $end
-$var wire 1 8e x_on_analog_en_vddio_q $end
-$var wire 1 9e x_on_analog_en_vswitch $end
-$var wire 1 :e x_on_in_hv $end
-$var wire 1 ;e x_on_in_lv $end
-$var wire 1 <e x_on_pad $end
-$var wire 1 =e zero_on_analog_en_vdda $end
-$var wire 1 >e zero_on_analog_en_vddio_q $end
-$var wire 1 ?e zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 ^d tie_lo_esd $end
-$var wire 1 _d tie_hi_esd $end
-$var wire 1 @e pwr_good_amux_vccd $end
-$var wire 1 `d in_h $end
-$var wire 1 ad in $end
-$var wire 1 Ae enable_pad_vssio_q $end
-$var wire 1 Be enable_pad_vddio_q $end
-$var wire 1 Ce enable_pad_amuxbus_b $end
-$var wire 1 De enable_pad_amuxbus_a $end
-$var wire 1 Ee disable_inp_buff_lv $end
-$var wire 1 Fe disable_inp_buff $end
-$var wire 3 Ge amux_select [2:0] $end
-$var reg 1 He analog_en_final $end
-$var reg 1 Ie analog_en_vdda $end
-$var reg 1 Je analog_en_vddio_q $end
-$var reg 1 Ke analog_en_vswitch $end
-$var reg 1 Le dis_err_msgs $end
-$var reg 3 Me dm_final [2:0] $end
-$var reg 1 Ne hld_ovr_final $end
-$var reg 1 Oe ib_mode_sel_final $end
-$var reg 1 Pe inp_dis_final $end
-$var reg 1 Qe notifier_dm $end
-$var reg 1 Re notifier_enable_h $end
-$var reg 1 Se notifier_hld_ovr $end
-$var reg 1 Te notifier_ib_mode_sel $end
-$var reg 1 Ue notifier_inp_dis $end
-$var reg 1 Ve notifier_oe_n $end
-$var reg 1 We notifier_out $end
-$var reg 1 Xe notifier_slow $end
-$var reg 1 Ye notifier_vtrip_sel $end
-$var reg 1 Ze oe_n_final $end
-$var reg 1 [e out_final $end
-$var reg 1 \e slow_final $end
-$var reg 1 ]e vtrip_sel_final $end
-$var integer 32 ^e msg_count_pad [31:0] $end
-$var integer 32 _e msg_count_pad1 [31:0] $end
-$var integer 32 `e msg_count_pad10 [31:0] $end
-$var integer 32 ae msg_count_pad11 [31:0] $end
-$var integer 32 be msg_count_pad12 [31:0] $end
-$var integer 32 ce msg_count_pad2 [31:0] $end
-$var integer 32 de msg_count_pad3 [31:0] $end
-$var integer 32 ee msg_count_pad4 [31:0] $end
-$var integer 32 fe msg_count_pad5 [31:0] $end
-$var integer 32 ge msg_count_pad6 [31:0] $end
-$var integer 32 he msg_count_pad7 [31:0] $end
-$var integer 32 ie msg_count_pad8 [31:0] $end
-$var integer 32 je msg_count_pad9 [31:0] $end
-$var integer 32 ke slow_0_delay [31:0] $end
-$var integer 32 le slow_1_delay [31:0] $end
-$var integer 32 me slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module io_pad[31] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ne analog_en $end
-$var wire 1 oe analog_pol $end
-$var wire 1 pe analog_sel $end
-$var wire 3 qe dm [2:0] $end
-$var wire 1 re enable_h $end
-$var wire 1 se enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 te hld_h_n $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 ue ib_mode_sel $end
-$var wire 1 ve inp_dis $end
-$var wire 1 we oe_n $end
-$var wire 1 xe out $end
-$var wire 1 ye pad $end
-$var wire 1 ze pad_a_esd_0_h $end
-$var wire 1 {e pad_a_esd_1_h $end
-$var wire 1 |e pad_a_noesd_h $end
-$var wire 1 }e slow $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ~e vtrip_sel $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 !f tie_lo_esd $end
-$var wire 1 "f tie_hi_esd $end
-$var wire 1 #f in_h $end
-$var wire 1 $f in $end
-$scope module gpiov2_base $end
-$var event 1 %f event_error_vswitch5 $end
-$var event 1 &f event_error_vswitch4 $end
-$var event 1 'f event_error_vswitch3 $end
-$var event 1 (f event_error_vswitch2 $end
-$var event 1 )f event_error_vswitch1 $end
-$var event 1 *f event_error_vddio_q2 $end
-$var event 1 +f event_error_vddio_q1 $end
-$var event 1 ,f event_error_vdda_vddioq_vswitch2 $end
-$var event 1 -f event_error_vdda3 $end
-$var event 1 .f event_error_vdda2 $end
-$var event 1 /f event_error_vdda $end
-$var event 1 0f event_error_supply_good $end
-$var event 1 1f event_error_enable_vddio $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ne analog_en $end
-$var wire 1 oe analog_pol $end
-$var wire 1 pe analog_sel $end
-$var wire 3 2f dm [2:0] $end
-$var wire 3 3f dm_buf [2:0] $end
-$var wire 1 re enable_h $end
-$var wire 1 se enable_inp_h $end
-$var wire 1 s; enable_vdda_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' enable_vswitch_h $end
-$var wire 1 4f error_enable_vddio $end
-$var wire 1 5f error_supply_good $end
-$var wire 1 6f error_vdda $end
-$var wire 1 7f error_vdda2 $end
-$var wire 1 8f error_vdda3 $end
-$var wire 1 9f error_vdda_vddioq_vswitch2 $end
-$var wire 1 :f error_vddio_q1 $end
-$var wire 1 ;f error_vddio_q2 $end
-$var wire 1 <f error_vswitch1 $end
-$var wire 1 =f error_vswitch2 $end
-$var wire 1 >f error_vswitch3 $end
-$var wire 1 ?f error_vswitch4 $end
-$var wire 1 @f error_vswitch5 $end
-$var wire 1 Af functional_mode_amux $end
-$var wire 1 te hld_h_n $end
-$var wire 1 Bf hld_h_n_buf $end
-$var wire 1 l; hld_ovr $end
-$var wire 1 Cf hld_ovr_buf $end
-$var wire 1 ue ib_mode_sel $end
-$var wire 1 Df ib_mode_sel_buf $end
-$var wire 1 ve inp_dis $end
-$var wire 1 Ef inp_dis_buf $end
-$var wire 1 Ff invalid_controls_amux $end
-$var wire 1 we oe_n $end
-$var wire 1 Gf oe_n_buf $end
-$var wire 1 xe out $end
-$var wire 1 Hf out_buf $end
-$var wire 1 ye pad $end
-$var wire 1 ze pad_a_esd_0_h $end
-$var wire 1 {e pad_a_esd_1_h $end
-$var wire 1 |e pad_a_noesd_h $end
-$var wire 1 If pad_tristate $end
-$var wire 1 Jf pwr_good_active_mode $end
-$var wire 1 Kf pwr_good_active_mode_vdda $end
-$var wire 1 Lf pwr_good_amux $end
-$var wire 1 Mf pwr_good_analog_en_vdda $end
-$var wire 1 Nf pwr_good_analog_en_vddio_q $end
-$var wire 1 Of pwr_good_analog_en_vswitch $end
-$var wire 1 Pf pwr_good_hold_mode $end
-$var wire 1 Qf pwr_good_hold_mode_vdda $end
-$var wire 1 Rf pwr_good_hold_ovr_mode $end
-$var wire 1 Sf pwr_good_inpbuff_hv $end
-$var wire 1 Tf pwr_good_inpbuff_lv $end
-$var wire 1 Uf pwr_good_output_driver $end
-$var wire 1 }e slow $end
-$var wire 1 Vf slow_buf $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 u; vdda $end
-$var wire 1 & vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 u; vswitch $end
-$var wire 1 ~e vtrip_sel $end
-$var wire 1 Wf vtrip_sel_buf $end
-$var wire 1 Xf x_on_analog_en_vdda $end
-$var wire 1 Yf x_on_analog_en_vddio_q $end
-$var wire 1 Zf x_on_analog_en_vswitch $end
-$var wire 1 [f x_on_in_hv $end
-$var wire 1 \f x_on_in_lv $end
-$var wire 1 ]f x_on_pad $end
-$var wire 1 ^f zero_on_analog_en_vdda $end
-$var wire 1 _f zero_on_analog_en_vddio_q $end
-$var wire 1 `f zero_on_analog_en_vswitch $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 !f tie_lo_esd $end
-$var wire 1 "f tie_hi_esd $end
-$var wire 1 af pwr_good_amux_vccd $end
-$var wire 1 #f in_h $end
-$var wire 1 $f in $end
-$var wire 1 bf enable_pad_vssio_q $end
-$var wire 1 cf enable_pad_vddio_q $end
-$var wire 1 df enable_pad_amuxbus_b $end
-$var wire 1 ef enable_pad_amuxbus_a $end
-$var wire 1 ff disable_inp_buff_lv $end
-$var wire 1 gf disable_inp_buff $end
-$var wire 3 hf amux_select [2:0] $end
-$var reg 1 if analog_en_final $end
-$var reg 1 jf analog_en_vdda $end
-$var reg 1 kf analog_en_vddio_q $end
-$var reg 1 lf analog_en_vswitch $end
-$var reg 1 mf dis_err_msgs $end
-$var reg 3 nf dm_final [2:0] $end
-$var reg 1 of hld_ovr_final $end
-$var reg 1 pf ib_mode_sel_final $end
-$var reg 1 qf inp_dis_final $end
-$var reg 1 rf notifier_dm $end
-$var reg 1 sf notifier_enable_h $end
-$var reg 1 tf notifier_hld_ovr $end
-$var reg 1 uf notifier_ib_mode_sel $end
-$var reg 1 vf notifier_inp_dis $end
-$var reg 1 wf notifier_oe_n $end
-$var reg 1 xf notifier_out $end
-$var reg 1 yf notifier_slow $end
-$var reg 1 zf notifier_vtrip_sel $end
-$var reg 1 {f oe_n_final $end
-$var reg 1 |f out_final $end
-$var reg 1 }f slow_final $end
-$var reg 1 ~f vtrip_sel_final $end
-$var integer 32 !g msg_count_pad [31:0] $end
-$var integer 32 "g msg_count_pad1 [31:0] $end
-$var integer 32 #g msg_count_pad10 [31:0] $end
-$var integer 32 $g msg_count_pad11 [31:0] $end
-$var integer 32 %g msg_count_pad12 [31:0] $end
-$var integer 32 &g msg_count_pad2 [31:0] $end
-$var integer 32 'g msg_count_pad3 [31:0] $end
-$var integer 32 (g msg_count_pad4 [31:0] $end
-$var integer 32 )g msg_count_pad5 [31:0] $end
-$var integer 32 *g msg_count_pad6 [31:0] $end
-$var integer 32 +g msg_count_pad7 [31:0] $end
-$var integer 32 ,g msg_count_pad8 [31:0] $end
-$var integer 32 -g msg_count_pad9 [31:0] $end
-$var integer 32 .g slow_0_delay [31:0] $end
-$var integer 32 /g slow_1_delay [31:0] $end
-$var integer 32 0g slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module resetb_pad $end
-$var event 1 1g event_errflag_pad_pulse_width $end
-$var event 1 2g event_errflag_filt_in_h_pulse_width $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ' disable_pullup_h $end
-$var wire 1 ' en_vddio_sig_h $end
-$var wire 1 & enable_h $end
-$var wire 1 % enable_vddio $end
-$var wire 1 ' filt_in_h $end
-$var wire 1 ' inp_sel_h $end
-$var wire 1 3g mode_vcchib $end
-$var wire 1 ] pad $end
-$var wire 1 J4 pad_a_esd_h $end
-$var wire 1 ' pullup_h $end
-$var wire 1 4g pwr_good_pullup $end
-$var wire 1 5g pwr_good_xres_h_n $end
-$var wire 1 6g pwr_good_xres_tmp $end
-$var wire 1 7g tie_hi_esd $end
-$var wire 1 8g tie_lo_esd $end
-$var wire 1 J4 tie_weak_hi_h $end
-$var wire 1 9g tmp $end
-$var wire 1 :g tmp1 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 ;g x_on_xres_h_n $end
-$var wire 1 <g xres_tmp $end
-$var wire 1 j xres_h_n $end
-$var wire 1 K4 vssio_q $end
-$var reg 1 =g corrupt_enable $end
-$var reg 1 >g dis_err_msgs $end
-$var reg 1 ?g notifier_enable_h $end
-$var integer 32 @g disable_enable_vddio_change_x [31:0] $end
-$var real 1 Ag filt_in_h_pulse_width $end
-$var integer 32 Bg max_delay [31:0] $end
-$var integer 32 Cg min_delay [31:0] $end
-$var integer 32 Dg msg_count_filt_in_h [31:0] $end
-$var integer 32 Eg msg_count_pad [31:0] $end
-$var real 1 Fg pad_pulse_width $end
-$var real 1 Gg t_filt_in_h_current_transition $end
-$var real 1 Hg t_filt_in_h_prev_transition $end
-$var real 1 Ig t_pad_current_transition $end
-$var real 1 Jg t_pad_prev_transition $end
-$upscope $end
-$scope module vdd1v8hclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Kg drn_hvc $end
-$var wire 1 Lg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Kg drn_hvc $end
-$var wire 1 Mg ogc_hvc $end
-$var wire 1 Ng p_core $end
-$var wire 1 % p_pad $end
-$var wire 1 Lg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd1v8hclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Og drn_hvc $end
-$var wire 1 Pg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Og drn_hvc $end
-$var wire 1 Qg ogc_hvc $end
-$var wire 1 Rg p_core $end
-$var wire 1 % p_pad $end
-$var wire 1 Pg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd1v8lclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Sg bdy2_b2b $end
-$var wire 1 Tg drn_lvc1 $end
-$var wire 1 Ug drn_lvc2 $end
-$var wire 1 Vg src_bdy_lvc1 $end
-$var wire 1 Wg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Sg bdy2_b2b $end
-$var wire 1 Tg drn_lvc1 $end
-$var wire 1 Ug drn_lvc2 $end
-$var wire 1 Xg ogc_lvc $end
-$var wire 1 Yg p_core $end
-$var wire 1 % p_pad $end
-$var wire 1 Vg src_bdy_lvc1 $end
-$var wire 1 Wg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd1v8lclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Zg bdy2_b2b $end
-$var wire 1 [g drn_lvc1 $end
-$var wire 1 \g drn_lvc2 $end
-$var wire 1 ]g src_bdy_lvc1 $end
-$var wire 1 ^g src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Zg bdy2_b2b $end
-$var wire 1 [g drn_lvc1 $end
-$var wire 1 \g drn_lvc2 $end
-$var wire 1 _g ogc_lvc $end
-$var wire 1 `g p_core $end
-$var wire 1 % p_pad $end
-$var wire 1 ]g src_bdy_lvc1 $end
-$var wire 1 ^g src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3hclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ag drn_hvc $end
-$var wire 1 bg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ag drn_hvc $end
-$var wire 1 cg ogc_hvc $end
-$var wire 1 dg p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 bg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3hclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 eg drn_hvc $end
-$var wire 1 fg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 eg drn_hvc $end
-$var wire 1 gg ogc_hvc $end
-$var wire 1 hg p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 fg src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3lclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ig bdy2_b2b $end
-$var wire 1 jg drn_lvc1 $end
-$var wire 1 kg drn_lvc2 $end
-$var wire 1 lg src_bdy_lvc1 $end
-$var wire 1 mg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ig bdy2_b2b $end
-$var wire 1 jg drn_lvc1 $end
-$var wire 1 kg drn_lvc2 $end
-$var wire 1 ng ogc_lvc $end
-$var wire 1 og p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 lg src_bdy_lvc1 $end
-$var wire 1 mg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3lclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 pg bdy2_b2b $end
-$var wire 1 qg drn_lvc1 $end
-$var wire 1 rg drn_lvc2 $end
-$var wire 1 sg src_bdy_lvc1 $end
-$var wire 1 tg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 pg bdy2_b2b $end
-$var wire 1 qg drn_lvc1 $end
-$var wire 1 rg drn_lvc2 $end
-$var wire 1 ug ogc_lvc $end
-$var wire 1 vg p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 sg src_bdy_lvc1 $end
-$var wire 1 tg src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3lclamp[2] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 wg bdy2_b2b $end
-$var wire 1 xg drn_lvc1 $end
-$var wire 1 yg drn_lvc2 $end
-$var wire 1 zg src_bdy_lvc1 $end
-$var wire 1 {g src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 wg bdy2_b2b $end
-$var wire 1 xg drn_lvc1 $end
-$var wire 1 yg drn_lvc2 $end
-$var wire 1 |g ogc_lvc $end
-$var wire 1 }g p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 zg src_bdy_lvc1 $end
-$var wire 1 {g src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vdd3v3lclamp[3] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ~g bdy2_b2b $end
-$var wire 1 !h drn_lvc1 $end
-$var wire 1 "h drn_lvc2 $end
-$var wire 1 #h src_bdy_lvc1 $end
-$var wire 1 $h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 ~g bdy2_b2b $end
-$var wire 1 !h drn_lvc1 $end
-$var wire 1 "h drn_lvc2 $end
-$var wire 1 %h ogc_lvc $end
-$var wire 1 &h p_core $end
-$var wire 1 & p_pad $end
-$var wire 1 #h src_bdy_lvc1 $end
-$var wire 1 $h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vddiohclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 'h drn_hvc $end
-$var wire 1 (h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 'h drn_hvc $end
-$var wire 1 )h ogc_hvc $end
-$var wire 1 *h p_core $end
-$var wire 1 H4 p_pad $end
-$var wire 1 (h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vddiohclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 +h drn_hvc $end
-$var wire 1 ,h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_power_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 +h drn_hvc $end
-$var wire 1 -h ogc_hvc $end
-$var wire 1 .h p_core $end
-$var wire 1 H4 p_pad $end
-$var wire 1 ,h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vssalclamp $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 /h bdy2_b2b $end
-$var wire 1 0h drn_lvc1 $end
-$var wire 1 1h drn_lvc2 $end
-$var wire 1 2h src_bdy_lvc1 $end
-$var wire 1 3h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 /h bdy2_b2b $end
-$var wire 1 0h drn_lvc1 $end
-$var wire 1 1h drn_lvc2 $end
-$var wire 1 4h g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 5h ogc_lvc $end
-$var wire 1 2h src_bdy_lvc1 $end
-$var wire 1 3h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vssdlclamp $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 6h bdy2_b2b $end
-$var wire 1 7h drn_lvc1 $end
-$var wire 1 8h drn_lvc2 $end
-$var wire 1 9h src_bdy_lvc1 $end
-$var wire 1 :h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 6h bdy2_b2b $end
-$var wire 1 7h drn_lvc1 $end
-$var wire 1 8h drn_lvc2 $end
-$var wire 1 ;h g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 <h ogc_lvc $end
-$var wire 1 9h src_bdy_lvc1 $end
-$var wire 1 :h src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vsshclamp[0] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 =h drn_hvc $end
-$var wire 1 >h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 =h drn_hvc $end
-$var wire 1 ?h g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 @h ogc_hvc $end
-$var wire 1 >h src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vsshclamp[1] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Ah drn_hvc $end
-$var wire 1 Bh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Ah drn_hvc $end
-$var wire 1 Ch g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 Dh ogc_hvc $end
-$var wire 1 Bh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vsshclamp[2] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Eh drn_hvc $end
-$var wire 1 Fh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Eh drn_hvc $end
-$var wire 1 Gh g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 Hh ogc_hvc $end
-$var wire 1 Fh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vsshclamp[3] $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Ih drn_hvc $end
-$var wire 1 Jh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$scope module s8iom0s8_top_ground_hvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Ih drn_hvc $end
-$var wire 1 Kh g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 Lh ogc_hvc $end
-$var wire 1 Jh src_bdy_hvc $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 & vswitch $end
-$var wire 1 K4 vssio_q $end
-$upscope $end
-$upscope $end
-$scope module vssiolclamp $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Mh bdy2_b2b $end
-$var wire 1 Nh drn_lvc1 $end
-$var wire 1 Oh drn_lvc2 $end
-$var wire 1 Ph src_bdy_lvc1 $end
-$var wire 1 Qh src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 & vswitch $end
-$scope module s8iom0s8_top_ground_lvc_base $end
-$var wire 1 74 amuxbus_a $end
-$var wire 1 84 amuxbus_b $end
-$var wire 1 Mh bdy2_b2b $end
-$var wire 1 Nh drn_lvc1 $end
-$var wire 1 Oh drn_lvc2 $end
-$var wire 1 Rh g_core $end
-$var wire 1 ' g_pad $end
-$var wire 1 Sh ogc_lvc $end
-$var wire 1 Ph src_bdy_lvc1 $end
-$var wire 1 Qh src_bdy_lvc2 $end
-$var wire 1 % vccd $end
-$var wire 1 % vcchib $end
-$var wire 1 & vdda $end
-$var wire 1 H4 vddio $end
-$var wire 1 I4 vddio_q $end
-$var wire 1 ' vssa $end
-$var wire 1 ' vssd $end
-$var wire 1 ' vssio $end
-$var wire 1 K4 vssio_q $end
-$var wire 1 & vswitch $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module soc $end
-$var wire 1 7" clock $end
-$var wire 1 Th ext_clk $end
-$var wire 1 O flash_clk_ieb $end
-$var wire 1 P flash_csb_ieb $end
-$var wire 1 2" flash_io0_di $end
-$var wire 1 ." flash_io1_di $end
-$var wire 1 Uh flash_io2_di $end
-$var wire 1 Vh flash_io3_di $end
-$var wire 1 *" gpio_in_pad $end
-$var wire 128 Wh la_input [127:0] $end
-$var wire 32 Xh mgmt_io_data [31:0] $end
-$var wire 1 R mprj_ack_i $end
-$var wire 32 Yh mprj_adr_o [31:0] $end
-$var wire 1 T mprj_cyc_o $end
-$var wire 32 Zh mprj_dat_i [31:0] $end
-$var wire 32 [h mprj_dat_o [31:0] $end
-$var wire 4 \h mprj_sel_o [3:0] $end
-$var wire 1 \ mprj_we_o $end
-$var wire 1 ]h pass_thru_mgmt_sdo $end
-$var wire 1 i porb $end
-$var wire 1 ^h spi_sdi $end
-$var wire 1 ` xbar_ack_i $end
-$var wire 32 _h xbar_dat_i [31:0] $end
-$var wire 1 b xbar_we_o $end
-$var wire 1 c xbar_stb_o $end
-$var wire 4 `h xbar_sel_o [3:0] $end
-$var wire 32 ah xbar_dat_o [31:0] $end
-$var wire 1 f xbar_cyc_o $end
-$var wire 32 bh xbar_adr_o [31:0] $end
-$var wire 1 ch trap $end
-$var wire 1 dh spi_sdo $end
-$var wire 1 eh spi_sck $end
-$var wire 26 fh spi_pll_trim [25:0] $end
-$var wire 3 gh spi_pll_sel [2:0] $end
-$var wire 5 hh spi_pll_div [4:0] $end
-$var wire 1 ih spi_pll_dco_ena $end
-$var wire 1 jh spi_csb $end
-$var wire 1 kh pll_clk_core90 $end
-$var wire 1 lh pll_clk_core0 $end
-$var wire 1 mh pll_clk8 $end
-$var wire 1 nh pll_clk4 $end
-$var wire 1 oh pll_clk2 $end
-$var wire 1 k pll_clk16 $end
-$var wire 1 ph pll_clk $end
-$var wire 1 qh pass_thru_reset $end
-$var wire 1 rh pass_thru_mgmt_sdi $end
-$var wire 1 sh pass_thru_mgmt_sck $end
-$var wire 1 th pass_thru_mgmt_csb $end
-$var wire 1 l mprj_stb_o $end
-$var wire 1 p mprj_io_loader_resetn $end
-$var wire 1 q mprj_io_loader_data $end
-$var wire 1 r mprj_io_loader_clock $end
-$var wire 32 uh mask_rev [31:0] $end
-$var wire 128 vh la_output [127:0] $end
-$var wire 128 wh la_oen [127:0] $end
-$var wire 1 xh irq_spi $end
-$var wire 1 %" gpio_outenb_pad $end
-$var wire 1 &" gpio_out_pad $end
-$var wire 1 '" gpio_mode1_pad $end
-$var wire 1 (" gpio_mode0_pad $end
-$var wire 1 )" gpio_inenb_pad $end
-$var wire 1 yh flash_io3_oeb $end
-$var wire 1 zh flash_io3_ieb $end
-$var wire 1 {h flash_io3_do $end
-$var wire 1 |h flash_io2_oeb $end
-$var wire 1 }h flash_io2_ieb $end
-$var wire 1 ~h flash_io2_do $end
-$var wire 1 +" flash_io1_oeb $end
-$var wire 1 ," flash_io1_ieb $end
-$var wire 1 -" flash_io1_do $end
-$var wire 1 /" flash_io0_oeb $end
-$var wire 1 0" flash_io0_ieb $end
-$var wire 1 1" flash_io0_do $end
-$var wire 1 3" flash_csb_oeb $end
-$var wire 1 4" flash_csb $end
-$var wire 1 5" flash_clk_oeb $end
-$var wire 1 6" flash_clk $end
-$var wire 1 !i ext_reset $end
-$var wire 1 "i ext_clk_sel $end
-$var wire 1 8" core_rstn $end
-$var wire 1 9" core_clk $end
-$scope module clkrst $end
-$var wire 1 Th ext_clk $end
-$var wire 1 i resetb $end
-$var wire 1 8" resetb_sync $end
-$var wire 1 ph pll_clk $end
-$var wire 1 !i ext_reset $end
-$var wire 1 "i ext_clk_sel $end
-$var wire 1 9" core_clk $end
-$var reg 3 #i reset_delay [2:0] $end
-$upscope $end
-$scope module housekeeping $end
-$var wire 1 $i CSB $end
-$var wire 1 i RSTB $end
-$var wire 1 %i SCK $end
-$var wire 1 &i SDI $end
-$var wire 32 'i mask_rev [31:0] $end
-$var wire 12 (i mfgr_id [11:0] $end
-$var wire 1 )i mgmt_csb $end
-$var wire 1 *i mgmt_sck $end
-$var wire 1 +i mgmt_sdi $end
-$var wire 1 th pass_thru_mgmt_csb $end
-$var wire 1 ]h pass_thru_mgmt_sdo $end
-$var wire 1 ,i pass_thru_user_csb $end
-$var wire 1 -i pass_thru_user_sdo $end
-$var wire 8 .i prod_id [7:0] $end
-$var wire 1 /i wrstb $end
-$var wire 1 ch trap $end
-$var wire 1 0i sdo_enb $end
-$var wire 1 !i reset $end
-$var wire 1 1i rdstb $end
-$var wire 1 2i pass_thru_user_sdi $end
-$var wire 1 3i pass_thru_user_sck $end
-$var wire 1 4i pass_thru_user_delay $end
-$var wire 1 5i pass_thru_user $end
-$var wire 1 qh pass_thru_reset $end
-$var wire 1 rh pass_thru_mgmt_sdi $end
-$var wire 1 sh pass_thru_mgmt_sck $end
-$var wire 1 6i pass_thru_mgmt_delay $end
-$var wire 1 7i pass_thru_mgmt $end
-$var wire 8 8i odata [7:0] $end
-$var wire 1 9i mgmt_sdo $end
-$var wire 32 :i mask_rev_in [31:0] $end
-$var wire 1 ;i loc_sdoenb $end
-$var wire 1 <i loc_sdo $end
-$var wire 1 =i loc_sdi $end
-$var wire 1 >i loc_sck $end
-$var wire 1 ?i loc_csb $end
-$var wire 8 @i idata [7:0] $end
-$var wire 8 Ai iaddr [7:0] $end
-$var wire 1 Bi SDO $end
-$var reg 1 xh irq $end
-$var reg 1 "i pll_bypass $end
-$var reg 1 ih pll_dco_ena $end
-$var reg 5 Ci pll_div [4:0] $end
-$var reg 3 Di pll_sel [2:0] $end
-$var reg 26 Ei pll_trim [25:0] $end
-$var reg 1 Fi reset_reg $end
-$scope module U1 $end
-$var wire 1 ?i CSB $end
-$var wire 1 >i SCK $end
-$var wire 1 =i SDI $end
-$var wire 1 Gi csb_reset $end
-$var wire 8 Hi idata [7:0] $end
-$var wire 1 qh pass_thru_reset $end
-$var wire 1 Ii reset $end
-$var wire 8 Ji odata [7:0] $end
-$var wire 8 Ki oaddr [7:0] $end
-$var wire 1 <i SDO $end
-$var reg 8 Li addr [7:0] $end
-$var reg 3 Mi count [2:0] $end
-$var reg 3 Ni fixed [2:0] $end
-$var reg 8 Oi ldata [7:0] $end
-$var reg 1 7i pass_thru_mgmt $end
-$var reg 1 6i pass_thru_mgmt_delay $end
-$var reg 1 5i pass_thru_user $end
-$var reg 1 4i pass_thru_user_delay $end
-$var reg 1 Pi pre_pass_thru_mgmt $end
-$var reg 1 Qi pre_pass_thru_user $end
-$var reg 7 Ri predata [6:0] $end
-$var reg 1 1i rdstb $end
-$var reg 1 Si readmode $end
-$var reg 1 ;i sdoenb $end
-$var reg 3 Ti state [2:0] $end
-$var reg 1 Ui writemode $end
-$var reg 1 /i wrstb $end
-$upscope $end
-$upscope $end
-$scope module pll $end
-$var wire 1 ih dco $end
-$var wire 5 Vi div [4:0] $end
-$var wire 26 Wi ext_trim [25:0] $end
-$var wire 1 "i extclk_sel $end
-$var wire 1 Xi ireset $end
-$var wire 1 7" osc $end
-$var wire 1 Yi reset $end
-$var wire 1 i resetb $end
-$var wire 3 Zi sel [2:0] $end
-$var wire 1 [i resetbb $end
-$var wire 26 \i otrim [25:0] $end
-$var wire 4 ]i nint [3:0] $end
-$var wire 26 ^i itrim [25:0] $end
-$var wire 1 _i creset $end
-$var wire 2 `i clockp [1:0] $end
-$var wire 4 ai clockd [3:0] $end
-$var wire 1 ph clockc $end
-$scope module idiv16 $end
-$var wire 1 bi CLK $end
-$var wire 1 ci D $end
-$var wire 1 di VGND $end
-$var wire 1 ei VNB $end
-$var wire 1 fi VPB $end
-$var wire 1 gi VPWR $end
-$var wire 1 [i RESET_B $end
-$var wire 1 hi Q_N $end
-$var wire 1 ii Q $end
-$scope module sc_cell $end
-$var wire 1 bi CLK $end
-$var wire 1 ci D $end
-$var wire 1 ii Q $end
-$var wire 1 hi Q_N $end
-$var wire 1 ji RESET $end
-$var wire 1 ki buf_Q $end
-$var wire 1 [i RESET_B $end
-$upscope $end
-$upscope $end
-$scope module idiv2 $end
-$var wire 1 li CLK $end
-$var wire 1 mi D $end
-$var wire 1 ni VGND $end
-$var wire 1 oi VNB $end
-$var wire 1 pi VPB $end
-$var wire 1 qi VPWR $end
-$var wire 1 [i RESET_B $end
-$var wire 1 ri Q_N $end
-$var wire 1 si Q $end
-$scope module sc_cell $end
-$var wire 1 li CLK $end
-$var wire 1 mi D $end
-$var wire 1 si Q $end
-$var wire 1 ri Q_N $end
-$var wire 1 ti RESET $end
-$var wire 1 ui buf_Q $end
-$var wire 1 [i RESET_B $end
-$upscope $end
-$upscope $end
-$scope module idiv4 $end
-$var wire 1 vi CLK $end
-$var wire 1 wi D $end
-$var wire 1 xi VGND $end
-$var wire 1 yi VNB $end
-$var wire 1 zi VPB $end
-$var wire 1 {i VPWR $end
-$var wire 1 [i RESET_B $end
-$var wire 1 |i Q_N $end
-$var wire 1 }i Q $end
-$scope module sc_cell $end
-$var wire 1 vi CLK $end
-$var wire 1 wi D $end
-$var wire 1 }i Q $end
-$var wire 1 |i Q_N $end
-$var wire 1 ~i RESET $end
-$var wire 1 !j buf_Q $end
-$var wire 1 [i RESET_B $end
-$upscope $end
-$upscope $end
-$scope module idiv8 $end
-$var wire 1 "j CLK $end
-$var wire 1 #j D $end
-$var wire 1 $j VGND $end
-$var wire 1 %j VNB $end
-$var wire 1 &j VPB $end
-$var wire 1 'j VPWR $end
-$var wire 1 [i RESET_B $end
-$var wire 1 (j Q_N $end
-$var wire 1 )j Q $end
-$scope module sc_cell $end
-$var wire 1 "j CLK $end
-$var wire 1 #j D $end
-$var wire 1 )j Q $end
-$var wire 1 (j Q_N $end
-$var wire 1 *j RESET $end
-$var wire 1 +j buf_Q $end
-$var wire 1 [i RESET_B $end
-$upscope $end
-$upscope $end
-$scope module irbb $end
-$var wire 1 i A $end
-$var wire 1 ,j VGND $end
-$var wire 1 -j VNB $end
-$var wire 1 .j VPB $end
-$var wire 1 /j VPWR $end
-$var wire 1 [i X $end
-$scope module sc_cell $end
-$var wire 1 i A $end
-$var wire 1 [i X $end
-$var wire 1 0j buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module pll_control $end
-$var wire 1 1j clock $end
-$var wire 5 2j div [4:0] $end
-$var wire 1 7" osc $end
-$var wire 1 _i reset $end
-$var wire 26 3j trim [25:0] $end
-$var wire 5 4j tint [4:0] $end
-$var wire 6 5j sum [5:0] $end
-$var reg 5 6j count0 [4:0] $end
-$var reg 5 7j count1 [4:0] $end
-$var reg 3 8j oscbuf [2:0] $end
-$var reg 3 9j prep [2:0] $end
-$var reg 7 :j tval [6:0] $end
-$upscope $end
-$scope module ringosc $end
-$var wire 1 Xi reset $end
-$var wire 26 ;j trim [25:0] $end
-$var wire 13 <j d [12:0] $end
-$var wire 2 =j clockp [1:0] $end
-$var wire 2 >j c [1:0] $end
-$scope begin dstage[0] $end
-$scope module id $end
-$var wire 1 ?j d1 $end
-$var wire 1 @j in $end
-$var wire 1 Aj out $end
-$var wire 2 Bj trim [1:0] $end
-$var wire 1 Cj ts $end
-$var wire 1 Dj d2 $end
-$var wire 1 Ej d0 $end
-$scope module delaybuf0 $end
-$var wire 1 @j A $end
-$var wire 1 Fj VGND $end
-$var wire 1 Gj VNB $end
-$var wire 1 Hj VPB $end
-$var wire 1 Ij VPWR $end
-$var wire 1 Cj X $end
-$scope module sc_cell $end
-$var wire 1 @j A $end
-$var wire 1 Cj X $end
-$var wire 1 Jj buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 Cj A $end
-$var wire 1 Kj VGND $end
-$var wire 1 Lj VNB $end
-$var wire 1 Mj VPB $end
-$var wire 1 Nj VPWR $end
-$var wire 1 Ej X $end
-$scope module sc_cell $end
-$var wire 1 Cj A $end
-$var wire 1 Ej X $end
-$var wire 1 Oj buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 Pj TE $end
-$var wire 1 Qj VGND $end
-$var wire 1 Rj VNB $end
-$var wire 1 Sj VPB $end
-$var wire 1 Tj VPWR $end
-$var wire 1 Aj Z $end
-$var wire 1 Dj A $end
-$scope module sc_cell $end
-$var wire 1 Pj TE $end
-$var wire 1 Aj Z $end
-$var wire 1 Dj A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 Ej A $end
-$var wire 1 Uj TE $end
-$var wire 1 Vj VGND $end
-$var wire 1 Wj VNB $end
-$var wire 1 Xj VPB $end
-$var wire 1 Yj VPWR $end
-$var wire 1 ?j Z $end
-$scope module sc_cell $end
-$var wire 1 Ej A $end
-$var wire 1 Uj TE $end
-$var wire 1 ?j Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 Cj A $end
-$var wire 1 Zj TE_B $end
-$var wire 1 [j VGND $end
-$var wire 1 \j VNB $end
-$var wire 1 ]j VPB $end
-$var wire 1 ^j VPWR $end
-$var wire 1 Aj Z $end
-$scope module sc_cell $end
-$var wire 1 Cj A $end
-$var wire 1 Zj TE_B $end
-$var wire 1 Aj Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 Cj A $end
-$var wire 1 _j TE_B $end
-$var wire 1 `j VGND $end
-$var wire 1 aj VNB $end
-$var wire 1 bj VPB $end
-$var wire 1 cj VPWR $end
-$var wire 1 ?j Z $end
-$scope module sc_cell $end
-$var wire 1 Cj A $end
-$var wire 1 _j TE_B $end
-$var wire 1 ?j Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 ?j A $end
-$var wire 1 dj VGND $end
-$var wire 1 ej VNB $end
-$var wire 1 fj VPB $end
-$var wire 1 gj VPWR $end
-$var wire 1 Dj Y $end
-$scope module sc_cell $end
-$var wire 1 ?j A $end
-$var wire 1 Dj Y $end
-$var wire 1 hj not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[1] $end
-$scope module id $end
-$var wire 1 ij d1 $end
-$var wire 1 jj in $end
-$var wire 1 kj out $end
-$var wire 2 lj trim [1:0] $end
-$var wire 1 mj ts $end
-$var wire 1 nj d2 $end
-$var wire 1 oj d0 $end
-$scope module delaybuf0 $end
-$var wire 1 jj A $end
-$var wire 1 pj VGND $end
-$var wire 1 qj VNB $end
-$var wire 1 rj VPB $end
-$var wire 1 sj VPWR $end
-$var wire 1 mj X $end
-$scope module sc_cell $end
-$var wire 1 jj A $end
-$var wire 1 mj X $end
-$var wire 1 tj buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 mj A $end
-$var wire 1 uj VGND $end
-$var wire 1 vj VNB $end
-$var wire 1 wj VPB $end
-$var wire 1 xj VPWR $end
-$var wire 1 oj X $end
-$scope module sc_cell $end
-$var wire 1 mj A $end
-$var wire 1 oj X $end
-$var wire 1 yj buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 zj TE $end
-$var wire 1 {j VGND $end
-$var wire 1 |j VNB $end
-$var wire 1 }j VPB $end
-$var wire 1 ~j VPWR $end
-$var wire 1 kj Z $end
-$var wire 1 nj A $end
-$scope module sc_cell $end
-$var wire 1 zj TE $end
-$var wire 1 kj Z $end
-$var wire 1 nj A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 oj A $end
-$var wire 1 !k TE $end
-$var wire 1 "k VGND $end
-$var wire 1 #k VNB $end
-$var wire 1 $k VPB $end
-$var wire 1 %k VPWR $end
-$var wire 1 ij Z $end
-$scope module sc_cell $end
-$var wire 1 oj A $end
-$var wire 1 !k TE $end
-$var wire 1 ij Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 mj A $end
-$var wire 1 &k TE_B $end
-$var wire 1 'k VGND $end
-$var wire 1 (k VNB $end
-$var wire 1 )k VPB $end
-$var wire 1 *k VPWR $end
-$var wire 1 kj Z $end
-$scope module sc_cell $end
-$var wire 1 mj A $end
-$var wire 1 &k TE_B $end
-$var wire 1 kj Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 mj A $end
-$var wire 1 +k TE_B $end
-$var wire 1 ,k VGND $end
-$var wire 1 -k VNB $end
-$var wire 1 .k VPB $end
-$var wire 1 /k VPWR $end
-$var wire 1 ij Z $end
-$scope module sc_cell $end
-$var wire 1 mj A $end
-$var wire 1 +k TE_B $end
-$var wire 1 ij Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 ij A $end
-$var wire 1 0k VGND $end
-$var wire 1 1k VNB $end
-$var wire 1 2k VPB $end
-$var wire 1 3k VPWR $end
-$var wire 1 nj Y $end
-$scope module sc_cell $end
-$var wire 1 ij A $end
-$var wire 1 nj Y $end
-$var wire 1 4k not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[2] $end
-$scope module id $end
-$var wire 1 5k d1 $end
-$var wire 1 6k in $end
-$var wire 1 7k out $end
-$var wire 2 8k trim [1:0] $end
-$var wire 1 9k ts $end
-$var wire 1 :k d2 $end
-$var wire 1 ;k d0 $end
-$scope module delaybuf0 $end
-$var wire 1 6k A $end
-$var wire 1 <k VGND $end
-$var wire 1 =k VNB $end
-$var wire 1 >k VPB $end
-$var wire 1 ?k VPWR $end
-$var wire 1 9k X $end
-$scope module sc_cell $end
-$var wire 1 6k A $end
-$var wire 1 9k X $end
-$var wire 1 @k buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 9k A $end
-$var wire 1 Ak VGND $end
-$var wire 1 Bk VNB $end
-$var wire 1 Ck VPB $end
-$var wire 1 Dk VPWR $end
-$var wire 1 ;k X $end
-$scope module sc_cell $end
-$var wire 1 9k A $end
-$var wire 1 ;k X $end
-$var wire 1 Ek buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 Fk TE $end
-$var wire 1 Gk VGND $end
-$var wire 1 Hk VNB $end
-$var wire 1 Ik VPB $end
-$var wire 1 Jk VPWR $end
-$var wire 1 7k Z $end
-$var wire 1 :k A $end
-$scope module sc_cell $end
-$var wire 1 Fk TE $end
-$var wire 1 7k Z $end
-$var wire 1 :k A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 ;k A $end
-$var wire 1 Kk TE $end
-$var wire 1 Lk VGND $end
-$var wire 1 Mk VNB $end
-$var wire 1 Nk VPB $end
-$var wire 1 Ok VPWR $end
-$var wire 1 5k Z $end
-$scope module sc_cell $end
-$var wire 1 ;k A $end
-$var wire 1 Kk TE $end
-$var wire 1 5k Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 9k A $end
-$var wire 1 Pk TE_B $end
-$var wire 1 Qk VGND $end
-$var wire 1 Rk VNB $end
-$var wire 1 Sk VPB $end
-$var wire 1 Tk VPWR $end
-$var wire 1 7k Z $end
-$scope module sc_cell $end
-$var wire 1 9k A $end
-$var wire 1 Pk TE_B $end
-$var wire 1 7k Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 9k A $end
-$var wire 1 Uk TE_B $end
-$var wire 1 Vk VGND $end
-$var wire 1 Wk VNB $end
-$var wire 1 Xk VPB $end
-$var wire 1 Yk VPWR $end
-$var wire 1 5k Z $end
-$scope module sc_cell $end
-$var wire 1 9k A $end
-$var wire 1 Uk TE_B $end
-$var wire 1 5k Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 5k A $end
-$var wire 1 Zk VGND $end
-$var wire 1 [k VNB $end
-$var wire 1 \k VPB $end
-$var wire 1 ]k VPWR $end
-$var wire 1 :k Y $end
-$scope module sc_cell $end
-$var wire 1 5k A $end
-$var wire 1 :k Y $end
-$var wire 1 ^k not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[3] $end
-$scope module id $end
-$var wire 1 _k d1 $end
-$var wire 1 `k in $end
-$var wire 1 ak out $end
-$var wire 2 bk trim [1:0] $end
-$var wire 1 ck ts $end
-$var wire 1 dk d2 $end
-$var wire 1 ek d0 $end
-$scope module delaybuf0 $end
-$var wire 1 `k A $end
-$var wire 1 fk VGND $end
-$var wire 1 gk VNB $end
-$var wire 1 hk VPB $end
-$var wire 1 ik VPWR $end
-$var wire 1 ck X $end
-$scope module sc_cell $end
-$var wire 1 `k A $end
-$var wire 1 ck X $end
-$var wire 1 jk buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 ck A $end
-$var wire 1 kk VGND $end
-$var wire 1 lk VNB $end
-$var wire 1 mk VPB $end
-$var wire 1 nk VPWR $end
-$var wire 1 ek X $end
-$scope module sc_cell $end
-$var wire 1 ck A $end
-$var wire 1 ek X $end
-$var wire 1 ok buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 pk TE $end
-$var wire 1 qk VGND $end
-$var wire 1 rk VNB $end
-$var wire 1 sk VPB $end
-$var wire 1 tk VPWR $end
-$var wire 1 ak Z $end
-$var wire 1 dk A $end
-$scope module sc_cell $end
-$var wire 1 pk TE $end
-$var wire 1 ak Z $end
-$var wire 1 dk A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 ek A $end
-$var wire 1 uk TE $end
-$var wire 1 vk VGND $end
-$var wire 1 wk VNB $end
-$var wire 1 xk VPB $end
-$var wire 1 yk VPWR $end
-$var wire 1 _k Z $end
-$scope module sc_cell $end
-$var wire 1 ek A $end
-$var wire 1 uk TE $end
-$var wire 1 _k Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 ck A $end
-$var wire 1 zk TE_B $end
-$var wire 1 {k VGND $end
-$var wire 1 |k VNB $end
-$var wire 1 }k VPB $end
-$var wire 1 ~k VPWR $end
-$var wire 1 ak Z $end
-$scope module sc_cell $end
-$var wire 1 ck A $end
-$var wire 1 zk TE_B $end
-$var wire 1 ak Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 ck A $end
-$var wire 1 !l TE_B $end
-$var wire 1 "l VGND $end
-$var wire 1 #l VNB $end
-$var wire 1 $l VPB $end
-$var wire 1 %l VPWR $end
-$var wire 1 _k Z $end
-$scope module sc_cell $end
-$var wire 1 ck A $end
-$var wire 1 !l TE_B $end
-$var wire 1 _k Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 _k A $end
-$var wire 1 &l VGND $end
-$var wire 1 'l VNB $end
-$var wire 1 (l VPB $end
-$var wire 1 )l VPWR $end
-$var wire 1 dk Y $end
-$scope module sc_cell $end
-$var wire 1 _k A $end
-$var wire 1 dk Y $end
-$var wire 1 *l not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[4] $end
-$scope module id $end
-$var wire 1 +l d1 $end
-$var wire 1 ,l in $end
-$var wire 1 -l out $end
-$var wire 2 .l trim [1:0] $end
-$var wire 1 /l ts $end
-$var wire 1 0l d2 $end
-$var wire 1 1l d0 $end
-$scope module delaybuf0 $end
-$var wire 1 ,l A $end
-$var wire 1 2l VGND $end
-$var wire 1 3l VNB $end
-$var wire 1 4l VPB $end
-$var wire 1 5l VPWR $end
-$var wire 1 /l X $end
-$scope module sc_cell $end
-$var wire 1 ,l A $end
-$var wire 1 /l X $end
-$var wire 1 6l buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 /l A $end
-$var wire 1 7l VGND $end
-$var wire 1 8l VNB $end
-$var wire 1 9l VPB $end
-$var wire 1 :l VPWR $end
-$var wire 1 1l X $end
-$scope module sc_cell $end
-$var wire 1 /l A $end
-$var wire 1 1l X $end
-$var wire 1 ;l buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 <l TE $end
-$var wire 1 =l VGND $end
-$var wire 1 >l VNB $end
-$var wire 1 ?l VPB $end
-$var wire 1 @l VPWR $end
-$var wire 1 -l Z $end
-$var wire 1 0l A $end
-$scope module sc_cell $end
-$var wire 1 <l TE $end
-$var wire 1 -l Z $end
-$var wire 1 0l A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 1l A $end
-$var wire 1 Al TE $end
-$var wire 1 Bl VGND $end
-$var wire 1 Cl VNB $end
-$var wire 1 Dl VPB $end
-$var wire 1 El VPWR $end
-$var wire 1 +l Z $end
-$scope module sc_cell $end
-$var wire 1 1l A $end
-$var wire 1 Al TE $end
-$var wire 1 +l Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 /l A $end
-$var wire 1 Fl TE_B $end
-$var wire 1 Gl VGND $end
-$var wire 1 Hl VNB $end
-$var wire 1 Il VPB $end
-$var wire 1 Jl VPWR $end
-$var wire 1 -l Z $end
-$scope module sc_cell $end
-$var wire 1 /l A $end
-$var wire 1 Fl TE_B $end
-$var wire 1 -l Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 /l A $end
-$var wire 1 Kl TE_B $end
-$var wire 1 Ll VGND $end
-$var wire 1 Ml VNB $end
-$var wire 1 Nl VPB $end
-$var wire 1 Ol VPWR $end
-$var wire 1 +l Z $end
-$scope module sc_cell $end
-$var wire 1 /l A $end
-$var wire 1 Kl TE_B $end
-$var wire 1 +l Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 +l A $end
-$var wire 1 Pl VGND $end
-$var wire 1 Ql VNB $end
-$var wire 1 Rl VPB $end
-$var wire 1 Sl VPWR $end
-$var wire 1 0l Y $end
-$scope module sc_cell $end
-$var wire 1 +l A $end
-$var wire 1 0l Y $end
-$var wire 1 Tl not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[5] $end
-$scope module id $end
-$var wire 1 Ul d1 $end
-$var wire 1 Vl in $end
-$var wire 1 Wl out $end
-$var wire 2 Xl trim [1:0] $end
-$var wire 1 Yl ts $end
-$var wire 1 Zl d2 $end
-$var wire 1 [l d0 $end
-$scope module delaybuf0 $end
-$var wire 1 Vl A $end
-$var wire 1 \l VGND $end
-$var wire 1 ]l VNB $end
-$var wire 1 ^l VPB $end
-$var wire 1 _l VPWR $end
-$var wire 1 Yl X $end
-$scope module sc_cell $end
-$var wire 1 Vl A $end
-$var wire 1 Yl X $end
-$var wire 1 `l buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 Yl A $end
-$var wire 1 al VGND $end
-$var wire 1 bl VNB $end
-$var wire 1 cl VPB $end
-$var wire 1 dl VPWR $end
-$var wire 1 [l X $end
-$scope module sc_cell $end
-$var wire 1 Yl A $end
-$var wire 1 [l X $end
-$var wire 1 el buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 fl TE $end
-$var wire 1 gl VGND $end
-$var wire 1 hl VNB $end
-$var wire 1 il VPB $end
-$var wire 1 jl VPWR $end
-$var wire 1 Wl Z $end
-$var wire 1 Zl A $end
-$scope module sc_cell $end
-$var wire 1 fl TE $end
-$var wire 1 Wl Z $end
-$var wire 1 Zl A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 [l A $end
-$var wire 1 kl TE $end
-$var wire 1 ll VGND $end
-$var wire 1 ml VNB $end
-$var wire 1 nl VPB $end
-$var wire 1 ol VPWR $end
-$var wire 1 Ul Z $end
-$scope module sc_cell $end
-$var wire 1 [l A $end
-$var wire 1 kl TE $end
-$var wire 1 Ul Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 Yl A $end
-$var wire 1 pl TE_B $end
-$var wire 1 ql VGND $end
-$var wire 1 rl VNB $end
-$var wire 1 sl VPB $end
-$var wire 1 tl VPWR $end
-$var wire 1 Wl Z $end
-$scope module sc_cell $end
-$var wire 1 Yl A $end
-$var wire 1 pl TE_B $end
-$var wire 1 Wl Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 Yl A $end
-$var wire 1 ul TE_B $end
-$var wire 1 vl VGND $end
-$var wire 1 wl VNB $end
-$var wire 1 xl VPB $end
-$var wire 1 yl VPWR $end
-$var wire 1 Ul Z $end
-$scope module sc_cell $end
-$var wire 1 Yl A $end
-$var wire 1 ul TE_B $end
-$var wire 1 Ul Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 Ul A $end
-$var wire 1 zl VGND $end
-$var wire 1 {l VNB $end
-$var wire 1 |l VPB $end
-$var wire 1 }l VPWR $end
-$var wire 1 Zl Y $end
-$scope module sc_cell $end
-$var wire 1 Ul A $end
-$var wire 1 Zl Y $end
-$var wire 1 ~l not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[6] $end
-$scope module id $end
-$var wire 1 !m d1 $end
-$var wire 1 "m in $end
-$var wire 1 #m out $end
-$var wire 2 $m trim [1:0] $end
-$var wire 1 %m ts $end
-$var wire 1 &m d2 $end
-$var wire 1 'm d0 $end
-$scope module delaybuf0 $end
-$var wire 1 "m A $end
-$var wire 1 (m VGND $end
-$var wire 1 )m VNB $end
-$var wire 1 *m VPB $end
-$var wire 1 +m VPWR $end
-$var wire 1 %m X $end
-$scope module sc_cell $end
-$var wire 1 "m A $end
-$var wire 1 %m X $end
-$var wire 1 ,m buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 %m A $end
-$var wire 1 -m VGND $end
-$var wire 1 .m VNB $end
-$var wire 1 /m VPB $end
-$var wire 1 0m VPWR $end
-$var wire 1 'm X $end
-$scope module sc_cell $end
-$var wire 1 %m A $end
-$var wire 1 'm X $end
-$var wire 1 1m buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 2m TE $end
-$var wire 1 3m VGND $end
-$var wire 1 4m VNB $end
-$var wire 1 5m VPB $end
-$var wire 1 6m VPWR $end
-$var wire 1 #m Z $end
-$var wire 1 &m A $end
-$scope module sc_cell $end
-$var wire 1 2m TE $end
-$var wire 1 #m Z $end
-$var wire 1 &m A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 'm A $end
-$var wire 1 7m TE $end
-$var wire 1 8m VGND $end
-$var wire 1 9m VNB $end
-$var wire 1 :m VPB $end
-$var wire 1 ;m VPWR $end
-$var wire 1 !m Z $end
-$scope module sc_cell $end
-$var wire 1 'm A $end
-$var wire 1 7m TE $end
-$var wire 1 !m Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 %m A $end
-$var wire 1 <m TE_B $end
-$var wire 1 =m VGND $end
-$var wire 1 >m VNB $end
-$var wire 1 ?m VPB $end
-$var wire 1 @m VPWR $end
-$var wire 1 #m Z $end
-$scope module sc_cell $end
-$var wire 1 %m A $end
-$var wire 1 <m TE_B $end
-$var wire 1 #m Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 %m A $end
-$var wire 1 Am TE_B $end
-$var wire 1 Bm VGND $end
-$var wire 1 Cm VNB $end
-$var wire 1 Dm VPB $end
-$var wire 1 Em VPWR $end
-$var wire 1 !m Z $end
-$scope module sc_cell $end
-$var wire 1 %m A $end
-$var wire 1 Am TE_B $end
-$var wire 1 !m Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 !m A $end
-$var wire 1 Fm VGND $end
-$var wire 1 Gm VNB $end
-$var wire 1 Hm VPB $end
-$var wire 1 Im VPWR $end
-$var wire 1 &m Y $end
-$scope module sc_cell $end
-$var wire 1 !m A $end
-$var wire 1 &m Y $end
-$var wire 1 Jm not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[7] $end
-$scope module id $end
-$var wire 1 Km d1 $end
-$var wire 1 Lm in $end
-$var wire 1 Mm out $end
-$var wire 2 Nm trim [1:0] $end
-$var wire 1 Om ts $end
-$var wire 1 Pm d2 $end
-$var wire 1 Qm d0 $end
-$scope module delaybuf0 $end
-$var wire 1 Lm A $end
-$var wire 1 Rm VGND $end
-$var wire 1 Sm VNB $end
-$var wire 1 Tm VPB $end
-$var wire 1 Um VPWR $end
-$var wire 1 Om X $end
-$scope module sc_cell $end
-$var wire 1 Lm A $end
-$var wire 1 Om X $end
-$var wire 1 Vm buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 Om A $end
-$var wire 1 Wm VGND $end
-$var wire 1 Xm VNB $end
-$var wire 1 Ym VPB $end
-$var wire 1 Zm VPWR $end
-$var wire 1 Qm X $end
-$scope module sc_cell $end
-$var wire 1 Om A $end
-$var wire 1 Qm X $end
-$var wire 1 [m buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 \m TE $end
-$var wire 1 ]m VGND $end
-$var wire 1 ^m VNB $end
-$var wire 1 _m VPB $end
-$var wire 1 `m VPWR $end
-$var wire 1 Mm Z $end
-$var wire 1 Pm A $end
-$scope module sc_cell $end
-$var wire 1 \m TE $end
-$var wire 1 Mm Z $end
-$var wire 1 Pm A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 Qm A $end
-$var wire 1 am TE $end
-$var wire 1 bm VGND $end
-$var wire 1 cm VNB $end
-$var wire 1 dm VPB $end
-$var wire 1 em VPWR $end
-$var wire 1 Km Z $end
-$scope module sc_cell $end
-$var wire 1 Qm A $end
-$var wire 1 am TE $end
-$var wire 1 Km Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 Om A $end
-$var wire 1 fm TE_B $end
-$var wire 1 gm VGND $end
-$var wire 1 hm VNB $end
-$var wire 1 im VPB $end
-$var wire 1 jm VPWR $end
-$var wire 1 Mm Z $end
-$scope module sc_cell $end
-$var wire 1 Om A $end
-$var wire 1 fm TE_B $end
-$var wire 1 Mm Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 Om A $end
-$var wire 1 km TE_B $end
-$var wire 1 lm VGND $end
-$var wire 1 mm VNB $end
-$var wire 1 nm VPB $end
-$var wire 1 om VPWR $end
-$var wire 1 Km Z $end
-$scope module sc_cell $end
-$var wire 1 Om A $end
-$var wire 1 km TE_B $end
-$var wire 1 Km Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 Km A $end
-$var wire 1 pm VGND $end
-$var wire 1 qm VNB $end
-$var wire 1 rm VPB $end
-$var wire 1 sm VPWR $end
-$var wire 1 Pm Y $end
-$scope module sc_cell $end
-$var wire 1 Km A $end
-$var wire 1 Pm Y $end
-$var wire 1 tm not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[8] $end
-$scope module id $end
-$var wire 1 um d1 $end
-$var wire 1 vm in $end
-$var wire 1 wm out $end
-$var wire 2 xm trim [1:0] $end
-$var wire 1 ym ts $end
-$var wire 1 zm d2 $end
-$var wire 1 {m d0 $end
-$scope module delaybuf0 $end
-$var wire 1 vm A $end
-$var wire 1 |m VGND $end
-$var wire 1 }m VNB $end
-$var wire 1 ~m VPB $end
-$var wire 1 !n VPWR $end
-$var wire 1 ym X $end
-$scope module sc_cell $end
-$var wire 1 vm A $end
-$var wire 1 ym X $end
-$var wire 1 "n buf0_out_X $end
-$upscope $end
-$upscope $end
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-$var wire 1 ym A $end
-$var wire 1 #n VGND $end
-$var wire 1 $n VNB $end
-$var wire 1 %n VPB $end
-$var wire 1 &n VPWR $end
-$var wire 1 {m X $end
-$scope module sc_cell $end
-$var wire 1 ym A $end
-$var wire 1 {m X $end
-$var wire 1 'n buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 (n TE $end
-$var wire 1 )n VGND $end
-$var wire 1 *n VNB $end
-$var wire 1 +n VPB $end
-$var wire 1 ,n VPWR $end
-$var wire 1 wm Z $end
-$var wire 1 zm A $end
-$scope module sc_cell $end
-$var wire 1 (n TE $end
-$var wire 1 wm Z $end
-$var wire 1 zm A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 {m A $end
-$var wire 1 -n TE $end
-$var wire 1 .n VGND $end
-$var wire 1 /n VNB $end
-$var wire 1 0n VPB $end
-$var wire 1 1n VPWR $end
-$var wire 1 um Z $end
-$scope module sc_cell $end
-$var wire 1 {m A $end
-$var wire 1 -n TE $end
-$var wire 1 um Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 ym A $end
-$var wire 1 2n TE_B $end
-$var wire 1 3n VGND $end
-$var wire 1 4n VNB $end
-$var wire 1 5n VPB $end
-$var wire 1 6n VPWR $end
-$var wire 1 wm Z $end
-$scope module sc_cell $end
-$var wire 1 ym A $end
-$var wire 1 2n TE_B $end
-$var wire 1 wm Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 ym A $end
-$var wire 1 7n TE_B $end
-$var wire 1 8n VGND $end
-$var wire 1 9n VNB $end
-$var wire 1 :n VPB $end
-$var wire 1 ;n VPWR $end
-$var wire 1 um Z $end
-$scope module sc_cell $end
-$var wire 1 ym A $end
-$var wire 1 7n TE_B $end
-$var wire 1 um Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 um A $end
-$var wire 1 <n VGND $end
-$var wire 1 =n VNB $end
-$var wire 1 >n VPB $end
-$var wire 1 ?n VPWR $end
-$var wire 1 zm Y $end
-$scope module sc_cell $end
-$var wire 1 um A $end
-$var wire 1 zm Y $end
-$var wire 1 @n not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[9] $end
-$scope module id $end
-$var wire 1 An d1 $end
-$var wire 1 Bn in $end
-$var wire 1 Cn out $end
-$var wire 2 Dn trim [1:0] $end
-$var wire 1 En ts $end
-$var wire 1 Fn d2 $end
-$var wire 1 Gn d0 $end
-$scope module delaybuf0 $end
-$var wire 1 Bn A $end
-$var wire 1 Hn VGND $end
-$var wire 1 In VNB $end
-$var wire 1 Jn VPB $end
-$var wire 1 Kn VPWR $end
-$var wire 1 En X $end
-$scope module sc_cell $end
-$var wire 1 Bn A $end
-$var wire 1 En X $end
-$var wire 1 Ln buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 En A $end
-$var wire 1 Mn VGND $end
-$var wire 1 Nn VNB $end
-$var wire 1 On VPB $end
-$var wire 1 Pn VPWR $end
-$var wire 1 Gn X $end
-$scope module sc_cell $end
-$var wire 1 En A $end
-$var wire 1 Gn X $end
-$var wire 1 Qn buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 Rn TE $end
-$var wire 1 Sn VGND $end
-$var wire 1 Tn VNB $end
-$var wire 1 Un VPB $end
-$var wire 1 Vn VPWR $end
-$var wire 1 Cn Z $end
-$var wire 1 Fn A $end
-$scope module sc_cell $end
-$var wire 1 Rn TE $end
-$var wire 1 Cn Z $end
-$var wire 1 Fn A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 Gn A $end
-$var wire 1 Wn TE $end
-$var wire 1 Xn VGND $end
-$var wire 1 Yn VNB $end
-$var wire 1 Zn VPB $end
-$var wire 1 [n VPWR $end
-$var wire 1 An Z $end
-$scope module sc_cell $end
-$var wire 1 Gn A $end
-$var wire 1 Wn TE $end
-$var wire 1 An Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 En A $end
-$var wire 1 \n TE_B $end
-$var wire 1 ]n VGND $end
-$var wire 1 ^n VNB $end
-$var wire 1 _n VPB $end
-$var wire 1 `n VPWR $end
-$var wire 1 Cn Z $end
-$scope module sc_cell $end
-$var wire 1 En A $end
-$var wire 1 \n TE_B $end
-$var wire 1 Cn Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 En A $end
-$var wire 1 an TE_B $end
-$var wire 1 bn VGND $end
-$var wire 1 cn VNB $end
-$var wire 1 dn VPB $end
-$var wire 1 en VPWR $end
-$var wire 1 An Z $end
-$scope module sc_cell $end
-$var wire 1 En A $end
-$var wire 1 an TE_B $end
-$var wire 1 An Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 An A $end
-$var wire 1 fn VGND $end
-$var wire 1 gn VNB $end
-$var wire 1 hn VPB $end
-$var wire 1 in VPWR $end
-$var wire 1 Fn Y $end
-$scope module sc_cell $end
-$var wire 1 An A $end
-$var wire 1 Fn Y $end
-$var wire 1 jn not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[10] $end
-$scope module id $end
-$var wire 1 kn d1 $end
-$var wire 1 ln in $end
-$var wire 1 mn out $end
-$var wire 2 nn trim [1:0] $end
-$var wire 1 on ts $end
-$var wire 1 pn d2 $end
-$var wire 1 qn d0 $end
-$scope module delaybuf0 $end
-$var wire 1 ln A $end
-$var wire 1 rn VGND $end
-$var wire 1 sn VNB $end
-$var wire 1 tn VPB $end
-$var wire 1 un VPWR $end
-$var wire 1 on X $end
-$scope module sc_cell $end
-$var wire 1 ln A $end
-$var wire 1 on X $end
-$var wire 1 vn buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 on A $end
-$var wire 1 wn VGND $end
-$var wire 1 xn VNB $end
-$var wire 1 yn VPB $end
-$var wire 1 zn VPWR $end
-$var wire 1 qn X $end
-$scope module sc_cell $end
-$var wire 1 on A $end
-$var wire 1 qn X $end
-$var wire 1 {n buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 |n TE $end
-$var wire 1 }n VGND $end
-$var wire 1 ~n VNB $end
-$var wire 1 !o VPB $end
-$var wire 1 "o VPWR $end
-$var wire 1 mn Z $end
-$var wire 1 pn A $end
-$scope module sc_cell $end
-$var wire 1 |n TE $end
-$var wire 1 mn Z $end
-$var wire 1 pn A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 qn A $end
-$var wire 1 #o TE $end
-$var wire 1 $o VGND $end
-$var wire 1 %o VNB $end
-$var wire 1 &o VPB $end
-$var wire 1 'o VPWR $end
-$var wire 1 kn Z $end
-$scope module sc_cell $end
-$var wire 1 qn A $end
-$var wire 1 #o TE $end
-$var wire 1 kn Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 on A $end
-$var wire 1 (o TE_B $end
-$var wire 1 )o VGND $end
-$var wire 1 *o VNB $end
-$var wire 1 +o VPB $end
-$var wire 1 ,o VPWR $end
-$var wire 1 mn Z $end
-$scope module sc_cell $end
-$var wire 1 on A $end
-$var wire 1 (o TE_B $end
-$var wire 1 mn Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 on A $end
-$var wire 1 -o TE_B $end
-$var wire 1 .o VGND $end
-$var wire 1 /o VNB $end
-$var wire 1 0o VPB $end
-$var wire 1 1o VPWR $end
-$var wire 1 kn Z $end
-$scope module sc_cell $end
-$var wire 1 on A $end
-$var wire 1 -o TE_B $end
-$var wire 1 kn Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 kn A $end
-$var wire 1 2o VGND $end
-$var wire 1 3o VNB $end
-$var wire 1 4o VPB $end
-$var wire 1 5o VPWR $end
-$var wire 1 pn Y $end
-$scope module sc_cell $end
-$var wire 1 kn A $end
-$var wire 1 pn Y $end
-$var wire 1 6o not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope begin dstage[11] $end
-$scope module id $end
-$var wire 1 7o d1 $end
-$var wire 1 8o in $end
-$var wire 1 9o out $end
-$var wire 2 :o trim [1:0] $end
-$var wire 1 ;o ts $end
-$var wire 1 <o d2 $end
-$var wire 1 =o d0 $end
-$scope module delaybuf0 $end
-$var wire 1 8o A $end
-$var wire 1 >o VGND $end
-$var wire 1 ?o VNB $end
-$var wire 1 @o VPB $end
-$var wire 1 Ao VPWR $end
-$var wire 1 ;o X $end
-$scope module sc_cell $end
-$var wire 1 8o A $end
-$var wire 1 ;o X $end
-$var wire 1 Bo buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf1 $end
-$var wire 1 ;o A $end
-$var wire 1 Co VGND $end
-$var wire 1 Do VNB $end
-$var wire 1 Eo VPB $end
-$var wire 1 Fo VPWR $end
-$var wire 1 =o X $end
-$scope module sc_cell $end
-$var wire 1 ;o A $end
-$var wire 1 =o X $end
-$var wire 1 Go buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 Ho TE $end
-$var wire 1 Io VGND $end
-$var wire 1 Jo VNB $end
-$var wire 1 Ko VPB $end
-$var wire 1 Lo VPWR $end
-$var wire 1 9o Z $end
-$var wire 1 <o A $end
-$scope module sc_cell $end
-$var wire 1 Ho TE $end
-$var wire 1 9o Z $end
-$var wire 1 <o A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 =o A $end
-$var wire 1 Mo TE $end
-$var wire 1 No VGND $end
-$var wire 1 Oo VNB $end
-$var wire 1 Po VPB $end
-$var wire 1 Qo VPWR $end
-$var wire 1 7o Z $end
-$scope module sc_cell $end
-$var wire 1 =o A $end
-$var wire 1 Mo TE $end
-$var wire 1 7o Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 ;o A $end
-$var wire 1 Ro TE_B $end
-$var wire 1 So VGND $end
-$var wire 1 To VNB $end
-$var wire 1 Uo VPB $end
-$var wire 1 Vo VPWR $end
-$var wire 1 9o Z $end
-$scope module sc_cell $end
-$var wire 1 ;o A $end
-$var wire 1 Ro TE_B $end
-$var wire 1 9o Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 ;o A $end
-$var wire 1 Wo TE_B $end
-$var wire 1 Xo VGND $end
-$var wire 1 Yo VNB $end
-$var wire 1 Zo VPB $end
-$var wire 1 [o VPWR $end
-$var wire 1 7o Z $end
-$scope module sc_cell $end
-$var wire 1 ;o A $end
-$var wire 1 Wo TE_B $end
-$var wire 1 7o Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 7o A $end
-$var wire 1 \o VGND $end
-$var wire 1 ]o VNB $end
-$var wire 1 ^o VPB $end
-$var wire 1 _o VPWR $end
-$var wire 1 <o Y $end
-$scope module sc_cell $end
-$var wire 1 7o A $end
-$var wire 1 <o Y $end
-$var wire 1 `o not0_out_Y $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module ibufp00 $end
-$var wire 1 ao A $end
-$var wire 1 bo VGND $end
-$var wire 1 co VNB $end
-$var wire 1 do VPB $end
-$var wire 1 eo VPWR $end
-$var wire 1 fo Y $end
-$scope module sc_cell $end
-$var wire 1 ao A $end
-$var wire 1 fo Y $end
-$var wire 1 go not0_out_Y $end
-$upscope $end
-$upscope $end
-$scope module ibufp01 $end
-$var wire 1 ho A $end
-$var wire 1 io VGND $end
-$var wire 1 jo VNB $end
-$var wire 1 ko VPB $end
-$var wire 1 lo VPWR $end
-$var wire 1 mo Y $end
-$scope module sc_cell $end
-$var wire 1 ho A $end
-$var wire 1 mo Y $end
-$var wire 1 no not0_out_Y $end
-$upscope $end
-$upscope $end
-$scope module ibufp10 $end
-$var wire 1 oo A $end
-$var wire 1 po VGND $end
-$var wire 1 qo VNB $end
-$var wire 1 ro VPB $end
-$var wire 1 so VPWR $end
-$var wire 1 to Y $end
-$scope module sc_cell $end
-$var wire 1 oo A $end
-$var wire 1 to Y $end
-$var wire 1 uo not0_out_Y $end
-$upscope $end
-$upscope $end
-$scope module ibufp11 $end
-$var wire 1 vo A $end
-$var wire 1 wo VGND $end
-$var wire 1 xo VNB $end
-$var wire 1 yo VPB $end
-$var wire 1 zo VPWR $end
-$var wire 1 {o Y $end
-$scope module sc_cell $end
-$var wire 1 vo A $end
-$var wire 1 {o Y $end
-$var wire 1 |o not0_out_Y $end
-$upscope $end
-$upscope $end
-$scope module iss $end
-$var wire 1 }o d1 $end
-$var wire 1 ~o in $end
-$var wire 1 !p one $end
-$var wire 1 "p out $end
-$var wire 1 Xi reset $end
-$var wire 2 #p trim [1:0] $end
-$var wire 1 $p d2 $end
-$var wire 1 %p d0 $end
-$var wire 1 &p ctrl0 $end
-$scope module const1 $end
-$var wire 1 !p HI $end
-$var wire 1 'p LO $end
-$var wire 1 (p VGND $end
-$var wire 1 )p VNB $end
-$var wire 1 *p VPB $end
-$var wire 1 +p VPWR $end
-$scope module sc_cell $end
-$var wire 1 !p HI $end
-$var wire 1 'p LO $end
-$upscope $end
-$upscope $end
-$scope module ctrlen0 $end
-$var wire 1 Xi A $end
-$var wire 1 ,p B $end
-$var wire 1 -p VGND $end
-$var wire 1 .p VNB $end
-$var wire 1 /p VPB $end
-$var wire 1 0p VPWR $end
-$var wire 1 &p X $end
-$scope module sc_cell $end
-$var wire 1 Xi A $end
-$var wire 1 ,p B $end
-$var wire 1 &p X $end
-$var wire 1 1p or0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delaybuf0 $end
-$var wire 1 ~o A $end
-$var wire 1 2p VGND $end
-$var wire 1 3p VNB $end
-$var wire 1 4p VPB $end
-$var wire 1 5p VPWR $end
-$var wire 1 %p X $end
-$scope module sc_cell $end
-$var wire 1 ~o A $end
-$var wire 1 %p X $end
-$var wire 1 6p buf0_out_X $end
-$upscope $end
-$upscope $end
-$scope module delayen0 $end
-$var wire 1 7p TE $end
-$var wire 1 8p VGND $end
-$var wire 1 9p VNB $end
-$var wire 1 :p VPB $end
-$var wire 1 ;p VPWR $end
-$var wire 1 "p Z $end
-$var wire 1 $p A $end
-$scope module sc_cell $end
-$var wire 1 7p TE $end
-$var wire 1 "p Z $end
-$var wire 1 $p A $end
-$upscope $end
-$upscope $end
-$scope module delayen1 $end
-$var wire 1 %p A $end
-$var wire 1 <p TE $end
-$var wire 1 =p VGND $end
-$var wire 1 >p VNB $end
-$var wire 1 ?p VPB $end
-$var wire 1 @p VPWR $end
-$var wire 1 }o Z $end
-$scope module sc_cell $end
-$var wire 1 %p A $end
-$var wire 1 <p TE $end
-$var wire 1 }o Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb0 $end
-$var wire 1 ~o A $end
-$var wire 1 &p TE_B $end
-$var wire 1 Ap VGND $end
-$var wire 1 Bp VNB $end
-$var wire 1 Cp VPB $end
-$var wire 1 Dp VPWR $end
-$var wire 1 "p Z $end
-$scope module sc_cell $end
-$var wire 1 ~o A $end
-$var wire 1 &p TE_B $end
-$var wire 1 "p Z $end
-$upscope $end
-$upscope $end
-$scope module delayenb1 $end
-$var wire 1 ~o A $end
-$var wire 1 Ep TE_B $end
-$var wire 1 Fp VGND $end
-$var wire 1 Gp VNB $end
-$var wire 1 Hp VPB $end
-$var wire 1 Ip VPWR $end
-$var wire 1 }o Z $end
-$scope module sc_cell $end
-$var wire 1 ~o A $end
-$var wire 1 Ep TE_B $end
-$var wire 1 }o Z $end
-$upscope $end
-$upscope $end
-$scope module delayint0 $end
-$var wire 1 }o A $end
-$var wire 1 Jp VGND $end
-$var wire 1 Kp VNB $end
-$var wire 1 Lp VPB $end
-$var wire 1 Mp VPWR $end
-$var wire 1 $p Y $end
-$scope module sc_cell $end
-$var wire 1 }o A $end
-$var wire 1 $p Y $end
-$var wire 1 Np not0_out_Y $end
-$upscope $end
-$upscope $end
-$scope module reseten0 $end
-$var wire 1 !p A $end
-$var wire 1 Xi TE $end
-$var wire 1 Op VGND $end
-$var wire 1 Pp VNB $end
-$var wire 1 Qp VPB $end
-$var wire 1 Rp VPWR $end
-$var wire 1 "p Z $end
-$scope module sc_cell $end
-$var wire 1 !p A $end
-$var wire 1 Xi TE $end
-$var wire 1 "p Z $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module soc $end
-$var wire 1 9" clk $end
-$var wire 1 Th ext_clk $end
-$var wire 1 "i ext_clk_sel $end
-$var wire 1 O flash_clk_ieb $end
-$var wire 1 P flash_csb_ieb $end
-$var wire 1 2" flash_io0_di $end
-$var wire 1 ." flash_io1_di $end
-$var wire 1 Uh flash_io2_di $end
-$var wire 1 Vh flash_io3_di $end
-$var wire 1 *" gpio_in_pad $end
-$var wire 1 Sp irq_pin $end
-$var wire 1 xh irq_spi $end
-$var wire 1 Tp irq_stall $end
-$var wire 1 Up irq_uart $end
-$var wire 128 Vp la_input [127:0] $end
-$var wire 32 Wp mgmt_io_data [31:0] $end
-$var wire 1 R mprj_ack_i $end
-$var wire 32 Xp mprj_adr_o [31:0] $end
-$var wire 1 T mprj_cyc_o $end
-$var wire 32 Yp mprj_dat_i [31:0] $end
-$var wire 32 Zp mprj_dat_o [31:0] $end
-$var wire 4 [p mprj_sel_o [3:0] $end
-$var wire 1 \ mprj_we_o $end
-$var wire 1 qh pass_thru_mgmt $end
-$var wire 1 th pass_thru_mgmt_csb $end
-$var wire 1 sh pass_thru_mgmt_sck $end
-$var wire 1 rh pass_thru_mgmt_sdi $end
-$var wire 1 ]h pass_thru_mgmt_sdo $end
-$var wire 1 ph pll_clk $end
-$var wire 1 8" resetn $end
-$var wire 1 \p ser_rx $end
-$var wire 1 ^h spi_sdi $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 1 ` xbar_ack_i $end
-$var wire 32 _p xbar_adr_o [31:0] $end
-$var wire 1 f xbar_cyc_o $end
-$var wire 32 `p xbar_dat_i [31:0] $end
-$var wire 32 ap xbar_dat_o [31:0] $end
-$var wire 4 bp xbar_sel_o [3:0] $end
-$var wire 1 b xbar_we_o $end
-$var wire 1 c xbar_stb_o $end
-$var wire 1 cp uart_stb_i $end
-$var wire 32 dp uart_dat_o [31:0] $end
-$var wire 1 ep uart_ack_o $end
-$var wire 1 fp trap_output_dest $end
-$var wire 1 ch trap $end
-$var wire 1 gp sys_stb_i $end
-$var wire 32 hp sys_dat_o [31:0] $end
-$var wire 1 ip sys_ack_o $end
-$var wire 1 jp spimemio_flash_stb_i $end
-$var wire 32 kp spimemio_flash_dat_o [31:0] $end
-$var wire 1 lp spimemio_flash_ack_o $end
-$var wire 1 mp spimemio_cfg_stb_i $end
-$var wire 32 np spimemio_cfg_dat_o [31:0] $end
-$var wire 1 op spimemio_cfg_ack_o $end
-$var wire 1 dh spi_sdo $end
-$var wire 1 eh spi_sck $end
-$var wire 1 pp spi_master_stb_i $end
-$var wire 32 qp spi_master_dat_o [31:0] $end
-$var wire 1 rp spi_master_ack_o $end
-$var wire 1 jh spi_csb $end
-$var wire 1 sp ser_tx $end
-$var wire 1 tp pll_output_dest $end
-$var wire 1 l mprj_stb_o $end
-$var wire 1 p mprj_io_loader_resetn $end
-$var wire 1 q mprj_io_loader_data $end
-$var wire 1 r mprj_io_loader_clock $end
-$var wire 1 up mprj_ctrl_stb_i $end
-$var wire 32 vp mprj_ctrl_dat_o [31:0] $end
-$var wire 1 wp mprj_ctrl_ack_o $end
-$var wire 1 xp mem_stb_i $end
-$var wire 1 yp mem_instr $end
-$var wire 32 zp mem_dat_o [31:0] $end
-$var wire 1 {p mem_ack_o $end
-$var wire 1 |p la_stb_i $end
-$var wire 128 }p la_output [127:0] $end
-$var wire 128 ~p la_oen [127:0] $end
-$var wire 32 !q la_dat_o [31:0] $end
-$var wire 1 "q la_ack_o $end
-$var wire 1 #q irq_spi_master $end
-$var wire 1 $q irq_counter_timer1 $end
-$var wire 1 %q irq_counter_timer0 $end
-$var wire 1 &q irq_7_inputsrc $end
-$var wire 1 'q irq_7 $end
-$var wire 1 (q gpio_stb_i $end
-$var wire 1 )q gpio_pullup $end
-$var wire 1 *q gpio_pulldown $end
-$var wire 1 +q gpio_pu $end
-$var wire 1 ,q gpio_pd $end
-$var wire 1 %" gpio_outenb_pad $end
-$var wire 1 -q gpio_outenb $end
-$var wire 1 &" gpio_out_pad $end
-$var wire 1 .q gpio_out $end
-$var wire 1 /q gpio_oeb $end
-$var wire 1 '" gpio_mode1_pad $end
-$var wire 1 (" gpio_mode0_pad $end
-$var wire 1 )" gpio_inenb_pad $end
-$var wire 32 0q gpio_dat_o [31:0] $end
-$var wire 1 1q gpio_ack_o $end
-$var wire 1 2q gpio $end
-$var wire 1 yh flash_io3_oeb $end
-$var wire 1 zh flash_io3_ieb $end
-$var wire 1 {h flash_io3_do $end
-$var wire 1 |h flash_io2_oeb $end
-$var wire 1 }h flash_io2_ieb $end
-$var wire 1 ~h flash_io2_do $end
-$var wire 1 +" flash_io1_oeb $end
-$var wire 1 ," flash_io1_ieb $end
-$var wire 1 -" flash_io1_do $end
-$var wire 1 /" flash_io0_oeb $end
-$var wire 1 0" flash_io0_ieb $end
-$var wire 1 1" flash_io0_do $end
-$var wire 1 3" flash_csb_oeb $end
-$var wire 1 4" flash_csb $end
-$var wire 1 5" flash_clk_oeb $end
-$var wire 1 6" flash_clk $end
-$var wire 1 3q cpu_we_o $end
-$var wire 1 4q cpu_stb_o $end
-$var wire 4 5q cpu_sel_o [3:0] $end
-$var wire 32 6q cpu_dat_o [31:0] $end
-$var wire 32 7q cpu_dat_i [31:0] $end
-$var wire 1 8q cpu_cyc_o $end
-$var wire 32 9q cpu_adr_o [31:0] $end
-$var wire 1 :q cpu_ack_i $end
-$var wire 1 ;q counter_timer1_stb_i $end
-$var wire 32 <q counter_timer1_dat_o [31:0] $end
-$var wire 1 =q counter_timer1_ack_o $end
-$var wire 1 >q counter_timer0_stb_i $end
-$var wire 32 ?q counter_timer0_dat_o [31:0] $end
-$var wire 1 @q counter_timer0_ack_o $end
-$var reg 32 Aq irq [31:0] $end
-$scope module convert_gpio_bit $end
-$var wire 1 )" gpio_inenb_pad $end
-$var wire 1 (" gpio_mode0_pad $end
-$var wire 1 '" gpio_mode1_pad $end
-$var wire 1 .q gpio_out $end
-$var wire 1 -q gpio_outenb $end
-$var wire 1 *q gpio_pd $end
-$var wire 1 )q gpio_pu $end
-$var wire 1 %" gpio_outenb_pad $end
-$var wire 1 &" gpio_out_pad $end
-$upscope $end
-$scope module counter_timer_0 $end
-$var wire 1 Bq counter_timer_reg_cfg_sel $end
-$var wire 1 Cq counter_timer_reg_dat_sel $end
-$var wire 1 Dq counter_timer_reg_val_sel $end
-$var wire 32 Eq mem_wdata [31:0] $end
-$var wire 1 Fq reg_dat_re $end
-$var wire 1 Gq resetn $end
-$var wire 1 Hq valid $end
-$var wire 1 @q wb_ack_o $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 1 >q wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 4 Iq wb_sel_i [3:0] $end
-$var wire 32 Jq wb_dat_o [31:0] $end
-$var wire 32 Kq wb_dat_i [31:0] $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 Lq wb_adr_i [31:0] $end
-$var wire 4 Mq reg_val_we [3:0] $end
-$var wire 4 Nq reg_dat_we [3:0] $end
-$var wire 1 Oq reg_cfg_we $end
-$var wire 1 %q irq $end
-$var wire 32 Pq counter_timer_reg_val_do [31:0] $end
-$var wire 32 Qq counter_timer_reg_dat_do [31:0] $end
-$var wire 32 Rq counter_timer_reg_cfg_do [31:0] $end
-$scope module counter_timer_inst $end
-$var wire 1 ]p clkin $end
-$var wire 32 Sq reg_cfg_di [31:0] $end
-$var wire 1 Oq reg_cfg_we $end
-$var wire 32 Tq reg_dat_di [31:0] $end
-$var wire 4 Uq reg_dat_we [3:0] $end
-$var wire 32 Vq reg_val_di [31:0] $end
-$var wire 4 Wq reg_val_we [3:0] $end
-$var wire 1 Gq resetn $end
-$var wire 32 Xq reg_val_do [31:0] $end
-$var wire 32 Yq reg_dat_do [31:0] $end
-$var wire 32 Zq reg_cfg_do [31:0] $end
-$var reg 1 [q enable $end
-$var reg 1 \q irq_ena $end
-$var reg 1 %q irq_out $end
-$var reg 1 ]q oneshot $end
-$var reg 1 ^q updown $end
-$var reg 32 _q value_cur [31:0] $end
-$var reg 32 `q value_reset [31:0] $end
-$upscope $end
-$upscope $end
-$scope module counter_timer_1 $end
-$var wire 1 aq counter_timer_reg_cfg_sel $end
-$var wire 1 bq counter_timer_reg_dat_sel $end
-$var wire 1 cq counter_timer_reg_val_sel $end
-$var wire 32 dq mem_wdata [31:0] $end
-$var wire 1 eq reg_dat_re $end
-$var wire 1 fq resetn $end
-$var wire 1 gq valid $end
-$var wire 1 =q wb_ack_o $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 1 ;q wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 4 hq wb_sel_i [3:0] $end
-$var wire 32 iq wb_dat_o [31:0] $end
-$var wire 32 jq wb_dat_i [31:0] $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 kq wb_adr_i [31:0] $end
-$var wire 4 lq reg_val_we [3:0] $end
-$var wire 4 mq reg_dat_we [3:0] $end
-$var wire 1 nq reg_cfg_we $end
-$var wire 1 $q irq $end
-$var wire 32 oq counter_timer_reg_val_do [31:0] $end
-$var wire 32 pq counter_timer_reg_dat_do [31:0] $end
-$var wire 32 qq counter_timer_reg_cfg_do [31:0] $end
-$scope module counter_timer_inst $end
-$var wire 1 ]p clkin $end
-$var wire 32 rq reg_cfg_di [31:0] $end
-$var wire 1 nq reg_cfg_we $end
-$var wire 32 sq reg_dat_di [31:0] $end
-$var wire 4 tq reg_dat_we [3:0] $end
-$var wire 32 uq reg_val_di [31:0] $end
-$var wire 4 vq reg_val_we [3:0] $end
-$var wire 1 fq resetn $end
-$var wire 32 wq reg_val_do [31:0] $end
-$var wire 32 xq reg_dat_do [31:0] $end
-$var wire 32 yq reg_cfg_do [31:0] $end
-$var reg 1 zq enable $end
-$var reg 1 {q irq_ena $end
-$var reg 1 $q irq_out $end
-$var reg 1 |q oneshot $end
-$var reg 1 }q updown $end
-$var reg 32 ~q value_cur [31:0] $end
-$var reg 32 !r value_reset [31:0] $end
-$upscope $end
-$upscope $end
-$scope module cpu $end
-$var wire 1 "r clk $end
-$var wire 32 #r irq [31:0] $end
-$var wire 32 $r pcpi_rd [31:0] $end
-$var wire 1 %r pcpi_ready $end
-$var wire 1 &r pcpi_wait $end
-$var wire 1 'r pcpi_wr $end
-$var wire 1 (r resetn $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 1 )r we $end
-$var wire 32 *r wbm_dat_i [31:0] $end
-$var wire 1 :q wbm_ack_i $end
-$var wire 1 ch trap $end
-$var wire 1 +r trace_valid $end
-$var wire 36 ,r trace_data [35:0] $end
-$var wire 1 -r pcpi_valid $end
-$var wire 32 .r pcpi_rs2 [31:0] $end
-$var wire 32 /r pcpi_rs1 [31:0] $end
-$var wire 32 0r pcpi_insn [31:0] $end
-$var wire 4 1r mem_wstrb [3:0] $end
-$var wire 32 2r mem_wdata [31:0] $end
-$var wire 1 3r mem_valid $end
-$var wire 1 yp mem_instr $end
-$var wire 32 4r mem_addr [31:0] $end
-$var wire 32 5r eoi [31:0] $end
-$var reg 32 6r mem_rdata [31:0] $end
-$var reg 1 7r mem_ready $end
-$var reg 2 8r state [1:0] $end
-$var reg 32 9r wbm_adr_o [31:0] $end
-$var reg 1 8q wbm_cyc_o $end
-$var reg 32 :r wbm_dat_o [31:0] $end
-$var reg 4 ;r wbm_sel_o [3:0] $end
-$var reg 1 4q wbm_stb_o $end
-$var reg 1 3q wbm_we_o $end
-$scope module picorv32_core $end
-$var wire 1 "r clk $end
-$var wire 32 <r dbg_mem_addr [31:0] $end
-$var wire 1 =r dbg_mem_instr $end
-$var wire 32 >r dbg_mem_rdata [31:0] $end
-$var wire 1 ?r dbg_mem_ready $end
-$var wire 1 @r dbg_mem_valid $end
-$var wire 32 Ar dbg_mem_wdata [31:0] $end
-$var wire 4 Br dbg_mem_wstrb [3:0] $end
-$var wire 1 Cr instr_trap $end
-$var wire 32 Dr irq [31:0] $end
-$var wire 1 Er launch_next_insn $end
-$var wire 1 Fr mem_done $end
-$var wire 1 Gr mem_la_firstword $end
-$var wire 1 Hr mem_la_firstword_xfer $end
-$var wire 1 Ir mem_la_read $end
-$var wire 1 Jr mem_la_use_prefetched_high_word $end
-$var wire 1 Kr mem_la_write $end
-$var wire 32 Lr mem_rdata [31:0] $end
-$var wire 1 7r mem_ready $end
-$var wire 1 Mr mem_xfer $end
-$var wire 32 Nr pcpi_rd [31:0] $end
-$var wire 1 %r pcpi_ready $end
-$var wire 32 Or pcpi_rs1 [31:0] $end
-$var wire 32 Pr pcpi_rs2 [31:0] $end
-$var wire 1 &r pcpi_wait $end
-$var wire 1 'r pcpi_wr $end
-$var wire 1 (r resetn $end
-$var wire 1 Qr pcpi_mul_wr $end
-$var wire 1 Rr pcpi_mul_wait $end
-$var wire 1 Sr pcpi_mul_ready $end
-$var wire 32 Tr pcpi_mul_rd [31:0] $end
-$var wire 1 Ur pcpi_div_wr $end
-$var wire 1 Vr pcpi_div_wait $end
-$var wire 1 Wr pcpi_div_ready $end
-$var wire 32 Xr pcpi_div_rd [31:0] $end
-$var wire 32 Yr next_pc [31:0] $end
-$var wire 32 Zr mem_rdata_latched_noshuffle [31:0] $end
-$var wire 32 [r mem_rdata_latched [31:0] $end
-$var wire 32 \r mem_la_addr [31:0] $end
-$var wire 1 ]r mem_busy $end
-$var wire 1 ^r is_rdcycle_rdcycleh_rdinstr_rdinstrh $end
-$var wire 6 _r cpuregs_waddr [5:0] $end
-$var wire 32 `r cpuregs_rdata2 [31:0] $end
-$var wire 32 ar cpuregs_rdata1 [31:0] $end
-$var wire 6 br cpuregs_raddr2 [5:0] $end
-$var wire 6 cr cpuregs_raddr1 [5:0] $end
-$var reg 32 dr alu_add_sub [31:0] $end
-$var reg 1 er alu_eq $end
-$var reg 1 fr alu_lts $end
-$var reg 1 gr alu_ltu $end
-$var reg 32 hr alu_out [31:0] $end
-$var reg 1 ir alu_out_0 $end
-$var reg 1 jr alu_out_0_q $end
-$var reg 32 kr alu_out_q [31:0] $end
-$var reg 32 lr alu_shl [31:0] $end
-$var reg 32 mr alu_shr [31:0] $end
-$var reg 1 nr alu_wait $end
-$var reg 1 or alu_wait_2 $end
-$var reg 64 pr cached_ascii_instr [63:0] $end
-$var reg 32 qr cached_insn_imm [31:0] $end
-$var reg 32 rr cached_insn_opcode [31:0] $end
-$var reg 5 sr cached_insn_rd [4:0] $end
-$var reg 5 tr cached_insn_rs1 [4:0] $end
-$var reg 5 ur cached_insn_rs2 [4:0] $end
-$var reg 1 vr clear_prefetched_high_word $end
-$var reg 1 wr clear_prefetched_high_word_q $end
-$var reg 1 xr compressed_instr $end
-$var reg 64 yr count_cycle [63:0] $end
-$var reg 64 zr count_instr [63:0] $end
-$var reg 8 {r cpu_state [7:0] $end
-$var reg 32 |r cpuregs_rs1 [31:0] $end
-$var reg 32 }r cpuregs_rs2 [31:0] $end
-$var reg 32 ~r cpuregs_wrdata [31:0] $end
-$var reg 1 !s cpuregs_write $end
-$var reg 32 "s current_pc [31:0] $end
-$var reg 64 #s dbg_ascii_instr [63:0] $end
-$var reg 128 $s dbg_ascii_state [127:0] $end
-$var reg 32 %s dbg_insn_addr [31:0] $end
-$var reg 32 &s dbg_insn_imm [31:0] $end
-$var reg 32 's dbg_insn_opcode [31:0] $end
-$var reg 5 (s dbg_insn_rd [4:0] $end
-$var reg 5 )s dbg_insn_rs1 [4:0] $end
-$var reg 5 *s dbg_insn_rs2 [4:0] $end
-$var reg 1 +s dbg_next $end
-$var reg 32 ,s dbg_rs1val [31:0] $end
-$var reg 1 -s dbg_rs1val_valid $end
-$var reg 32 .s dbg_rs2val [31:0] $end
-$var reg 1 /s dbg_rs2val_valid $end
-$var reg 1 0s dbg_valid_insn $end
-$var reg 32 1s decoded_imm [31:0] $end
-$var reg 32 2s decoded_imm_j [31:0] $end
-$var reg 5 3s decoded_rd [4:0] $end
-$var reg 5 4s decoded_rs [4:0] $end
-$var reg 5 5s decoded_rs1 [4:0] $end
-$var reg 5 6s decoded_rs2 [4:0] $end
-$var reg 1 7s decoder_pseudo_trigger $end
-$var reg 1 8s decoder_pseudo_trigger_q $end
-$var reg 1 9s decoder_trigger $end
-$var reg 1 :s decoder_trigger_q $end
-$var reg 1 ;s do_waitirq $end
-$var reg 32 <s eoi [31:0] $end
-$var reg 1 =s instr_add $end
-$var reg 1 >s instr_addi $end
-$var reg 1 ?s instr_and $end
-$var reg 1 @s instr_andi $end
-$var reg 1 As instr_auipc $end
-$var reg 1 Bs instr_beq $end
-$var reg 1 Cs instr_bge $end
-$var reg 1 Ds instr_bgeu $end
-$var reg 1 Es instr_blt $end
-$var reg 1 Fs instr_bltu $end
-$var reg 1 Gs instr_bne $end
-$var reg 1 Hs instr_ecall_ebreak $end
-$var reg 1 Is instr_getq $end
-$var reg 1 Js instr_jal $end
-$var reg 1 Ks instr_jalr $end
-$var reg 1 Ls instr_lb $end
-$var reg 1 Ms instr_lbu $end
-$var reg 1 Ns instr_lh $end
-$var reg 1 Os instr_lhu $end
-$var reg 1 Ps instr_lui $end
-$var reg 1 Qs instr_lw $end
-$var reg 1 Rs instr_maskirq $end
-$var reg 1 Ss instr_or $end
-$var reg 1 Ts instr_ori $end
-$var reg 1 Us instr_rdcycle $end
-$var reg 1 Vs instr_rdcycleh $end
-$var reg 1 Ws instr_rdinstr $end
-$var reg 1 Xs instr_rdinstrh $end
-$var reg 1 Ys instr_retirq $end
-$var reg 1 Zs instr_sb $end
-$var reg 1 [s instr_setq $end
-$var reg 1 \s instr_sh $end
-$var reg 1 ]s instr_sll $end
-$var reg 1 ^s instr_slli $end
-$var reg 1 _s instr_slt $end
-$var reg 1 `s instr_slti $end
-$var reg 1 as instr_sltiu $end
-$var reg 1 bs instr_sltu $end
-$var reg 1 cs instr_sra $end
-$var reg 1 ds instr_srai $end
-$var reg 1 es instr_srl $end
-$var reg 1 fs instr_srli $end
-$var reg 1 gs instr_sub $end
-$var reg 1 hs instr_sw $end
-$var reg 1 is instr_timer $end
-$var reg 1 js instr_waitirq $end
-$var reg 1 ks instr_xor $end
-$var reg 1 ls instr_xori $end
-$var reg 1 ms irq_active $end
-$var reg 1 ns irq_delay $end
-$var reg 32 os irq_mask [31:0] $end
-$var reg 32 ps irq_pending [31:0] $end
-$var reg 2 qs irq_state [1:0] $end
-$var reg 1 rs is_alu_reg_imm $end
-$var reg 1 ss is_alu_reg_reg $end
-$var reg 1 ts is_beq_bne_blt_bge_bltu_bgeu $end
-$var reg 1 us is_compare $end
-$var reg 1 vs is_jalr_addi_slti_sltiu_xori_ori_andi $end
-$var reg 1 ws is_lb_lh_lw_lbu_lhu $end
-$var reg 1 xs is_lbu_lhu_lw $end
-$var reg 1 ys is_lui_auipc_jal $end
-$var reg 1 zs is_lui_auipc_jal_jalr_addi_add_sub $end
-$var reg 1 {s is_sb_sh_sw $end
-$var reg 1 |s is_sll_srl_sra $end
-$var reg 1 }s is_slli_srli_srai $end
-$var reg 1 ~s is_slti_blt_slt $end
-$var reg 1 !t is_sltiu_bltu_sltu $end
-$var reg 1 "t last_mem_valid $end
-$var reg 1 #t latched_branch $end
-$var reg 1 $t latched_compr $end
-$var reg 1 %t latched_is_lb $end
-$var reg 1 &t latched_is_lh $end
-$var reg 1 't latched_is_lu $end
-$var reg 5 (t latched_rd [4:0] $end
-$var reg 1 )t latched_stalu $end
-$var reg 1 *t latched_store $end
-$var reg 1 +t latched_trace $end
-$var reg 16 ,t mem_16bit_buffer [15:0] $end
-$var reg 32 -t mem_addr [31:0] $end
-$var reg 1 .t mem_do_prefetch $end
-$var reg 1 /t mem_do_rdata $end
-$var reg 1 0t mem_do_rinst $end
-$var reg 1 1t mem_do_wdata $end
-$var reg 1 yp mem_instr $end
-$var reg 1 2t mem_la_firstword_reg $end
-$var reg 1 3t mem_la_secondword $end
-$var reg 32 4t mem_la_wdata [31:0] $end
-$var reg 4 5t mem_la_wstrb [3:0] $end
-$var reg 32 6t mem_rdata_q [31:0] $end
-$var reg 32 7t mem_rdata_word [31:0] $end
-$var reg 2 8t mem_state [1:0] $end
-$var reg 1 3r mem_valid $end
-$var reg 32 9t mem_wdata [31:0] $end
-$var reg 2 :t mem_wordsize [1:0] $end
-$var reg 4 ;t mem_wstrb [3:0] $end
-$var reg 64 <t new_ascii_instr [63:0] $end
-$var reg 32 =t next_insn_opcode [31:0] $end
-$var reg 32 >t next_irq_pending [31:0] $end
-$var reg 32 ?t pcpi_insn [31:0] $end
-$var reg 32 @t pcpi_int_rd [31:0] $end
-$var reg 1 At pcpi_int_ready $end
-$var reg 1 Bt pcpi_int_wait $end
-$var reg 1 Ct pcpi_int_wr $end
-$var reg 1 Dt pcpi_timeout $end
-$var reg 4 Et pcpi_timeout_counter [3:0] $end
-$var reg 1 -r pcpi_valid $end
-$var reg 1 Ft prefetched_high_word $end
-$var reg 64 Gt q_ascii_instr [63:0] $end
-$var reg 32 Ht q_insn_imm [31:0] $end
-$var reg 32 It q_insn_opcode [31:0] $end
-$var reg 5 Jt q_insn_rd [4:0] $end
-$var reg 5 Kt q_insn_rs1 [4:0] $end
-$var reg 5 Lt q_insn_rs2 [4:0] $end
-$var reg 32 Mt reg_next_pc [31:0] $end
-$var reg 32 Nt reg_op1 [31:0] $end
-$var reg 32 Ot reg_op2 [31:0] $end
-$var reg 32 Pt reg_out [31:0] $end
-$var reg 32 Qt reg_pc [31:0] $end
-$var reg 5 Rt reg_sh [4:0] $end
-$var reg 1 St set_mem_do_rdata $end
-$var reg 1 Tt set_mem_do_rinst $end
-$var reg 1 Ut set_mem_do_wdata $end
-$var reg 32 Vt timer [31:0] $end
-$var reg 36 Wt trace_data [35:0] $end
-$var reg 1 +r trace_valid $end
-$var reg 1 ch trap $end
-$scope begin genblk3 $end
-$scope module pcpi_mul $end
-$var wire 1 "r clk $end
-$var wire 1 Xt mul_start $end
-$var wire 32 Yt pcpi_insn [31:0] $end
-$var wire 32 Zt pcpi_rs1 [31:0] $end
-$var wire 32 [t pcpi_rs2 [31:0] $end
-$var wire 1 -r pcpi_valid $end
-$var wire 1 (r resetn $end
-$var wire 1 \t instr_rs2_signed $end
-$var wire 1 ]t instr_rs1_signed $end
-$var wire 1 ^t instr_any_mulh $end
-$var wire 1 _t instr_any_mul $end
-$var reg 1 `t instr_mul $end
-$var reg 1 at instr_mulh $end
-$var reg 1 bt instr_mulhsu $end
-$var reg 1 ct instr_mulhu $end
-$var reg 7 dt mul_counter [6:0] $end
-$var reg 1 et mul_finish $end
-$var reg 1 ft mul_waiting $end
-$var reg 64 gt next_rd [63:0] $end
-$var reg 64 ht next_rdt [63:0] $end
-$var reg 64 it next_rdx [63:0] $end
-$var reg 64 jt next_rs1 [63:0] $end
-$var reg 64 kt next_rs2 [63:0] $end
-$var reg 32 lt pcpi_rd [31:0] $end
-$var reg 1 Sr pcpi_ready $end
-$var reg 1 Rr pcpi_wait $end
-$var reg 1 mt pcpi_wait_q $end
-$var reg 1 Qr pcpi_wr $end
-$var reg 64 nt rd [63:0] $end
-$var reg 64 ot rdx [63:0] $end
-$var reg 64 pt rs1 [63:0] $end
-$var reg 64 qt rs2 [63:0] $end
-$var reg 64 rt this_rs2 [63:0] $end
-$var integer 32 st i [31:0] $end
-$var integer 32 tt j [31:0] $end
-$upscope $end
-$upscope $end
-$scope begin genblk5 $end
-$scope module pcpi_div $end
-$var wire 1 "r clk $end
-$var wire 32 ut pcpi_insn [31:0] $end
-$var wire 32 vt pcpi_rs1 [31:0] $end
-$var wire 32 wt pcpi_rs2 [31:0] $end
-$var wire 1 -r pcpi_valid $end
-$var wire 1 (r resetn $end
-$var wire 1 xt start $end
-$var wire 1 yt instr_any_div_rem $end
-$var reg 32 zt dividend [31:0] $end
-$var reg 63 {t divisor [62:0] $end
-$var reg 1 |t instr_div $end
-$var reg 1 }t instr_divu $end
-$var reg 1 ~t instr_rem $end
-$var reg 1 !u instr_remu $end
-$var reg 1 "u outsign $end
-$var reg 32 #u pcpi_rd [31:0] $end
-$var reg 1 Wr pcpi_ready $end
-$var reg 1 Vr pcpi_wait $end
-$var reg 1 $u pcpi_wait_q $end
-$var reg 1 Ur pcpi_wr $end
-$var reg 32 %u quotient [31:0] $end
-$var reg 32 &u quotient_msk [31:0] $end
-$var reg 1 'u running $end
-$upscope $end
-$upscope $end
-$scope begin genblk8 $end
-$upscope $end
-$scope module cpuregs $end
-$var wire 1 "r clk $end
-$var wire 6 (u raddr1 [5:0] $end
-$var wire 6 )u raddr2 [5:0] $end
-$var wire 32 *u rdata1 [31:0] $end
-$var wire 32 +u rdata2 [31:0] $end
-$var wire 6 ,u waddr [5:0] $end
-$var wire 32 -u wdata [31:0] $end
-$var wire 1 .u wen $end
-$upscope $end
-$scope task empty_statement $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_wb $end
-$var wire 1 *" gpio_in_pad $end
-$var wire 4 /u iomem_we [3:0] $end
-$var wire 1 0u resetn $end
-$var wire 1 1u valid $end
-$var wire 1 1q wb_ack_o $end
-$var wire 32 2u wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 3u wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 4u wb_sel_i [3:0] $end
-$var wire 1 (q wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 5u wb_dat_o [31:0] $end
-$var wire 1 6u ready $end
-$var wire 1 +q gpio_pu $end
-$var wire 1 ,q gpio_pd $end
-$var wire 1 /q gpio_oeb $end
-$var wire 1 2q gpio $end
-$scope module gpio_ctrl $end
-$var wire 1 ]p clk $end
-$var wire 1 *" gpio_in_pad $end
-$var wire 32 7u iomem_addr [31:0] $end
-$var wire 1 1u iomem_valid $end
-$var wire 32 8u iomem_wdata [31:0] $end
-$var wire 1 9u iomem_wstrb $end
-$var wire 1 0u resetn $end
-$var wire 1 :u gpio_sel $end
-$var wire 1 ;u gpio_pu_sel $end
-$var wire 1 <u gpio_pd_sel $end
-$var wire 1 =u gpio_oeb_sel $end
-$var reg 1 2q gpio $end
-$var reg 1 /q gpio_oeb $end
-$var reg 1 ,q gpio_pd $end
-$var reg 1 +q gpio_pu $end
-$var reg 32 >u iomem_rdata [31:0] $end
-$var reg 1 6u iomem_ready $end
-$upscope $end
-$upscope $end
-$scope module intercon $end
-$var wire 32 ?u wbm_adr_i [31:0] $end
-$var wire 1 4q wbm_stb_i $end
-$var wire 13 @u wbs_ack_i [12:0] $end
-$var wire 416 Au wbs_dat_i [415:0] $end
-$var wire 13 Bu wbs_stb_o [12:0] $end
-$var wire 1 :q wbm_ack_o $end
-$var wire 13 Cu slave_sel [12:0] $end
-$var reg 32 Du wbm_dat_o [31:0] $end
-$var integer 32 Eu i [31:0] $end
-$scope begin genblk1[0] $end
-$upscope $end
-$scope begin genblk1[1] $end
-$upscope $end
-$scope begin genblk1[2] $end
-$upscope $end
-$scope begin genblk1[3] $end
-$upscope $end
-$scope begin genblk1[4] $end
-$upscope $end
-$scope begin genblk1[5] $end
-$upscope $end
-$scope begin genblk1[6] $end
-$upscope $end
-$scope begin genblk1[7] $end
-$upscope $end
-$scope begin genblk1[8] $end
-$upscope $end
-$scope begin genblk1[9] $end
-$upscope $end
-$scope begin genblk1[10] $end
-$upscope $end
-$scope begin genblk1[11] $end
-$upscope $end
-$scope begin genblk1[12] $end
-$upscope $end
-$upscope $end
-$scope module la $end
-$var wire 4 Fu iomem_we [3:0] $end
-$var wire 128 Gu la_data_in [127:0] $end
-$var wire 1 Hu resetn $end
-$var wire 1 Iu valid $end
-$var wire 1 "q wb_ack_o $end
-$var wire 32 Ju wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 Ku wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 Lu wb_sel_i [3:0] $end
-$var wire 1 |p wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 Mu wb_dat_o [31:0] $end
-$var wire 1 Nu ready $end
-$var wire 128 Ou la_oen [127:0] $end
-$var wire 128 Pu la_data [127:0] $end
-$scope module la_ctrl $end
-$var wire 1 ]p clk $end
-$var wire 32 Qu iomem_addr [31:0] $end
-$var wire 1 Iu iomem_valid $end
-$var wire 32 Ru iomem_wdata [31:0] $end
-$var wire 4 Su iomem_wstrb [3:0] $end
-$var wire 128 Tu la_data_in [127:0] $end
-$var wire 1 Hu resetn $end
-$var wire 128 Uu la_oen [127:0] $end
-$var wire 4 Vu la_ena_sel [3:0] $end
-$var wire 4 Wu la_data_sel [3:0] $end
-$var wire 128 Xu la_data [127:0] $end
-$var reg 32 Yu iomem_rdata [31:0] $end
-$var reg 1 Nu iomem_ready $end
-$var reg 32 Zu la_data_0 [31:0] $end
-$var reg 32 [u la_data_1 [31:0] $end
-$var reg 32 \u la_data_2 [31:0] $end
-$var reg 32 ]u la_data_3 [31:0] $end
-$var reg 32 ^u la_ena_0 [31:0] $end
-$var reg 32 _u la_ena_1 [31:0] $end
-$var reg 32 `u la_ena_2 [31:0] $end
-$var reg 32 au la_ena_3 [31:0] $end
-$upscope $end
-$upscope $end
-$scope module mprj_ctrl $end
-$var wire 4 bu iomem_we [3:0] $end
-$var wire 32 cu mgmt_gpio_io [31:0] $end
-$var wire 1 du resetn $end
-$var wire 1 eu valid $end
-$var wire 1 wp wb_ack_o $end
-$var wire 32 fu wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 gu wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 hu wb_sel_i [3:0] $end
-$var wire 1 up wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 iu wb_dat_o [31:0] $end
-$var wire 1 p serial_resetn $end
-$var wire 1 q serial_data_out $end
-$var wire 1 r serial_clock $end
-$var wire 1 ju ready $end
-$scope module mprj_ctrl $end
-$var wire 1 ]p clk $end
-$var wire 32 ku iomem_addr [31:0] $end
-$var wire 1 eu iomem_valid $end
-$var wire 32 lu iomem_wdata [31:0] $end
-$var wire 2 mu iomem_wstrb [1:0] $end
-$var wire 32 nu mgmt_gpio_io [31:0] $end
-$var wire 1 du resetn $end
-$var wire 1 ou xfer_sel $end
-$var wire 32 pu pwr_ctrl_sel [31:0] $end
-$var wire 1 qu mgmt_gpio_in $end
-$var wire 1 ru io_data_sel $end
-$var wire 32 su io_ctrl_sel [31:0] $end
-$var reg 32 tu iomem_rdata [31:0] $end
-$var reg 1 ju iomem_ready $end
-$var reg 32 uu mgmt_gpio_out [31:0] $end
-$var reg 6 vu pad_count [5:0] $end
-$var reg 1 r serial_clock $end
-$var reg 1 q serial_data_out $end
-$var reg 14 wu serial_data_staging [13:0] $end
-$var reg 1 p serial_resetn $end
-$var reg 4 xu xfer_count [3:0] $end
-$var reg 1 yu xfer_ctrl $end
-$var reg 2 zu xfer_state [1:0] $end
-$scope begin genblk1[0] $end
-$upscope $end
-$scope begin genblk1[1] $end
-$upscope $end
-$scope begin genblk1[2] $end
-$upscope $end
-$scope begin genblk1[3] $end
-$upscope $end
-$scope begin genblk1[4] $end
-$upscope $end
-$scope begin genblk1[5] $end
-$upscope $end
-$scope begin genblk1[6] $end
-$upscope $end
-$scope begin genblk1[7] $end
-$upscope $end
-$scope begin genblk1[8] $end
-$upscope $end
-$scope begin genblk1[9] $end
-$upscope $end
-$scope begin genblk1[10] $end
-$upscope $end
-$scope begin genblk1[11] $end
-$upscope $end
-$scope begin genblk1[12] $end
-$upscope $end
-$scope begin genblk1[13] $end
-$upscope $end
-$scope begin genblk1[14] $end
-$upscope $end
-$scope begin genblk1[15] $end
-$upscope $end
-$scope begin genblk1[16] $end
-$upscope $end
-$scope begin genblk1[17] $end
-$upscope $end
-$scope begin genblk1[18] $end
-$upscope $end
-$scope begin genblk1[19] $end
-$upscope $end
-$scope begin genblk1[20] $end
-$upscope $end
-$scope begin genblk1[21] $end
-$upscope $end
-$scope begin genblk1[22] $end
-$upscope $end
-$scope begin genblk1[23] $end
-$upscope $end
-$scope begin genblk1[24] $end
-$upscope $end
-$scope begin genblk1[25] $end
-$upscope $end
-$scope begin genblk1[26] $end
-$upscope $end
-$scope begin genblk1[27] $end
-$upscope $end
-$scope begin genblk1[28] $end
-$upscope $end
-$scope begin genblk1[29] $end
-$upscope $end
-$scope begin genblk1[30] $end
-$upscope $end
-$scope begin genblk1[31] $end
-$upscope $end
-$scope begin genblk2[0] $end
-$upscope $end
-$scope begin genblk2[1] $end
-$upscope $end
-$scope begin genblk2[2] $end
-$upscope $end
-$scope begin genblk2[3] $end
-$upscope $end
-$scope begin genblk2[4] $end
-$upscope $end
-$scope begin genblk2[5] $end
-$upscope $end
-$scope begin genblk2[6] $end
-$upscope $end
-$scope begin genblk2[7] $end
-$upscope $end
-$scope begin genblk2[8] $end
-$upscope $end
-$scope begin genblk2[9] $end
-$upscope $end
-$scope begin genblk2[10] $end
-$upscope $end
-$scope begin genblk2[11] $end
-$upscope $end
-$scope begin genblk2[12] $end
-$upscope $end
-$scope begin genblk2[13] $end
-$upscope $end
-$scope begin genblk2[14] $end
-$upscope $end
-$scope begin genblk2[15] $end
-$upscope $end
-$scope begin genblk2[16] $end
-$upscope $end
-$scope begin genblk2[17] $end
-$upscope $end
-$scope begin genblk2[18] $end
-$upscope $end
-$scope begin genblk2[19] $end
-$upscope $end
-$scope begin genblk2[20] $end
-$upscope $end
-$scope begin genblk2[21] $end
-$upscope $end
-$scope begin genblk2[22] $end
-$upscope $end
-$scope begin genblk2[23] $end
-$upscope $end
-$scope begin genblk2[24] $end
-$upscope $end
-$scope begin genblk2[25] $end
-$upscope $end
-$scope begin genblk2[26] $end
-$upscope $end
-$scope begin genblk2[27] $end
-$upscope $end
-$scope begin genblk2[28] $end
-$upscope $end
-$scope begin genblk2[29] $end
-$upscope $end
-$scope begin genblk2[30] $end
-$upscope $end
-$scope begin genblk2[31] $end
-$upscope $end
-$scope begin genblk3[0] $end
-$upscope $end
-$scope begin genblk3[1] $end
-$upscope $end
-$scope begin genblk3[2] $end
-$upscope $end
-$scope begin genblk3[3] $end
-$upscope $end
-$scope begin genblk3[4] $end
-$upscope $end
-$scope begin genblk3[5] $end
-$upscope $end
-$scope begin genblk3[6] $end
-$upscope $end
-$scope begin genblk3[7] $end
-$upscope $end
-$scope begin genblk3[8] $end
-$upscope $end
-$scope begin genblk3[9] $end
-$upscope $end
-$scope begin genblk3[10] $end
-$upscope $end
-$scope begin genblk3[11] $end
-$upscope $end
-$scope begin genblk3[12] $end
-$upscope $end
-$scope begin genblk3[13] $end
-$upscope $end
-$scope begin genblk3[14] $end
-$upscope $end
-$scope begin genblk3[15] $end
-$upscope $end
-$scope begin genblk3[16] $end
-$upscope $end
-$scope begin genblk3[17] $end
-$upscope $end
-$scope begin genblk3[18] $end
-$upscope $end
-$scope begin genblk3[19] $end
-$upscope $end
-$scope begin genblk3[20] $end
-$upscope $end
-$scope begin genblk3[21] $end
-$upscope $end
-$scope begin genblk3[22] $end
-$upscope $end
-$scope begin genblk3[23] $end
-$upscope $end
-$scope begin genblk3[24] $end
-$upscope $end
-$scope begin genblk3[25] $end
-$upscope $end
-$scope begin genblk3[26] $end
-$upscope $end
-$scope begin genblk3[27] $end
-$upscope $end
-$scope begin genblk3[28] $end
-$upscope $end
-$scope begin genblk3[29] $end
-$upscope $end
-$scope begin genblk3[30] $end
-$upscope $end
-$scope begin genblk3[31] $end
-$upscope $end
-$scope begin genblk4[0] $end
-$upscope $end
-$scope begin genblk4[1] $end
-$upscope $end
-$scope begin genblk4[2] $end
-$upscope $end
-$scope begin genblk4[3] $end
-$upscope $end
-$scope begin genblk4[4] $end
-$upscope $end
-$scope begin genblk4[5] $end
-$upscope $end
-$scope begin genblk4[6] $end
-$upscope $end
-$scope begin genblk4[7] $end
-$upscope $end
-$scope begin genblk4[8] $end
-$upscope $end
-$scope begin genblk4[9] $end
-$upscope $end
-$scope begin genblk4[10] $end
-$upscope $end
-$scope begin genblk4[11] $end
-$upscope $end
-$scope begin genblk4[12] $end
-$upscope $end
-$scope begin genblk4[13] $end
-$upscope $end
-$scope begin genblk4[14] $end
-$upscope $end
-$scope begin genblk4[15] $end
-$upscope $end
-$scope begin genblk4[16] $end
-$upscope $end
-$scope begin genblk4[17] $end
-$upscope $end
-$scope begin genblk4[18] $end
-$upscope $end
-$scope begin genblk4[19] $end
-$upscope $end
-$scope begin genblk4[20] $end
-$upscope $end
-$scope begin genblk4[21] $end
-$upscope $end
-$scope begin genblk4[22] $end
-$upscope $end
-$scope begin genblk4[23] $end
-$upscope $end
-$scope begin genblk4[24] $end
-$upscope $end
-$scope begin genblk4[25] $end
-$upscope $end
-$scope begin genblk4[26] $end
-$upscope $end
-$scope begin genblk4[27] $end
-$upscope $end
-$scope begin genblk4[28] $end
-$upscope $end
-$scope begin genblk4[29] $end
-$upscope $end
-$scope begin genblk4[30] $end
-$upscope $end
-$scope begin genblk4[31] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module simple_spi_master_inst $end
-$var wire 32 {u mem_wdata [31:0] $end
-$var wire 1 |u reg_dat_re $end
-$var wire 1 }u resetn $end
-$var wire 1 ^h sdi $end
-$var wire 1 ~u simple_spi_master_reg_cfg_sel $end
-$var wire 1 !v simple_spi_master_reg_dat_sel $end
-$var wire 1 "v valid $end
-$var wire 1 rp wb_ack_o $end
-$var wire 32 #v wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 $v wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 %v wb_sel_i [3:0] $end
-$var wire 1 pp wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 &v wb_dat_o [31:0] $end
-$var wire 32 'v simple_spi_master_reg_dat_do [31:0] $end
-$var wire 32 (v simple_spi_master_reg_cfg_do [31:0] $end
-$var wire 1 dh sdo $end
-$var wire 1 eh sck $end
-$var wire 1 )v reg_dat_we $end
-$var wire 1 *v reg_dat_wait $end
-$var wire 2 +v reg_cfg_we [1:0] $end
-$var wire 1 #q irq $end
-$var wire 1 jh csb $end
-$scope module spi_master $end
-$var wire 1 ]p clk $end
-$var wire 1 #q irq_out $end
-$var wire 32 ,v reg_cfg_di [31:0] $end
-$var wire 2 -v reg_cfg_we [1:0] $end
-$var wire 32 .v reg_dat_di [31:0] $end
-$var wire 1 |u reg_dat_re $end
-$var wire 1 *v reg_dat_wait $end
-$var wire 1 )v reg_dat_we $end
-$var wire 1 }u resetn $end
-$var wire 1 ^h sdi $end
-$var wire 1 dh sdo $end
-$var wire 1 eh sck $end
-$var wire 32 /v reg_dat_do [31:0] $end
-$var wire 32 0v reg_cfg_do [31:0] $end
-$var wire 1 jh csb $end
-$var reg 8 1v count [7:0] $end
-$var reg 8 2v d_latched [7:0] $end
-$var reg 1 3v done $end
-$var reg 1 4v enable $end
-$var reg 1 5v err_out $end
-$var reg 1 6v hsck $end
-$var reg 1 7v icsb $end
-$var reg 1 8v invcsb $end
-$var reg 1 9v invsck $end
-$var reg 1 :v irqena $end
-$var reg 1 ;v isck $end
-$var reg 1 <v isdo $end
-$var reg 1 =v mlb $end
-$var reg 1 >v mode $end
-$var reg 3 ?v nbit [2:0] $end
-$var reg 8 @v prescaler [7:0] $end
-$var reg 1 Av r_latched $end
-$var reg 8 Bv rreg [7:0] $end
-$var reg 2 Cv state [1:0] $end
-$var reg 1 Dv stream $end
-$var reg 8 Ev treg [7:0] $end
-$var reg 1 Fv w_latched $end
-$upscope $end
-$upscope $end
-$scope module simpleuart $end
-$var wire 32 Gv mem_wdata [31:0] $end
-$var wire 1 Hv reg_dat_re $end
-$var wire 1 Iv resetn $end
-$var wire 1 \p ser_rx $end
-$var wire 1 Jv simpleuart_reg_dat_sel $end
-$var wire 1 Kv simpleuart_reg_div_sel $end
-$var wire 1 Lv valid $end
-$var wire 1 ep wb_ack_o $end
-$var wire 32 Mv wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 Nv wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 Ov wb_sel_i [3:0] $end
-$var wire 1 cp wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 Pv wb_dat_o [31:0] $end
-$var wire 32 Qv simpleuart_reg_div_do [31:0] $end
-$var wire 32 Rv simpleuart_reg_dat_do [31:0] $end
-$var wire 1 sp ser_tx $end
-$var wire 4 Sv reg_div_we [3:0] $end
-$var wire 1 Tv reg_dat_we $end
-$var wire 1 Uv reg_dat_wait $end
-$scope module simpleuart $end
-$var wire 1 ]p clk $end
-$var wire 32 Vv reg_dat_di [31:0] $end
-$var wire 1 Hv reg_dat_re $end
-$var wire 1 Uv reg_dat_wait $end
-$var wire 1 Tv reg_dat_we $end
-$var wire 32 Wv reg_div_di [31:0] $end
-$var wire 32 Xv reg_div_do [31:0] $end
-$var wire 4 Yv reg_div_we [3:0] $end
-$var wire 1 Iv resetn $end
-$var wire 1 \p ser_rx $end
-$var wire 1 sp ser_tx $end
-$var wire 32 Zv reg_dat_do [31:0] $end
-$var reg 32 [v cfg_divider [31:0] $end
-$var reg 8 \v recv_buf_data [7:0] $end
-$var reg 1 ]v recv_buf_valid $end
-$var reg 32 ^v recv_divcnt [31:0] $end
-$var reg 8 _v recv_pattern [7:0] $end
-$var reg 4 `v recv_state [3:0] $end
-$var reg 4 av send_bitcnt [3:0] $end
-$var reg 32 bv send_divcnt [31:0] $end
-$var reg 1 cv send_dummy $end
-$var reg 10 dv send_pattern [9:0] $end
-$upscope $end
-$upscope $end
-$scope module soc_mem $end
-$var wire 1 ev ram_wen $end
-$var wire 1 fv valid $end
-$var wire 32 gv wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 hv wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 iv wb_sel_i [3:0] $end
-$var wire 1 xp wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 4 jv wen [3:0] $end
-$var wire 32 kv wb_dat_o [31:0] $end
-$var reg 1 {p wb_ack_o $end
-$var reg 1 lv wb_ack_read $end
-$scope module mem $end
-$var wire 22 mv addr [21:0] $end
-$var wire 1 ]p clk $end
-$var wire 1 fv ena $end
-$var wire 32 nv wdata [31:0] $end
-$var wire 4 ov wen [3:0] $end
-$var wire 32 pv rdata [31:0] $end
-$scope module SRAM $end
-$var wire 13 qv addr0 [12:0] $end
-$var wire 13 rv addr1 [12:0] $end
-$var wire 1 ]p clk0 $end
-$var wire 1 sv clk1 $end
-$var wire 1 tv csb0 $end
-$var wire 1 uv csb1 $end
-$var wire 32 vv din0 [31:0] $end
-$var wire 1 wv web0 $end
-$var wire 4 xv wmask0 [3:0] $end
-$var reg 13 yv addr0_reg [12:0] $end
-$var reg 13 zv addr1_reg [12:0] $end
-$var reg 1 {v csb0_reg $end
-$var reg 1 |v csb1_reg $end
-$var reg 32 }v din0_reg [31:0] $end
-$var reg 32 ~v dout0 [31:0] $end
-$var reg 32 !w dout1 [31:0] $end
-$var reg 1 "w web0_reg $end
-$var reg 4 #w wmask0_reg [3:0] $end
-$scope begin MEM_READ0 $end
-$upscope $end
-$scope begin MEM_READ1 $end
-$upscope $end
-$scope begin MEM_WRITE0 $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module spimemio $end
-$var wire 1 O flash_clk_ieb $end
-$var wire 1 P flash_csb_ieb $end
-$var wire 1 2" flash_io0_di $end
-$var wire 1 ." flash_io1_di $end
-$var wire 1 Uh flash_io2_di $end
-$var wire 1 Vh flash_io3_di $end
-$var wire 1 qh pass_thru $end
-$var wire 1 th pass_thru_csb $end
-$var wire 1 sh pass_thru_sck $end
-$var wire 1 rh pass_thru_sdi $end
-$var wire 1 ]h pass_thru_sdo $end
-$var wire 1 $w resetn $end
-$var wire 1 %w spimemio_cfgreg_sel $end
-$var wire 1 &w valid $end
-$var wire 32 'w wb_adr_i [31:0] $end
-$var wire 1 op wb_cfg_ack_o $end
-$var wire 32 (w wb_cfg_dat_o [31:0] $end
-$var wire 1 mp wb_cfg_stb_i $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 )w wb_dat_i [31:0] $end
-$var wire 1 lp wb_flash_ack_o $end
-$var wire 32 *w wb_flash_dat_o [31:0] $end
-$var wire 1 jp wb_flash_stb_i $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 +w wb_sel_i [3:0] $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 ,w spimemio_cfgreg_do [31:0] $end
-$var wire 1 -w spimem_ready $end
-$var wire 32 .w spimem_rdata [31:0] $end
-$var wire 24 /w mem_addr [23:0] $end
-$var wire 1 yh flash_io3_oeb $end
-$var wire 1 zh flash_io3_ieb $end
-$var wire 1 {h flash_io3_do $end
-$var wire 1 |h flash_io2_oeb $end
-$var wire 1 }h flash_io2_ieb $end
-$var wire 1 ~h flash_io2_do $end
-$var wire 1 +" flash_io1_oeb $end
-$var wire 1 ," flash_io1_ieb $end
-$var wire 1 -" flash_io1_do $end
-$var wire 1 /" flash_io0_oeb $end
-$var wire 1 0" flash_io0_ieb $end
-$var wire 1 1" flash_io0_do $end
-$var wire 1 3" flash_csb_oeb $end
-$var wire 1 4" flash_csb $end
-$var wire 1 5" flash_clk_oeb $end
-$var wire 1 6" flash_clk $end
-$var wire 4 0w cfgreg_we [3:0] $end
-$scope module spimemio $end
-$var wire 24 1w addr [23:0] $end
-$var wire 32 2w cfgreg_di [31:0] $end
-$var wire 4 3w cfgreg_we [3:0] $end
-$var wire 1 ]p clk $end
-$var wire 1 O flash_clk_ieb $end
-$var wire 1 P flash_csb_ieb $end
-$var wire 1 2" flash_io0_di $end
-$var wire 1 ." flash_io1_di $end
-$var wire 1 Uh flash_io2_di $end
-$var wire 1 Vh flash_io3_di $end
-$var wire 1 4w jump $end
-$var wire 1 5w pass_thru $end
-$var wire 1 6w pass_thru_csb $end
-$var wire 1 7w pass_thru_sck $end
-$var wire 1 8w pass_thru_sdi $end
-$var wire 1 -w ready $end
-$var wire 1 $w resetn $end
-$var wire 1 &w valid $end
-$var wire 1 9w xfer_ddr $end
-$var wire 1 :w xfer_dspi $end
-$var wire 1 ;w xfer_io3_oe $end
-$var wire 1 <w xfer_io3_do $end
-$var wire 1 =w xfer_io2_oe $end
-$var wire 1 >w xfer_io2_do $end
-$var wire 1 ?w xfer_io1_oe $end
-$var wire 1 @w xfer_io1_do $end
-$var wire 1 Aw xfer_io0_oe $end
-$var wire 1 Bw xfer_io0_do $end
-$var wire 1 Cw xfer_csb $end
-$var wire 1 Dw xfer_clk $end
-$var wire 1 Ew pass_thru_sdo $end
-$var wire 1 yh flash_io3_oeb $end
-$var wire 1 zh flash_io3_ieb $end
-$var wire 1 {h flash_io3_do $end
-$var wire 1 |h flash_io2_oeb $end
-$var wire 1 }h flash_io2_ieb $end
-$var wire 1 ~h flash_io2_do $end
-$var wire 1 +" flash_io1_oeb $end
-$var wire 1 ," flash_io1_ieb $end
-$var wire 1 -" flash_io1_do $end
-$var wire 1 /" flash_io0_oeb $end
-$var wire 1 0" flash_io0_ieb $end
-$var wire 1 1" flash_io0_do $end
-$var wire 1 3" flash_csb_oeb $end
-$var wire 1 4" flash_csb $end
-$var wire 1 5" flash_clk_oeb $end
-$var wire 1 6" flash_clk $end
-$var wire 1 Fw dout_valid $end
-$var wire 4 Gw dout_tag [3:0] $end
-$var wire 8 Hw dout_data [7:0] $end
-$var wire 1 Iw din_ready $end
-$var wire 32 Jw cfgreg_do [31:0] $end
-$var reg 24 Kw buffer [23:0] $end
-$var reg 1 Lw config_clk $end
-$var reg 1 Mw config_cont $end
-$var reg 1 Nw config_csb $end
-$var reg 1 Ow config_ddr $end
-$var reg 4 Pw config_do [3:0] $end
-$var reg 4 Qw config_dummy [3:0] $end
-$var reg 1 Rw config_en $end
-$var reg 4 Sw config_oe [3:0] $end
-$var reg 1 Tw config_qspi $end
-$var reg 1 Uw din_cont $end
-$var reg 8 Vw din_data [7:0] $end
-$var reg 1 Ww din_ddr $end
-$var reg 1 Xw din_qspi $end
-$var reg 1 Yw din_rd $end
-$var reg 4 Zw din_tag [3:0] $end
-$var reg 1 [w din_valid $end
-$var reg 24 \w rd_addr [23:0] $end
-$var reg 1 ]w rd_inc $end
-$var reg 1 ^w rd_valid $end
-$var reg 1 _w rd_wait $end
-$var reg 32 `w rdata [31:0] $end
-$var reg 1 aw softreset $end
-$var reg 4 bw state [3:0] $end
-$var reg 1 cw xfer_io0_90 $end
-$var reg 1 dw xfer_io1_90 $end
-$var reg 1 ew xfer_io2_90 $end
-$var reg 1 fw xfer_io3_90 $end
-$var reg 1 gw xfer_resetn $end
-$scope module xfer $end
-$var wire 1 ]p clk $end
-$var wire 1 Uw din_cont $end
-$var wire 8 hw din_data [7:0] $end
-$var wire 1 9w din_ddr $end
-$var wire 1 :w din_dspi $end
-$var wire 1 Xw din_qspi $end
-$var wire 1 Yw din_rd $end
-$var wire 1 Iw din_ready $end
-$var wire 4 iw din_tag [3:0] $end
-$var wire 1 [w din_valid $end
-$var wire 8 jw dout_data [7:0] $end
-$var wire 4 kw dout_tag [3:0] $end
-$var wire 1 Fw dout_valid $end
-$var wire 1 2" flash_io0_di $end
-$var wire 1 ." flash_io1_di $end
-$var wire 1 Uh flash_io2_di $end
-$var wire 1 Vh flash_io3_di $end
-$var wire 1 $w resetn $end
-$var wire 1 gw xfer_resetn $end
-$var reg 4 lw count [3:0] $end
-$var reg 4 mw dummy_count [3:0] $end
-$var reg 1 nw fetch $end
-$var reg 1 Dw flash_clk $end
-$var reg 1 Cw flash_csb $end
-$var reg 1 Bw flash_io0_do $end
-$var reg 1 Aw flash_io0_oe $end
-$var reg 1 @w flash_io1_do $end
-$var reg 1 ?w flash_io1_oe $end
-$var reg 1 >w flash_io2_do $end
-$var reg 1 =w flash_io2_oe $end
-$var reg 1 <w flash_io3_do $end
-$var reg 1 ;w flash_io3_oe $end
-$var reg 8 ow ibuffer [7:0] $end
-$var reg 1 pw last_fetch $end
-$var reg 4 qw next_count [3:0] $end
-$var reg 1 rw next_fetch $end
-$var reg 8 sw next_ibuffer [7:0] $end
-$var reg 8 tw next_obuffer [7:0] $end
-$var reg 8 uw obuffer [7:0] $end
-$var reg 1 vw xfer_cont $end
-$var reg 1 ww xfer_ddr $end
-$var reg 1 xw xfer_ddr_q $end
-$var reg 1 yw xfer_dspi $end
-$var reg 1 zw xfer_qspi $end
-$var reg 1 {w xfer_rd $end
-$var reg 4 |w xfer_tag [3:0] $end
-$var reg 4 }w xfer_tag_q [3:0] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module sysctrl $end
-$var wire 4 ~w iomem_we [3:0] $end
-$var wire 1 !x resetn $end
-$var wire 1 "x valid $end
-$var wire 1 ip wb_ack_o $end
-$var wire 32 #x wb_adr_i [31:0] $end
-$var wire 1 ]p wb_clk_i $end
-$var wire 1 8q wb_cyc_i $end
-$var wire 32 $x wb_dat_i [31:0] $end
-$var wire 1 ^p wb_rst_i $end
-$var wire 4 %x wb_sel_i [3:0] $end
-$var wire 1 gp wb_stb_i $end
-$var wire 1 3q wb_we_i $end
-$var wire 32 &x wb_dat_o [31:0] $end
-$var wire 1 fp trap_output_dest $end
-$var wire 1 'x ready $end
-$var wire 1 tp pll_output_dest $end
-$var wire 1 &q irq_7_inputsrc $end
-$scope module sysctrl $end
-$var wire 1 ]p clk $end
-$var wire 32 (x iomem_addr [31:0] $end
-$var wire 1 "x iomem_valid $end
-$var wire 32 )x iomem_wdata [31:0] $end
-$var wire 4 *x iomem_wstrb [3:0] $end
-$var wire 1 !x resetn $end
-$var wire 1 +x trap_out_sel $end
-$var wire 1 ,x pll_out_sel $end
-$var wire 1 -x irq7_sel $end
-$var reg 32 .x iomem_rdata [31:0] $end
-$var reg 1 'x iomem_ready $end
-$var reg 1 &q irq_7_inputsrc $end
-$var reg 1 tp pll_output_dest $end
-$var reg 1 fp trap_output_dest $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module user_id_value $end
-$var wire 32 /x user_proj_id_low [31:0] $end
-$var wire 32 0x user_proj_id_high [31:0] $end
-$var wire 32 1x mask_rev [31:0] $end
-$scope begin genblk1[0] $end
-$upscope $end
-$scope begin genblk1[1] $end
-$upscope $end
-$scope begin genblk1[2] $end
-$upscope $end
-$scope begin genblk1[3] $end
-$upscope $end
-$scope begin genblk1[4] $end
-$upscope $end
-$scope begin genblk1[5] $end
-$upscope $end
-$scope begin genblk1[6] $end
-$upscope $end
-$scope begin genblk1[7] $end
-$upscope $end
-$scope begin genblk1[8] $end
-$upscope $end
-$scope begin genblk1[9] $end
-$upscope $end
-$scope begin genblk1[10] $end
-$upscope $end
-$scope begin genblk1[11] $end
-$upscope $end
-$scope begin genblk1[12] $end
-$upscope $end
-$scope begin genblk1[13] $end
-$upscope $end
-$scope begin genblk1[14] $end
-$upscope $end
-$scope begin genblk1[15] $end
-$upscope $end
-$scope begin genblk1[16] $end
-$upscope $end
-$scope begin genblk1[17] $end
-$upscope $end
-$scope begin genblk1[18] $end
-$upscope $end
-$scope begin genblk1[19] $end
-$upscope $end
-$scope begin genblk1[20] $end
-$upscope $end
-$scope begin genblk1[21] $end
-$upscope $end
-$scope begin genblk1[22] $end
-$upscope $end
-$scope begin genblk1[23] $end
-$upscope $end
-$scope begin genblk1[24] $end
-$upscope $end
-$scope begin genblk1[25] $end
-$upscope $end
-$scope begin genblk1[26] $end
-$upscope $end
-$scope begin genblk1[27] $end
-$upscope $end
-$scope begin genblk1[28] $end
-$upscope $end
-$scope begin genblk1[29] $end
-$upscope $end
-$scope begin genblk1[30] $end
-$upscope $end
-$scope begin genblk1[31] $end
-$upscope $end
-$scope module mask_rev_value[0] $end
-$var wire 1 2x HI $end
-$var wire 1 3x LO $end
-$var wire 1 4x VGND $end
-$var wire 1 5x VNB $end
-$var wire 1 6x VPB $end
-$var wire 1 7x VPWR $end
-$scope module sc_cell $end
-$var wire 1 2x HI $end
-$var wire 1 3x LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[1] $end
-$var wire 1 8x HI $end
-$var wire 1 9x LO $end
-$var wire 1 :x VGND $end
-$var wire 1 ;x VNB $end
-$var wire 1 <x VPB $end
-$var wire 1 =x VPWR $end
-$scope module sc_cell $end
-$var wire 1 8x HI $end
-$var wire 1 9x LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[2] $end
-$var wire 1 >x HI $end
-$var wire 1 ?x LO $end
-$var wire 1 @x VGND $end
-$var wire 1 Ax VNB $end
-$var wire 1 Bx VPB $end
-$var wire 1 Cx VPWR $end
-$scope module sc_cell $end
-$var wire 1 >x HI $end
-$var wire 1 ?x LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[3] $end
-$var wire 1 Dx HI $end
-$var wire 1 Ex LO $end
-$var wire 1 Fx VGND $end
-$var wire 1 Gx VNB $end
-$var wire 1 Hx VPB $end
-$var wire 1 Ix VPWR $end
-$scope module sc_cell $end
-$var wire 1 Dx HI $end
-$var wire 1 Ex LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[4] $end
-$var wire 1 Jx HI $end
-$var wire 1 Kx LO $end
-$var wire 1 Lx VGND $end
-$var wire 1 Mx VNB $end
-$var wire 1 Nx VPB $end
-$var wire 1 Ox VPWR $end
-$scope module sc_cell $end
-$var wire 1 Jx HI $end
-$var wire 1 Kx LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[5] $end
-$var wire 1 Px HI $end
-$var wire 1 Qx LO $end
-$var wire 1 Rx VGND $end
-$var wire 1 Sx VNB $end
-$var wire 1 Tx VPB $end
-$var wire 1 Ux VPWR $end
-$scope module sc_cell $end
-$var wire 1 Px HI $end
-$var wire 1 Qx LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[6] $end
-$var wire 1 Vx HI $end
-$var wire 1 Wx LO $end
-$var wire 1 Xx VGND $end
-$var wire 1 Yx VNB $end
-$var wire 1 Zx VPB $end
-$var wire 1 [x VPWR $end
-$scope module sc_cell $end
-$var wire 1 Vx HI $end
-$var wire 1 Wx LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[7] $end
-$var wire 1 \x HI $end
-$var wire 1 ]x LO $end
-$var wire 1 ^x VGND $end
-$var wire 1 _x VNB $end
-$var wire 1 `x VPB $end
-$var wire 1 ax VPWR $end
-$scope module sc_cell $end
-$var wire 1 \x HI $end
-$var wire 1 ]x LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[8] $end
-$var wire 1 bx HI $end
-$var wire 1 cx LO $end
-$var wire 1 dx VGND $end
-$var wire 1 ex VNB $end
-$var wire 1 fx VPB $end
-$var wire 1 gx VPWR $end
-$scope module sc_cell $end
-$var wire 1 bx HI $end
-$var wire 1 cx LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[9] $end
-$var wire 1 hx HI $end
-$var wire 1 ix LO $end
-$var wire 1 jx VGND $end
-$var wire 1 kx VNB $end
-$var wire 1 lx VPB $end
-$var wire 1 mx VPWR $end
-$scope module sc_cell $end
-$var wire 1 hx HI $end
-$var wire 1 ix LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[10] $end
-$var wire 1 nx HI $end
-$var wire 1 ox LO $end
-$var wire 1 px VGND $end
-$var wire 1 qx VNB $end
-$var wire 1 rx VPB $end
-$var wire 1 sx VPWR $end
-$scope module sc_cell $end
-$var wire 1 nx HI $end
-$var wire 1 ox LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[11] $end
-$var wire 1 tx HI $end
-$var wire 1 ux LO $end
-$var wire 1 vx VGND $end
-$var wire 1 wx VNB $end
-$var wire 1 xx VPB $end
-$var wire 1 yx VPWR $end
-$scope module sc_cell $end
-$var wire 1 tx HI $end
-$var wire 1 ux LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[12] $end
-$var wire 1 zx HI $end
-$var wire 1 {x LO $end
-$var wire 1 |x VGND $end
-$var wire 1 }x VNB $end
-$var wire 1 ~x VPB $end
-$var wire 1 !y VPWR $end
-$scope module sc_cell $end
-$var wire 1 zx HI $end
-$var wire 1 {x LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[13] $end
-$var wire 1 "y HI $end
-$var wire 1 #y LO $end
-$var wire 1 $y VGND $end
-$var wire 1 %y VNB $end
-$var wire 1 &y VPB $end
-$var wire 1 'y VPWR $end
-$scope module sc_cell $end
-$var wire 1 "y HI $end
-$var wire 1 #y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[14] $end
-$var wire 1 (y HI $end
-$var wire 1 )y LO $end
-$var wire 1 *y VGND $end
-$var wire 1 +y VNB $end
-$var wire 1 ,y VPB $end
-$var wire 1 -y VPWR $end
-$scope module sc_cell $end
-$var wire 1 (y HI $end
-$var wire 1 )y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[15] $end
-$var wire 1 .y HI $end
-$var wire 1 /y LO $end
-$var wire 1 0y VGND $end
-$var wire 1 1y VNB $end
-$var wire 1 2y VPB $end
-$var wire 1 3y VPWR $end
-$scope module sc_cell $end
-$var wire 1 .y HI $end
-$var wire 1 /y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[16] $end
-$var wire 1 4y HI $end
-$var wire 1 5y LO $end
-$var wire 1 6y VGND $end
-$var wire 1 7y VNB $end
-$var wire 1 8y VPB $end
-$var wire 1 9y VPWR $end
-$scope module sc_cell $end
-$var wire 1 4y HI $end
-$var wire 1 5y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[17] $end
-$var wire 1 :y HI $end
-$var wire 1 ;y LO $end
-$var wire 1 <y VGND $end
-$var wire 1 =y VNB $end
-$var wire 1 >y VPB $end
-$var wire 1 ?y VPWR $end
-$scope module sc_cell $end
-$var wire 1 :y HI $end
-$var wire 1 ;y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[18] $end
-$var wire 1 @y HI $end
-$var wire 1 Ay LO $end
-$var wire 1 By VGND $end
-$var wire 1 Cy VNB $end
-$var wire 1 Dy VPB $end
-$var wire 1 Ey VPWR $end
-$scope module sc_cell $end
-$var wire 1 @y HI $end
-$var wire 1 Ay LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[19] $end
-$var wire 1 Fy HI $end
-$var wire 1 Gy LO $end
-$var wire 1 Hy VGND $end
-$var wire 1 Iy VNB $end
-$var wire 1 Jy VPB $end
-$var wire 1 Ky VPWR $end
-$scope module sc_cell $end
-$var wire 1 Fy HI $end
-$var wire 1 Gy LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[20] $end
-$var wire 1 Ly HI $end
-$var wire 1 My LO $end
-$var wire 1 Ny VGND $end
-$var wire 1 Oy VNB $end
-$var wire 1 Py VPB $end
-$var wire 1 Qy VPWR $end
-$scope module sc_cell $end
-$var wire 1 Ly HI $end
-$var wire 1 My LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[21] $end
-$var wire 1 Ry HI $end
-$var wire 1 Sy LO $end
-$var wire 1 Ty VGND $end
-$var wire 1 Uy VNB $end
-$var wire 1 Vy VPB $end
-$var wire 1 Wy VPWR $end
-$scope module sc_cell $end
-$var wire 1 Ry HI $end
-$var wire 1 Sy LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[22] $end
-$var wire 1 Xy HI $end
-$var wire 1 Yy LO $end
-$var wire 1 Zy VGND $end
-$var wire 1 [y VNB $end
-$var wire 1 \y VPB $end
-$var wire 1 ]y VPWR $end
-$scope module sc_cell $end
-$var wire 1 Xy HI $end
-$var wire 1 Yy LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[23] $end
-$var wire 1 ^y HI $end
-$var wire 1 _y LO $end
-$var wire 1 `y VGND $end
-$var wire 1 ay VNB $end
-$var wire 1 by VPB $end
-$var wire 1 cy VPWR $end
-$scope module sc_cell $end
-$var wire 1 ^y HI $end
-$var wire 1 _y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[24] $end
-$var wire 1 dy HI $end
-$var wire 1 ey LO $end
-$var wire 1 fy VGND $end
-$var wire 1 gy VNB $end
-$var wire 1 hy VPB $end
-$var wire 1 iy VPWR $end
-$scope module sc_cell $end
-$var wire 1 dy HI $end
-$var wire 1 ey LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[25] $end
-$var wire 1 jy HI $end
-$var wire 1 ky LO $end
-$var wire 1 ly VGND $end
-$var wire 1 my VNB $end
-$var wire 1 ny VPB $end
-$var wire 1 oy VPWR $end
-$scope module sc_cell $end
-$var wire 1 jy HI $end
-$var wire 1 ky LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[26] $end
-$var wire 1 py HI $end
-$var wire 1 qy LO $end
-$var wire 1 ry VGND $end
-$var wire 1 sy VNB $end
-$var wire 1 ty VPB $end
-$var wire 1 uy VPWR $end
-$scope module sc_cell $end
-$var wire 1 py HI $end
-$var wire 1 qy LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[27] $end
-$var wire 1 vy HI $end
-$var wire 1 wy LO $end
-$var wire 1 xy VGND $end
-$var wire 1 yy VNB $end
-$var wire 1 zy VPB $end
-$var wire 1 {y VPWR $end
-$scope module sc_cell $end
-$var wire 1 vy HI $end
-$var wire 1 wy LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[28] $end
-$var wire 1 |y HI $end
-$var wire 1 }y LO $end
-$var wire 1 ~y VGND $end
-$var wire 1 !z VNB $end
-$var wire 1 "z VPB $end
-$var wire 1 #z VPWR $end
-$scope module sc_cell $end
-$var wire 1 |y HI $end
-$var wire 1 }y LO $end
-$upscope $end
-$upscope $end
-$scope module mask_rev_value[29] $end
-$var wire 1 $z HI $end
-$var wire 1 %z LO $end
-$var wire 1 &z VGND $end
-$var wire 1 'z VNB $end
-$var wire 1 (z VPB $end
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-$scope module sc_cell $end
-$var wire 1 $z HI $end
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-$upscope $end
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-$var wire 1 *z HI $end
-$var wire 1 +z LO $end
-$var wire 1 ,z VGND $end
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-$scope module sc_cell $end
-$var wire 1 *z HI $end
-$var wire 1 +z LO $end
-$upscope $end
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-$scope module mask_rev_value[31] $end
-$var wire 1 0z HI $end
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-$var wire 1 2z VGND $end
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-$scope module sc_cell $end
-$var wire 1 0z HI $end
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-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
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-12

verilog/dv/caravel/mgmt_soc/gpio/make.log

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/make.log b/verilog/dv/caravel/mgmt_soc/gpio/make.log
new file mode 100644
index 0000000..7ce024a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/make.log
@@ -0,0 +1,2 @@
+vvp gpio.vvp
+make: *** [Makefile:21: gpio.vcd] Interrupt

verilog/rtl/chip_io.v

diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index bd359b9..82df32d 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -4,12 +4,12 @@
     	inout  vdd1v8,
     	inout  vss,
 	inout  gpio,
-	inout  clock,
-	inout  resetb,
+	input  clock,
+	input  resetb,
 	output flash_csb,
 	output flash_clk,
-	output flash_io0,
-	output flash_io1,
+	inout  flash_io0,
+	inout  flash_io1,
 	// Chip Core Interface
 	output porb_h,
 	output clock_core,

verilog/rtl/pads.v

diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index ad2ac30..472f6ec 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -7,7 +7,7 @@
 	.vswitch(vdd3v3),\
 	.vddio_q(vddio_q),\
 	.vcchib(vdd1v8),\
-	.vddio(vdd),\
+	.vddio(vdd3v3),\
 	.vccd(vdd1v8),\
 	.vssio(vss),\
 	.vssd(vss),\