Added DSIM to the simulation makefiles
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
index 80b942f..9eba549 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -20,11 +20,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
index 31f295b..4d47f98 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
index ddbb6a0..d50e261 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
index 2d8184e..1f5ee62 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
index c6dda4b..4969c6a 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
index dda0128..c08b51f 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
index 35d89c6..c60b5af 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -20,11 +20,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile
index ae67b2a..dace1f7 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -20,11 +20,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
index d6550a4..351c740 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -20,11 +20,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile
index 04b127e..641a453 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -17,11 +17,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
index 6101741..e054fa8 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -20,11 +20,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
index 19aa2ca..e421c20 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -21,11 +21,11 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DGL -I $(BEHAVIOURAL_MODELS) \
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
