| commit | 2adba1022dc305c913c6b2bce00149b2a8a8c966 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Oct 19 18:22:43 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Oct 19 18:22:43 2020 +0200 |
| tree | 79255a39e380ec7f63b383a7b7d0438db167b38f | |
| parent | 60aeb5f8651cd88e3b7cb1b4982f6a992e6eef48 [diff] |
Fix typos in parameter names
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 8b143db..841ef64 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -58,8 +58,8 @@ /*--------------------------------------*/ user_proj_example #( - .IO_PADS(`MPRJ_IO_PADS), - .PWR_PADS(`MPRJ_PWR_PADS) + .IO_PADS(IO_PADS), + .PWR_PADS(PWR_PADS) ) mprj ( .vdda1(vdda1), // User area 1 3.3V power .vdda2(vdda2), // User area 2 3.3V power