FWRISC-S is a Featherweight RISC-V implementation of the RV32IMC instruction set with IoT-appropriate security features. This implementation supports the integer instructions, registers, CSRs, and exceptions as required by the RISC-V spec.
This revision of the core was created for the 2019 RISC-V security contest: https://riscv.org/2019/07/risc-v-softcpu-core-contest/
FWRISC is a non-pipelined processor that aims to balance performance with FPGA resource utilization. It achieves 0.15 DMIPS/Mhz.
FWRISC correctly runs all RISCV RV32I compliance tests. It also supports the Zephyr RTOS.
FWRISC-S implements Data Execution Prevention, as a way to prevent arbitrary code execution. While more-complex protection techniques are appropriate for more-complex systems, IoT systems typically run a fixed program that can be easily protected in this way. The Zephyr SoC-support configuration has been setup such that data execution prevention is configured just after kernel boot. Using linker symbols, the configuration programs CSRs to only allow execution in the text section of the image. See Zephyr for more information.
The bare FWRISC-S 1.0.0 core consumes the following resources:
See the Quickstart document to get started with FWRISC. For more detailed information, see the documents below.