| commit | 8330b6eae89e32c5d6ed7c7a1f54691557498a79 | [log] [tgz] |
|---|---|---|
| author | Matthew Ballance <matt.ballance@gmail.com> | Mon Dec 14 18:49:52 2020 -0800 |
| committer | Matthew Ballance <matt.ballance@gmail.com> | Mon Dec 14 18:49:52 2020 -0800 |
| tree | 802d3f2039d90745ab07c395a75bf3756fef17c3 | |
| parent | 7703a4446163aaa1f8b465bd667aff8f6dff5a3f [diff] |
Reduce density in user_proj_example to remove DRC errors Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
FWPayload is a small processor+peripherals subsystem, targeting the user-project area of Caraval.
FWPayload is taking Option #1 for integration into Caravel. Specifically, FWPayload is integrated into a customized version of user_proj_example (stored in verilog/rtl/fwpayload/user_proj_example.v). The config in openlane/user_proj_example creates a macro from this description, and that macro is integrated into user_project_wrapper using the provided configuration.
Openlane completes on user_proj_example with no DRC errors, and the following antenna violations:
Number of pins violated: 52 Number of nets violated: 51 Total number of nets: 34963
Running with diode-insertion strategy 3 (default) results in the following:
Number of pins violated: 193 Number of nets violated: 146 Total number of nets: 34963 [INFO]: Generating Final Summary Report... [SUCCESS]: Flow Completed Without Fatal Errors.
Integration tests pass for both RTL and gate-level simulations.
Caravel files (.gds,.lef,etc) have been copied from caravel/mpw-one-a tag on 20201206. A merged .gds is created by running the ‘ship’ target. The result is:
221398 problems occurred. See feedback entries. Using technology "sky130A", version 1.0.72-0-gb427e3b
{{PROGRESS}} Executing Step 4 of 4: Checking DRC Violations.
{{PROGRESS}} Running DRC Checks...
{{FAIL}} DRC Checks on GDS-II Failed, Reason: Total # of DRC violations is 21405435
TEST FAILED AT STEP 4
FWPayload uses several pieces of external IP. Some are bundled with the project, and some are fetched during the project-initialization step.
RISC-V core originally targeted for FPGA application
Parameterized Wishbone interconnect
SPI master IP, obtained from the Caravel repository. Bundled with the project.
UART IP, obtained from the Caravel repository. Bundled with the project.
The FWPayload memory map is designed to fit within the 28-bit user-area portion of the Caravel memory map.
0 (i) - unused 1 (i) - unused 2 (i) - unused 3 (i) - unused 4 (i) - unused 5 (i) - unused 6 (i) - unused 7 (i) - unused 8 (i) - unused 9 (i) - unused 10 (i) - unused 11 (i) - unused 12 (o) - GPIO-out [0] 13 (o) - GPIO-out [1] 14 (o) - GPIO-out [2] 15 (o) - GPIO-out [3] 16 (o) - UART Tx 17 (i) - UART Rx 18 (i) - SPI SDI 19 (o) - SPI CSB 20 (o) - SPI SCK 21 (o) - SPI SDO 22 (o) - SPI SDOENB 23 (o) - GPIO-out [4] 24 (o) - GPIO-out [5] 25 (o) - GPIO-out [6] 26 (o) - GPIO-out [7] 27 (i) - GPIO-in [0] 28 (i) - GPIO-in [1] 29 (i) - GPIO-in [2] 30 (i) - GPIO-in [3] 31 (i) - GPIO-in [4] 32 (i) - GPIO-in [5] 33 (i) - GPIO-in [6] 34 (i) - GPIO-in [7] 35 (i) - unused 36 (i) - unused 37 (i) - unused
FWPayload uses the Caravel logic analyzer to configure reset and clocking, probe the program counter of the FWRISC, and optionally, single-step the clock.
The FWPayload project uses IVPM (IP and Verification Package Manager) to manage external IP and Python dependencies. The project can be setup both with and without IVPM installed.
In both cases, setting up the project will result in creation of a packages directory within the project that contains external IPs and required Python packages.
Ensure IVPM is installed:
% pip3 install ivpm --user --upgrade
% cd <fwpayload_dir> % ivpm update
The project can also be setup without installing IVPM. The bootstrap.sh script is provided for this purpose. bootstrap.sh clones a local copy of ivpm.
% cd <fwpayload_dir> % ./bootstrap.sh
Testing of the fwpayload subsystem is done using a cocotb test environment. The block diagram is shown below:
Bus Functional Models (BFMs) are used to drive the Caravel management interface and logic-analyzer pins.
fwrisc_gpio
mgmt_mem_access
Individual tests are run from the dv/ directory by running ‘make’.
% cd dv/fwrisc_gpio % make clean % make
Test behavior is controlled using environment variables.