Skeleton user_project_wrapper
Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
diff --git a/Makefile b/Makefile
index 463947e..6c51043 100644
--- a/Makefile
+++ b/Makefile
@@ -16,7 +16,6 @@
.PHONY: verify
verify:
echo "verify"
- $(MAKE) -C dv
diff --git a/README.md b/README.md
index 249b9d3..5d87f7a 100644
--- a/README.md
+++ b/README.md
@@ -144,18 +144,12 @@
Openlane completes on fwpayload with the following status:
```
-0.25
-Number of pins violated: 479
-Number of nets violated: 297
-Total number of nets: 44367
+Number of pins violated: 321
+Number of nets violated: 201
+Total number of nets: 44783
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.
-0.15
-Number of pins violated: 509
-Number of nets violated: 360
-Total number of nets: 44404
-
```
Integrating the fwpayload macro into user_project_wrapper is currently
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..01dc308
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,39 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#set ::env(DESIGN_NAME) fwpayload
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2700 3700"
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+
+set vlog_files ""
+set vlog_bb_files ""
+lappend vlog_files "$script_dir/../../verilog/rtl/user_project_wrapper.v"
+lappend vlog_bb_files "$script_dir/../../verilog/rtl/fwpayload.v"
+
+set incdirs ""
+lappend incdirs $script_dir/../../packages/fwrisc/rtl
+lappend incdirs $script_dir/../../packages/fwprotocol-defs/src/sv
+
+puts "vlog_files=$vlog_files"
+puts "incdirs=$incdirs"
+
+set ::env(VERILOG_INCLUDE_DIRS) "$incdirs"
+set ::env(VERILOG_FILES) "$vlog_files"
+
+set ::env(VERILOG_FILES_BLACKBOX) "$vlog_bb_files"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/fwpayload.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/fwpayload.gds"
+
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
new file mode 100644
index 0000000..cfb71de
--- /dev/null
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,35 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag user_project_wrapper -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+place_io
+
+#add_macro_placement mprj 1355 3000 N
+add_macro_placement fwpayload 1355 3000 N
+
+manual_macro_placement f
+
+global_routing_or
+detailed_routing
+
+run_magic
+run_magic_spice_export
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(tritonRoute_result_file_tag).def \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+run_magic_drc
+
+run_lvs; # requires run_magic_spice_export
+
+run_antenna_check
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
new file mode 100644
index 0000000..f6d953c
--- /dev/null
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -0,0 +1,47 @@
+# Power nets
+set ::power_nets $::env(_VDD_NET_NAME)
+set ::ground_nets $::env(_GND_NET_NAME)
+
+pdngen::specify_grid stdcell {
+ name grid
+ core_ring {
+ met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
+ met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
+ }
+ rails {
+ }
+ straps {
+ met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
+ met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
+ }
+ connect {{met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ instance "obs_core_obs"
+ power_pins $::env(_VDD_NET_NAME)
+ ground_pins $::env(_GND_NET_NAME)
+ blockages "li1 met1 met2 met3 met4 met5"
+ straps {
+ }
+ connect {}
+}
+
+
+pdngen::specify_grid macro {
+ power_pins $::env(_VDD_NET_NAME)
+ ground_pins $::env(_GND_NET_NAME)
+ blockages ""
+ straps {
+ }
+ connect {}
+}
+
+set ::halo 0
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..70640e0
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,136 @@
+#BUS_SORT
+#NR
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+vssa1
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+vssa1
+vssd1
+vdda1
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+vdda1
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+vccd1
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+vccd2
+vssa2
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+vdda2
+vssd2
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/verilog/rtl/fwpayload.v b/verilog/rtl/fwpayload.v
index 197eed1..bd4e7e0 100644
--- a/verilog/rtl/fwpayload.v
+++ b/verilog/rtl/fwpayload.v
@@ -2,7 +2,49 @@
/****************************************************************************
* fwpayload.v
****************************************************************************/
-`include "wishbone_macros.svh"
+`define WB_WIRES_ARR(PREFIX,ADDR_WIDTH,DATA_WIDTH,SIZE) \
+ wire[(SIZE*ADDR_WIDTH)-1:0] PREFIX``adr; \
+ wire[(SIZE*DATA_WIDTH)-1:0] PREFIX``dat_w; \
+ wire[(SIZE*DATA_WIDTH)-1:0] PREFIX``dat_r; \
+ wire[SIZE-1:0] PREFIX``cyc; \
+ wire[SIZE-1:0] PREFIX``err; \
+ wire[SIZE*(DATA_WIDTH/8)-1:0] PREFIX``sel; \
+ wire[SIZE-1:0] PREFIX``stb; \
+ wire[SIZE-1:0] PREFIX``ack; \
+ wire[SIZE-1:0] PREFIX``we
+
+`define WB_CONNECT(P_PREFIX,W_PREFIX) \
+ .P_PREFIX``adr(W_PREFIX``adr), \
+ .P_PREFIX``dat_w(W_PREFIX``dat_w), \
+ .P_PREFIX``dat_r(W_PREFIX``dat_r), \
+ .P_PREFIX``cyc(W_PREFIX``cyc), \
+ .P_PREFIX``err(W_PREFIX``err), \
+ .P_PREFIX``sel(W_PREFIX``sel), \
+ .P_PREFIX``stb(W_PREFIX``stb), \
+ .P_PREFIX``ack(W_PREFIX``ack), \
+ .P_PREFIX``we(W_PREFIX``we)
+
+`define WB_CONNECT_ARR(P_PREFIX,W_PREFIX,INDEX,ADDR_WIDTH,DATA_WIDTH) \
+ .P_PREFIX``adr(W_PREFIX``adr[(INDEX)*(ADDR_WIDTH)+:(ADDR_WIDTH)]), \
+ .P_PREFIX``dat_w(W_PREFIX``dat_w[(INDEX)*(DATA_WIDTH)+:(DATA_WIDTH)]), \
+ .P_PREFIX``dat_r(W_PREFIX``dat_r[(INDEX)*(DATA_WIDTH)+:(DATA_WIDTH)]), \
+ .P_PREFIX``cyc(W_PREFIX``cyc[INDEX]), \
+ .P_PREFIX``err(W_PREFIX``err[INDEX]), \
+ .P_PREFIX``sel(W_PREFIX``sel[(INDEX)*(DATA_WIDTH/8)+:(DATA_WIDTH/8)]), \
+ .P_PREFIX``stb(W_PREFIX``stb[INDEX]), \
+ .P_PREFIX``ack(W_PREFIX``ack[INDEX]), \
+ .P_PREFIX``we(W_PREFIX``we[INDEX])
+
+`define WB_WIRES_ARR(PREFIX,ADDR_WIDTH,DATA_WIDTH,SIZE) \
+ wire[(SIZE*ADDR_WIDTH)-1:0] PREFIX``adr; \
+ wire[(SIZE*DATA_WIDTH)-1:0] PREFIX``dat_w; \
+ wire[(SIZE*DATA_WIDTH)-1:0] PREFIX``dat_r; \
+ wire[SIZE-1:0] PREFIX``cyc; \
+ wire[SIZE-1:0] PREFIX``err; \
+ wire[SIZE*(DATA_WIDTH/8)-1:0] PREFIX``sel; \
+ wire[SIZE-1:0] PREFIX``stb; \
+ wire[SIZE-1:0] PREFIX``ack; \
+ wire[SIZE-1:0] PREFIX``we
`ifndef MPRJ_IO_PADS
`define MPRJ_IO_PADS 38
