commit | 30548bff3eda10e0fd2f7b7420456f8564bf1e2c | [log] [tgz] |
---|---|---|
author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jun 11 13:58:37 2021 -0700 |
committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jun 11 13:58:37 2021 -0700 |
tree | fb108584a5562d41cdb72c7851b493b12a629a5d | |
parent | 75f011602560e21092b0ecb77e9dc6b23d3e0eaf [diff] |
caravel_fix
A RISC-V Processor instrumented for learning implemented in the user project area of the CIIC Harness (aka Caravel).
Rudder is used and improved while developing q-rib to improve tooling exprerience for aspiring ASIC designers.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Then you need to install the open_pdks prerequisite:
* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This could be done by cloning openlane and following the instructions given there to use the Makefile.
Install the required version of the PDK by running the following commands:
export PDK_ROOT=<The place where you want to install the pdk> make pdk
Then, you can learn more about the caravel chip by watching these video:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
If you will use OpenLANE to harden your design, go through the instructions in this README.md.
You must copy your synthesized gate-level-netlist for user_project_wrapper
to verilog/gl/
and overwrite user_project_wrapper.v
. Otherwise, you can point to it in info.yaml.
Note: If you're using openlane to harden your design, this should happen automatically.
Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
./gds/
in the Caravel directory.* Note: You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This section shows how.
Run the following command:
export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step> make
This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds
. You should expect ~90 magic DRC violations with the current “development” state of caravel.
To use the magic installed inside Openlane to complete the final GDS streaming out step, export the following:
export PDK_ROOT=<The location where the pdk is installed> export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned> export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc6> export CARAVEL_PATH=$(pwd)
Then, mount the docker:
docker run -it -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME
Finally, once inside the docker run the following commands:
cd $CARAVEL_PATH
make
exit
This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds
. You should expect ~90 magic DRC violations with the current “development” state of caravel.
Please make sure to run make compress
before commiting anything to your repository. Avoid having 2 versions of the gds/user_project_wrapper.gds or gds/caravel.gds one compressed and the other not compressed.
<macro>
/ : includes all configuration files used to run openlane on your project.The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: