- cd4cff7 Connected WB MI A port outputs to the wb bus by Manar · 4 years, 5 months ago
- 6bedda9 Added localparam for calculating mem address bits by Manar · 4 years, 5 months ago
- db08adb Updated default number of sram blocks for the user area by Manar · 4 years, 5 months ago
- cd41a1d Merge pull request #27 from ax3ghazy/conflict_warnings_fix by R. Timothy Edwards · 4 years, 5 months ago
- 706c312 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 5 months ago
- f46273f Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 5 months ago
- 55ec369 Connected storage area to mgmt_core by Manar · 4 years, 5 months ago
- 0cefb93 Seperated mgmt and user storage blocks base addresses by Manar · 4 years, 5 months ago
- 14f7ca0 Added storage area standalone rtl by Manar · 4 years, 5 months ago
- ec9b536 Removed storage area from mgmt_core by Manar · 4 years, 5 months ago
- d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
- 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
- 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
- ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
- e6eda80 Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 5 months ago
- 0b6219d Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 5 months ago
- 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
- 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
- 14d35ac Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
- 05ad4fc Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 5 months ago
- 2a62066 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 5 months ago
- 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
- 98a7adc Removed cross bar switch port from mgmt core by Manar · 4 years, 5 months ago
- b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
- 268a90b Merge pull request #18 from ax3ghazy/params by R. Timothy Edwards · 4 years, 5 months ago
- f757546 Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 4 years, 5 months ago
- 2adba10 Fix typos in parameter names by Ahmed Ghazy · 4 years, 5 months ago
- 6d9739d Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 5 months ago
- 81d5a89 Move wire declarations before they're first used by Ahmed Ghazy · 4 years, 5 months ago
- b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 6 months ago
- 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 6 months ago
- e2ef673 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 6 months ago
- 4c73335 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 6 months ago
- 7a8cbb1 Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 6 months ago
- 53d9218 Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 6 months ago
- ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
- 4286ae1 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 6 months ago
- f645a84 Finalized the voltage clamp arrangement and the total number of pads. by Tim Edwards · 4 years, 6 months ago
- 3245e2f Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 6 months ago
- bb3cd69 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 4 years, 6 months ago
- 8115320 Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 4 years, 6 months ago
- 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 6 months ago
- b78e1c1 Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 4 years, 6 months ago
- b3cef09 Removed temporary file. by Tim Edwards · 4 years, 6 months ago
- 5ae07d9 Corrected the error causing the failure of the GPIO testbench. by Tim Edwards · 4 years, 6 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
- 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago
- ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
- f51dd08 Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 6 months ago
- 89f0924 Made corrections; GPIO testbench now passes. by Tim Edwards · 4 years, 6 months ago
- 251e0df Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
- 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
- 61bfc1f Corrected the primary issue with simulation, which was the failure by Tim Edwards · 4 years, 6 months ago
- c18c474 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
- 04ba17f Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
- c5265b8 Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 4 years, 6 months ago
- ef8312e Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 6 months ago
- 0d14e6e harness phase1 initial commit by shalan · 4 years, 7 months ago
- fd13eb5 initial commit by shalan · 4 years, 7 months ago
- cd64af5 Started adding RTL for the Caravel project by Tim Edwards · 4 years, 8 months ago
