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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-019 / 706c31202f3b1c86ff2dbfe49bb0cca6dae2e331 / verilog
  1. 706c312 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 5 months ago
  2. f46273f Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 5 months ago
  3. ec9b536 Removed storage area from mgmt_core by Manar · 4 years, 5 months ago
  4. d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
  5. 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
  6. 3a1e353 Fix another 36->37 typo in mem_tb.v by Ahmed Ghazy · 4 years, 5 months ago
  7. cfe7653 Corrected the timer testbenches for minor count differences due to by Tim Edwards · 4 years, 5 months ago
  8. 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
  9. ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
  10. e6eda80 Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 5 months ago
  11. 0b6219d Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 5 months ago
  12. 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
  13. 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
  14. 14d35ac Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
  15. 05ad4fc Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 5 months ago
  16. 2a62066 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 5 months ago
  17. 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
  18. 98a7adc Removed cross bar switch port from mgmt core by Manar · 4 years, 5 months ago
  19. b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
  20. 268a90b Merge pull request #18 from ax3ghazy/params by R. Timothy Edwards · 4 years, 5 months ago
  21. 1c1b462 Merge pull request #17 from Manarabdelaty/release by R. Timothy Edwards · 4 years, 5 months ago
  22. 4533150 Merge pull request #16 from ax3ghazy/mkq by R. Timothy Edwards · 4 years, 5 months ago
  23. f757546 Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 4 years, 5 months ago
  24. 2adba10 Fix typos in parameter names by Ahmed Ghazy · 4 years, 5 months ago
  25. 6d9739d Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 5 months ago
  26. 7ea4895 Fixed sysctrl unit test by Manar · 4 years, 5 months ago
  27. ba04b40 Allow PDK_PATH to be user-specified by Ahmed Ghazy · 4 years, 5 months ago
  28. 81d5a89 Move wire declarations before they're first used by Ahmed Ghazy · 4 years, 5 months ago
  29. 63c933f Removed VCD and hex files, which should not be in the repository. by Tim Edwards · 4 years, 5 months ago
  30. b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 5 months ago
  31. 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 5 months ago
  32. e2ef673 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 5 months ago
  33. 4c73335 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 5 months ago
  34. 7a8cbb1 Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 5 months ago
  35. 53d9218 Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 5 months ago
  36. ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 5 months ago
  37. 4286ae1 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 5 months ago
  38. f645a84 Finalized the voltage clamp arrangement and the total number of pads. by Tim Edwards · 4 years, 5 months ago
  39. 3245e2f Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 5 months ago
  40. 406d37f Solved the trap issue by not driving the PLL clock so fast (not sure why by Tim Edwards · 4 years, 6 months ago
  41. 9073946 Removed a small error in the PLL testbench C code. However, the by Tim Edwards · 4 years, 6 months ago
  42. bb3cd69 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 4 years, 6 months ago
  43. 8115320 Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 4 years, 6 months ago
  44. 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 6 months ago
  45. b78e1c1 Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 4 years, 6 months ago
  46. 0c03240 Updated all the testbenches to use the new split power supplies and 37-bit by Tim Edwards · 4 years, 6 months ago
  47. b3cef09 Removed temporary file. by Tim Edwards · 4 years, 6 months ago
  48. 5ae07d9 Corrected the error causing the failure of the GPIO testbench. by Tim Edwards · 4 years, 6 months ago
  49. 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
  50. 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago
  51. ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
  52. f51dd08 Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 6 months ago
  53. 89f0924 Made corrections; GPIO testbench now passes. by Tim Edwards · 4 years, 6 months ago
  54. 251e0df Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
  55. 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
  56. 61bfc1f Corrected the primary issue with simulation, which was the failure by Tim Edwards · 4 years, 6 months ago
  57. c18c474 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
  58. 04ba17f Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
  59. 49e2c18 Some minor updates to the testbench Makefiles and verilog. by Tim Edwards · 4 years, 6 months ago
  60. c5265b8 Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 4 years, 6 months ago
  61. ef8312e Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 6 months ago
  62. 0d14e6e harness phase1 initial commit by shalan · 4 years, 7 months ago
  63. fd13eb5 initial commit by shalan · 4 years, 7 months ago
  64. cd64af5 Started adding RTL for the Caravel project by Tim Edwards · 4 years, 8 months ago
  65. 33de054 populated the project with data subfolders. by mkk · 4 years, 8 months ago