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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-019 / 581068fea64d0d978f060a259cfbb2756bc88e90 / verilog / rtl / user_project_wrapper.v
  1. 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
  2. 08cd6eb add default nettype none by Matt Venn · 4 years, 4 months ago
  3. 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
  4. b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
  5. 2adba10 Fix typos in parameter names by Ahmed Ghazy · 4 years, 5 months ago
  6. b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 6 months ago