- 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 6 months ago
- b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 6 months ago
- b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 7 months ago
- 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 7 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 7 months ago
- ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 7 months ago
- f51dd08 Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 7 months ago
- 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 7 months ago
- ef8312e Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 7 months ago[Renamed (71%) from verilog/dv/harness/defs.h]
- 0d14e6e harness phase1 initial commit by shalan · 4 years, 8 months ago[Renamed (66%) from verilog/dv/harness/mgmt_soc/defs.h]
- fd13eb5 initial commit by shalan · 4 years, 8 months ago
