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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-019 / 0a6a4476b97c00cefac7d01667b8ef4a68c0f3fb / verilog / rtl / user_proj_example.v
  1. b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
  2. 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 6 months ago
  3. ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
  4. 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
  5. 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago[Renamed (75%) from verilog/rtl/mprj_counter.v]
  6. 0d14e6e harness phase1 initial commit by shalan · 4 years, 7 months ago