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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-019/f5aadd4db93538e819357a3496dd3d0fa2fb3c62^!/.
commit
f5aadd4db93538e819357a3496dd3d0fa2fb3c62
[log]
author
Diego Hernando <djhernando96@gmail.com>
Wed Dec 16 00:58:47 2020 -0300
committer
Diego Hernando <djhernando96@gmail.com>
Wed Dec 16 00:58:47 2020 -0300
tree
50b0037cb308225c2124ec730c61df392065d8cd
parent
6ea9a858d8f1e3e8e5e41d1455ba182d08bfd9ed [diff]
Added schematics and netlists

diff --git a/xschem/netlist/bsim4v5.out b/xschem/netlist/bsim4v5.out
new file mode 100644
index 0000000..d9a142e
--- /dev/null
+++ b/xschem/netlist/bsim4v5.out

@@ -0,0 +1,5 @@
+BSIM4v5: Berkeley Short Channel IGFET Model-4
+Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
+
+++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
+Model = x1.xm1:sky130_fd_pr__pfet_01v8__model.24

diff --git a/xschem/netlist/opamp.spice b/xschem/netlist/opamp.spice
new file mode 100644
index 0000000..47f53a4
--- /dev/null
+++ b/xschem/netlist/opamp.spice

@@ -0,0 +1,28 @@
+**.subckt opamp vdd vss vin_n vin_p iref vout
+*.iopin vdd
+*.iopin vss
+*.ipin vin_n
+*.ipin vin_p
+*.ipin iref
+*.opin vout
+XM1 vbn vin_n vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM2 voe1 vin_p vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM3 vbn vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM4 voe1 vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM5 vp iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM7 vout iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+XM8 iref iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=15 m=15 
+XM9 net1 vdd voe1 vss sky130_fd_pr__nfet_01v8 W=0.75 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=6 m=6 
+XC1 net1 vout sky130_fd_pr__cap_mim_m3_1 W=17.55 L=15 MF=6 m=6
+XM6 vout voe1 vss vss sky130_fd_pr__nfet_01v8 W=4.5 L=0.45 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+**.ends
+.end

diff --git a/xschem/netlist/opamp_closeloop.spice b/xschem/netlist/opamp_closeloop.spice
new file mode 100644
index 0000000..9e39f56
--- /dev/null
+++ b/xschem/netlist/opamp_closeloop.spice

@@ -0,0 +1,128 @@
+**.subckt opamp_closeloop
+V1 vss GND DC{vss} 
+V2 vdd vss DC{vdd} 
+V4 vsen vcm sin(0 {vac} 1Meg) dc 0 ac 1 
+C4 vsen vin_signal 1 m=1
+I0 net1 vss DC{iref} 
+R1 vin vin_signal 500 m=1
+R3 vout vin 5k m=1
+C5 vin vss 5p m=1
+x1 vdd net1 vin vcm vout vss opamp
+C1 vout vss 20p m=1
+V5 vcm vss DC{vcm} 
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM5.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM8.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulations
+.control
+  ac dec 100 1k 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1k
+  *meas ac PM find vp(vout) when vdb(vout)=0
+  *print PM*180/PI
+  *meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) {vp(vout)*180/PI}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_ac1.raw
+
+  reset
+  tran 0.01u 11u
+  setplot tran1
+  plot v(vsen) v(vout)
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_tran1.raw
+
+  reset
+  noise v(vout) V4 dec 100 1k 10G 1
+  setplot noise1
+  plot inoise_spectrum onoise_spectrum
+  *print inoise_spectrum
+  *print onoise_spectrum
+  setplot noise2
+  *plot inoise_total onoise_total
+  print inoise_total
+  print onoise_total
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_noise.raw
+
+  reset
+  op
+  setplot op1
+  print vout
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_op1.raw
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  opamp.sym # of pins=6
+
+.subckt opamp  vdd iref vin_n vin_p vout vss
+*.iopin vdd
+*.iopin vss
+*.ipin vin_n
+*.ipin vin_p
+*.ipin iref
+*.opin vout
+XM1 vbn vin_n vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM2 voe1 vin_p vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM3 vbn vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM4 voe1 vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM5 vp iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM7 vout iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+XM8 iref iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=15 m=15 
+XM9 net1 vdd voe1 vss sky130_fd_pr__nfet_01v8 W=0.75 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=6 m=6 
+XC1 net1 vout sky130_fd_pr__cap_mim_m3_1 W=15 L=17.55 MF=6 m=6
+XM6 vout voe1 vss vss sky130_fd_pr__nfet_01v8 W=4.5 L=0.45 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/netlist/opamp_closeloop_rpad.spice b/xschem/netlist/opamp_closeloop_rpad.spice
new file mode 100644
index 0000000..d3a3261
--- /dev/null
+++ b/xschem/netlist/opamp_closeloop_rpad.spice

@@ -0,0 +1,130 @@
+**.subckt opamp_closeloop_rpad
+V1 vss GND DC{vss} 
+V2 vdd vss DC{vdd} 
+V4 vsen vcm sin(0 {vac} 1Meg) dc 0 ac 1 
+C4 vsen vin_signal 1 m=1
+I0 net1 vss DC{iref} 
+R1 vin vin_signal 500 m=1
+R3 vout vin 5k m=1
+C5 vin vss 5p m=1
+x1 vdd net1 net2 vcm net3 vss opamp
+C1 vout vss 20p m=1
+V5 vcm vss DC{vcm} 
+R2 net2 vin 150 m=1
+R4 vout net3 150 m=1
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM5.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM8.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulations
+.control
+  ac dec 100 1k 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1k
+  *meas ac PM find vp(vout) when vdb(vout)=0
+  *print PM*180/PI
+  *meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) {vp(vout)*180/PI}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_ac1.raw
+
+  reset
+  tran 0.01u 11u
+  setplot tran1
+  plot v(vsen) v(vout)
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_tran1.raw
+
+  reset
+  noise v(vout) V4 dec 100 1k 10G 1
+  setplot noise1
+  plot inoise_spectrum onoise_spectrum
+  *print inoise_spectrum
+  *print onoise_spectrum
+  setplot noise2
+  *plot inoise_total onoise_total
+  print inoise_total
+  print onoise_total
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_noise.raw
+
+  reset
+  op
+  setplot op1
+  print vout
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_op1.raw
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  opamp.sym # of pins=6
+
+.subckt opamp  vdd iref vin_n vin_p vout vss
+*.iopin vdd
+*.iopin vss
+*.ipin vin_n
+*.ipin vin_p
+*.ipin iref
+*.opin vout
+XM1 vbn vin_n vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM2 voe1 vin_p vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM3 vbn vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM4 voe1 vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM5 vp iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM7 vout iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+XM8 iref iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=15 m=15 
+XM9 net1 vdd voe1 vss sky130_fd_pr__nfet_01v8 W=0.75 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=6 m=6 
+XC1 net1 vout sky130_fd_pr__cap_mim_m3_1 W=15 L=17.55 MF=6 m=6
+XM6 vout voe1 vss vss sky130_fd_pr__nfet_01v8 W=4.5 L=0.45 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/netlist/opamp_openloop.spice b/xschem/netlist/opamp_openloop.spice
new file mode 100644
index 0000000..1b2a719
--- /dev/null
+++ b/xschem/netlist/opamp_openloop.spice

@@ -0,0 +1,113 @@
+**.subckt opamp_openloop
+V1 vss GND DC{vss} 
+V2 vdd vss DC{vdd} 
+V3 vcm vss DC{vcm} 
+V4 vsen vcm sin(0 {vac} 1Meg) dc 0 ac 1 
+C4 vsen vin 1 m=1
+I0 net1 vss DC{iref} 
+R1 ve vcm 500 m=1
+R2 vin ve 1G m=1
+R3 vout ve 5k m=1
+C5 vin vss 5p m=1
+C1 vout vss 20p m=1
+x1 vdd net1 vin vcm vout vss opamp
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+*.lib /home/dhernando/projects/foundry/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
+*.lib  ~/fulgor-opamp-sky130/xschem/sky130.lib TT
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib fs
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM5.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM8.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulation
+.control
+
+  ac dec 100 1 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1
+  meas ac PM find vp(vout) when vdb(vout)=0
+  print PM*180/PI
+  meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) {vp(vout)*180/PI}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_ac1.raw
+
+  reset
+  op
+  setplot op1
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_op1.raw
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  opamp.sym # of pins=6
+
+.subckt opamp  vdd iref vin_n vin_p vout vss
+*.iopin vdd
+*.iopin vss
+*.ipin vin_n
+*.ipin vin_p
+*.ipin iref
+*.opin vout
+XM1 vbn vin_n vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM2 voe1 vin_p vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM3 vbn vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM4 voe1 vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM5 vp iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM7 vout iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+XM8 iref iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=15 m=15 
+XM9 net1 vdd voe1 vss sky130_fd_pr__nfet_01v8 W=0.75 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=6 m=6 
+XC1 net1 vout sky130_fd_pr__cap_mim_m3_1 W=17.55 L=15 MF=6 m=6
+XM6 vout voe1 vss vss sky130_fd_pr__nfet_01v8 W=4.5 L=0.45 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/netlist/opamp_openloop_rpad.spice b/xschem/netlist/opamp_openloop_rpad.spice
new file mode 100644
index 0000000..cc50390
--- /dev/null
+++ b/xschem/netlist/opamp_openloop_rpad.spice

@@ -0,0 +1,115 @@
+**.subckt opamp_openloop_rpad
+V1 vss GND DC{vss} 
+V2 vdd vss DC{vdd} 
+V3 vcm vss DC{vcm} 
+V4 vsen vcm sin(0 {vac} 1Meg) dc 0 ac 1 
+C4 vsen vin 1 m=1
+I0 net1 vss DC{iref} 
+R1 ve vcm 500 m=1
+R2 vin ve 1G m=1
+R3 vout ve 5k m=1
+C5 vin vss 5p m=1
+C1 vout vss 20p m=1
+x1 vdd net1 net3 vcm net2 vss opamp
+R4 net3 vin 150 m=1
+R5 vout net2 150 m=1
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+*.lib /home/dhernando/projects/foundry/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
+*.lib  ~/fulgor-opamp-sky130/xschem/sky130.lib TT
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM5.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]  @M.X1.XM8.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++  @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulation
+.control
+
+  ac dec 100 1 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1
+  meas ac PM find vp(vout) when vdb(vout)=0
+  print PM*180/PI
+  meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) {vp(vout)*180/PI}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_ac1.raw
+
+  reset
+  op
+  setplot op1
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_op1.raw
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  opamp.sym # of pins=6
+
+.subckt opamp  vdd iref vin_n vin_p vout vss
+*.iopin vdd
+*.iopin vss
+*.ipin vin_n
+*.ipin vin_p
+*.ipin iref
+*.opin vout
+XM1 vbn vin_n vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM2 voe1 vin_p vp vp sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=200 m=200 
+XM3 vbn vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM4 voe1 vbn vss vss sky130_fd_pr__nfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=30 m=30 
+XM5 vp iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=60 m=60 
+XM7 vout iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+XM8 iref iref vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.3 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=15 m=15 
+XM9 net1 vdd voe1 vss sky130_fd_pr__nfet_01v8 W=0.75 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=12 m=12 
+XC1 net1 vout sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=6 m=6
+XM6 vout voe1 vss vss sky130_fd_pr__nfet_01v8 W=4.5 L=0.45 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=150 m=150 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/sch/opamp.sch b/xschem/sch/opamp.sch
new file mode 100644
index 0000000..d7413ac
--- /dev/null
+++ b/xschem/sch/opamp.sch

@@ -0,0 +1,193 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1290 -35 1290 40 { lab=vss}
+N 1570 -35 1570 40 { lab=vss}
+N 1290 40 1357.5 40 { lab=vss}
+N 1357.5 40 1570 40 { lab=vss}
+N 1370 -135 1370 -65 { lab=vbn}
+N 1210 -65 1290 -65 { lab=vss}
+N 1210 -65 1210 40 { lab=vss}
+N 1210 40 1290 40 { lab=vss}
+N 1570 -65 1637.5 -65 { lab=vss}
+N 1637.5 -65 1637.5 40 { lab=vss}
+N 1570 -240 1570 -95 { lab=voe1}
+N 1290 -360 1290 -300 { lab=vp}
+N 1290 -360 1570 -360 { lab=vp}
+N 1570 -360 1570 -300 { lab=vp}
+N 1287.5 -270 1350 -270 { lab=vp}
+N 1350 -360 1350 -270 { lab=vp}
+N 1507.5 -360 1507.5 -270 { lab=vp}
+N 1430 -410 1430 -360 { lab=vp}
+N 1890 -472.5 1890 -470 { lab=vdd}
+N 1890 -500 1890 -472.5 { lab=vdd}
+N 1430 -500 1890 -500 { lab=vdd}
+N 1430 -500 1430 -470 { lab=vdd}
+N 1887.5 -440 1967.5 -440 { lab=vdd}
+N 1967.5 -500 1967.5 -440 { lab=vdd}
+N 1890 -500 1967.5 -500 { lab=vdd}
+N 1050 -500 1050 -470 { lab=vdd}
+N 1050 -500 1430 -500 { lab=vdd}
+N 1050 -360 1152.5 -360 { lab=iref}
+N 1152.5 -440 1152.5 -360 { lab=iref}
+N 1767.5 -440 1850 -440 { lab=iref}
+N 970 -440 1052.5 -440 { lab=vdd}
+N 970 -500 970 -440 { lab=vdd}
+N 970 -500 1050 -500 { lab=vdd}
+N 1430 -440 1510 -440 { lab=vdd}
+N 1510 -500 1510 -440 { lab=vdd}
+N 1370 -137.5 1370 -135 { lab=vbn}
+N 1507.5 -270 1572.5 -270 { lab=vp}
+N 1290 -240 1290 -95 { lab=vbn}
+N 1290 -137.5 1370 -137.5 { lab=vbn}
+N 1090 -440 1152.5 -440 { lab=iref}
+N 1275 -440 1390 -440 { lab=iref}
+N 1152.5 -440 1275 -440 { lab=iref}
+N 1330 -65 1530 -65 { lab=vbn}
+N 1050 -410 1050 -360 { lab=iref}
+N 1180 -270 1250 -270 { lab=vin_n}
+N 1750 -190 1800 -190 { lab=#net1}
+N 1720 -250 1720 -230 { lab=vdd}
+N 1720 -190 1720 -110 { lab=vss}
+N 1570 -190 1690 -190 { lab=voe1}
+N 1860 -190 1890 -190 { lab=vout}
+N 950 -500 970 -500 { lab=vdd}
+N 950 40 1210 40 { lab=vss}
+N 1610 -270 1670 -270 { lab=vin_p}
+N 950 -360 1050 -360 { lab=iref}
+N 1570 40 1890 40 { lab=vss}
+N 1890 40 1980 40 { lab=vss}
+N 1980 -60 1980 40 { lab=vss}
+N 1890 -60 1980 -60 { lab=vss}
+N 1670 -60 1850 -60 { lab=voe1}
+N 1670 -190 1670 -60 { lab=voe1}
+N 1890 -190 1890 -90 { lab=vout}
+N 1890 -410 1890 -190 { lab=vout}
+N 1890 -240 2030 -240 { lab=vout}
+N 1890 -30 1890 40 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 1270 -270 0 0 {name=M1
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=200
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1590 -270 0 1 {name=M2
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=200
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1310 -65 0 1 {name=M3
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=30
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1550 -65 0 0 {name=M4
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=30
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1410 -440 0 0 {name=M5
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=30
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1870 -440 0 0 {name=M7
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=150
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1070 -440 0 1 {name=M8
+L=0.3
+W=3
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=15
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1272.5 -500 0 0 {name=l1 sig_type=std_logic lab=vdd
+}
+C {lab_wire.sym} 1275 -440 0 0 {name=l2 sig_type=std_logic lab=iref
+
+}
+C {lab_wire.sym} 1405 -360 0 0 {name=l4 sig_type=std_logic lab=vp}
+C {lab_pin.sym} 1767.5 -440 0 0 {name=l5 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1442.5 40 0 0 {name=l7 sig_type=std_logic lab=vss
+}
+C {lab_wire.sym} 1977.5 -240 0 0 {name=l8 sig_type=std_logic lab=vout
+}
+C {lab_wire.sym} 1450 -65 0 0 {name=l6 sig_type=std_logic lab=vbn}
+C {sky130_fd_pr/nfet_01v8.sym} 1720 -210 1 0 {name=M9
+L=0.15
+W=0.75
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=6
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 1720 -250 2 0 {name=l9 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1720 -110 2 0 {name=l10 sig_type=std_logic lab=vss
+}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 1830 -190 3 0 {name=C1 model=cap_mim_m3_1 W=17.55 L=15 MF=6 spiceprefix=X}
+C {iopin.sym} 950 -500 2 0 {name=p1 lab=vdd}
+C {iopin.sym} 950 40 2 0 {name=p2 lab=vss}
+C {ipin.sym} 1180 -270 0 0 {name=p3 lab=vin_n}
+C {ipin.sym} 1670 -270 2 0 {name=p4 lab=vin_p}
+C {ipin.sym} 950 -360 0 0 {name=p5 lab=iref}
+C {sky130_fd_pr/nfet_01v8.sym} 1870 -60 0 0 {name=M6
+L=0.45
+W=4.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=150
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1630 -190 0 0 {name=l3 sig_type=std_logic lab=voe1}
+C {opin.sym} 2030 -240 0 0 {name=p6 lab=vout}

diff --git a/xschem/sch/opamp.sym b/xschem/sch/opamp.sym
new file mode 100644
index 0000000..52d2a6c
--- /dev/null
+++ b/xschem/sch/opamp.sym

@@ -0,0 +1,34 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 40 -30 60 {}
+L 4 -70 -20 -50 -20 {}
+L 4 -70 20 -50 20 {}
+L 4 50 0 70 0 {}
+L 4 -50 -50 -50 -0 {}
+L 4 -50 -0 -50 50 {}
+L 4 -50 50 50 -0 {}
+L 4 -50 -50 50 0 {}
+L 7 -10 -50 -10 -30 {}
+L 7 10 40 10 60 {}
+L 7 10 20 10 40 {}
+B 5 -12.5 -52.5 -7.5 -47.5 {name=vdd dir=inout name=p1 }
+B 5 -32.5 57.5 -27.5 62.5 {name=iref dir=in name=p5 }
+B 5 -72.5 -22.5 -67.5 -17.5 {name=vin_n dir=in name=p3 }
+B 5 -72.5 17.5 -67.5 22.5 {name=vin_p dir=in name=p4 }
+B 5 67.5 -2.5 72.5 2.5 {name=vout dir=out name=p6 }
+B 5 7.5 57.5 12.5 62.5 {name=vss dir=inout name=p2 }
+T {@symname} -30.5 -6 0 0 0.3 0.3 {}
+T {@name} 15 -32 0 0 0.2 0.2 {}
+T {vdd} -4 -55 3 1 0.2 0.2 {}
+T {iref} -24 55 3 0 0.2 0.2 {}
+T {vin_n} -45 -24 0 0 0.2 0.2 {}
+T {vin_p} -45 16 0 0 0.2 0.2 {}
+T {vout} 75 -14 0 1 0.2 0.2 {}
+T {vss} 24 55 1 1 0.2 0.2 {}

diff --git a/xschem/sch/opamp_closeloop.sch b/xschem/sch/opamp_closeloop.sch
new file mode 100644
index 0000000..6605bab
--- /dev/null
+++ b/xschem/sch/opamp_closeloop.sch

@@ -0,0 +1,153 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 600 -170 600 -130 { lab=GND}
+N 600 -270 600 -230 { lab=vss}
+N 700 -270 700 -230 { lab=vdd}
+N 700 -170 700 -130 { lab=vss}
+N 800 -360 800 -330 { lab=vin_signal}
+N 1210 -190 1210 -150 { lab=vss}
+N 1210 -280 1210 -250 { lab=#net1}
+N 800 -270 800 -230 { lab=vsen}
+N 800 -170 800 -130 { lab=vcm}
+N 990 -550 1050 -550 { lab=vin}
+N 980 -550 980 -360 { lab=vin}
+N 980 -550 990 -550 { lab=vin}
+N 800 -360 860 -360 { lab=vin_signal}
+N 1030 -360 1090 -360 { lab=vin}
+N 1260 -550 1310 -550 { lab=vout}
+N 1030 -250 1030 -210 { lab=vss}
+N 1030 -360 1030 -310 { lab=vin}
+N 1250 -280 1250 -260 { lab=vss}
+N 1390 -340 1390 -310 { lab=vout}
+N 1310 -340 1390 -340 { lab=vout}
+N 1390 -250 1390 -200 { lab=vss}
+N 1110 -290 1110 -250 { lab=vcm}
+N 1110 -190 1110 -150 { lab=vss}
+N 1110 -320 1110 -290 { lab=vcm}
+N 1110 -320 1170 -320 { lab=vcm}
+N 1090 -360 1170 -360 { lab=vin}
+N 920 -360 1030 -360 { lab=vin}
+N 1310 -550 1390 -550 { lab=vout}
+N 1390 -550 1390 -340 { lab=vout}
+N 1050 -550 1200 -550 { lab=vin}
+N 1230 -420 1230 -390 { lab=vdd}
+C {vsource.sym} 600 -200 0 0 {name=V1 value=DC\{vss\}}
+C {vsource.sym} 700 -200 0 0 {name=V2 value=DC\{vdd\}}
+C {gnd.sym} 600 -130 0 0 {name=l14 lab=GND}
+C {vsource.sym} 800 -200 0 0 {name=V4 value="sin(0 \{vac\} 1Meg) dc 0 ac 1"}
+C {capa.sym} 800 -300 2 0 {name=C4
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 700 -270 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 600 -270 1 0 {name=l16 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 700 -130 3 0 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -130 3 0 {name=l20 sig_type=std_logic lab=vcm}
+C {isource.sym} 1210 -220 0 0 {name=I0 value=DC\{iref\}}
+C {lab_pin.sym} 1210 -150 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 800 -250 3 0 {name=l24 sig_type=std_logic lab=vsen}
+C {res.sym} 890 -360 1 0 {name=R1
+value=500
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1230 -550 1 0 {name=R3
+value=5k
+footprint=1206
+device=resistor
+m=1}
+C {lab_pin.sym} 1030 -210 3 0 {name=l28 sig_type=std_logic lab=vss
+}
+C {capa.sym} 1030 -280 0 0 {name=C5
+m=1
+value=5p
+footprint=1206
+device="ceramic capacitor"}
+C {netlist_not_shown.sym} 650 -530 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[id] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[id] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulations
+.control
+  ac dec 100 1k 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1k
+  *meas ac PM find vp(vout) when vdb(vout)=0
+  *print PM*180/PI
+  *meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) \{vp(vout)*180/PI\}
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_ac1.raw
+  
+  reset
+  tran 0.01u 11u
+  setplot tran1
+  plot v(vsen) v(vout)
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+
+  reset    
+  noise v(vout) V4 dec 100 1k 10G 1
+  setplot noise1
+  plot inoise_spectrum onoise_spectrum
+  *print inoise_spectrum
+  *print onoise_spectrum
+  setplot noise2
+  *plot inoise_total onoise_total
+  print inoise_total
+  print onoise_total
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_noise.raw
+  
+  reset
+  op
+  setplot op1
+  print vout  
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_op1.raw
+  
+.endc
+
+.end
+"}
+C {opamp.sym} 1240 -340 0 0 {name=x1}
+C {lab_pin.sym} 1250 -260 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {capa.sym} 1390 -280 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1390 -200 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1360 -340 0 0 {name=l3 sig_type=std_logic lab=vout}
+C {lab_pin.sym} 1110 -150 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1150 -320 0 0 {name=l4 sig_type=std_logic lab=vcm}
+C {vsource.sym} 1110 -220 0 0 {name=V5 value=DC\{vcm\}}
+C {lab_wire.sym} 1110 -360 0 0 {name=l6 sig_type=std_logic lab=vin}
+C {lab_wire.sym} 840 -360 0 0 {name=l7 sig_type=std_logic lab=vin_signal}
+C {lab_pin.sym} 1230 -420 1 0 {name=l8 sig_type=std_logic lab=vdd}

diff --git a/xschem/sch/opamp_closeloop_rpad.sch b/xschem/sch/opamp_closeloop_rpad.sch
new file mode 100644
index 0000000..f42c385
--- /dev/null
+++ b/xschem/sch/opamp_closeloop_rpad.sch

@@ -0,0 +1,166 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 600 -170 600 -130 { lab=GND}
+N 600 -270 600 -230 { lab=vss}
+N 700 -270 700 -230 { lab=vdd}
+N 700 -170 700 -130 { lab=vss}
+N 800 -360 800 -330 { lab=vin_signal}
+N 1210 -190 1210 -150 { lab=vss}
+N 1210 -280 1210 -250 { lab=#net1}
+N 800 -270 800 -230 { lab=vsen}
+N 800 -170 800 -130 { lab=vcm}
+N 990 -550 1050 -550 { lab=vin}
+N 980 -550 980 -360 { lab=vin}
+N 980 -550 990 -550 { lab=vin}
+N 800 -360 860 -360 { lab=vin_signal}
+N 1030 -360 1090 -360 { lab=vin}
+N 1260 -550 1310 -550 { lab=vout}
+N 1030 -250 1030 -210 { lab=vss}
+N 1030 -360 1030 -310 { lab=vin}
+N 1250 -280 1250 -260 { lab=vss}
+N 1460 -340 1460 -310 { lab=vout}
+N 1460 -250 1460 -200 { lab=vss}
+N 1110 -290 1110 -250 { lab=vcm}
+N 1110 -190 1110 -150 { lab=vss}
+N 1110 -320 1110 -290 { lab=vcm}
+N 1110 -320 1170 -320 { lab=vcm}
+N 920 -360 1030 -360 { lab=vin}
+N 1310 -550 1390 -550 { lab=vout}
+N 1050 -550 1200 -550 { lab=vin}
+N 1230 -420 1230 -390 { lab=vdd}
+N 1150 -360 1170 -360 { lab=#net2}
+N 1400 -340 1420 -340 { lab=vout}
+N 1390 -550 1460 -550 { lab=vout}
+N 1460 -550 1460 -340 { lab=vout}
+N 1420 -340 1460 -340 { lab=vout}
+N 1310 -340 1340 -340 { lab=#net3}
+C {vsource.sym} 600 -200 0 0 {name=V1 value=DC\{vss\}}
+C {vsource.sym} 700 -200 0 0 {name=V2 value=DC\{vdd\}}
+C {gnd.sym} 600 -130 0 0 {name=l14 lab=GND}
+C {vsource.sym} 800 -200 0 0 {name=V4 value="sin(0 \{vac\} 1Meg) dc 0 ac 1"}
+C {capa.sym} 800 -300 2 0 {name=C4
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 700 -270 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 600 -270 1 0 {name=l16 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 700 -130 3 0 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -130 3 0 {name=l20 sig_type=std_logic lab=vcm}
+C {isource.sym} 1210 -220 0 0 {name=I0 value=DC\{iref\}}
+C {lab_pin.sym} 1210 -150 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 800 -250 3 0 {name=l24 sig_type=std_logic lab=vsen}
+C {res.sym} 890 -360 1 0 {name=R1
+value=500
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1230 -550 1 0 {name=R3
+value=5k
+footprint=1206
+device=resistor
+m=1}
+C {lab_pin.sym} 1030 -210 3 0 {name=l28 sig_type=std_logic lab=vss
+}
+C {capa.sym} 1030 -280 0 0 {name=C5
+m=1
+value=5p
+footprint=1206
+device="ceramic capacitor"}
+C {netlist_not_shown.sym} 650 -530 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[id] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[id] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulations
+.control
+  ac dec 100 1k 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1k
+  *meas ac PM find vp(vout) when vdb(vout)=0
+  *print PM*180/PI
+  *meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) \{vp(vout)*180/PI\}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_ac1.raw
+  
+  reset
+  tran 0.01u 11u
+  setplot tran1
+  plot v(vsen) v(vout)
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_tran1.raw
+
+  reset    
+  noise v(vout) V4 dec 100 1k 10G 1
+  setplot noise1
+  plot inoise_spectrum onoise_spectrum
+  *print inoise_spectrum
+  *print onoise_spectrum
+  setplot noise2
+  *plot inoise_total onoise_total
+  print inoise_total
+  print onoise_total
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_noise.raw
+  
+  reset
+  op
+  setplot op1
+  print vout  
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_closeloop_op1.raw
+  
+.endc
+
+.end
+"}
+C {opamp.sym} 1240 -340 0 0 {name=x1}
+C {lab_pin.sym} 1250 -260 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {capa.sym} 1460 -280 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1460 -200 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1440 -340 0 0 {name=l3 sig_type=std_logic lab=vout}
+C {lab_pin.sym} 1110 -150 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1150 -320 0 0 {name=l4 sig_type=std_logic lab=vcm}
+C {vsource.sym} 1110 -220 0 0 {name=V5 value=DC\{vcm\}}
+C {lab_wire.sym} 1070 -360 0 0 {name=l6 sig_type=std_logic lab=vin}
+C {lab_wire.sym} 840 -360 0 0 {name=l7 sig_type=std_logic lab=vin_signal}
+C {lab_pin.sym} 1230 -420 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {res.sym} 1120 -360 1 0 {name=R2
+value=150
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1370 -340 1 0 {name=R4
+value=150
+footprint=1206
+device=resistor
+m=1}

diff --git a/xschem/sch/opamp_openloop.sch b/xschem/sch/opamp_openloop.sch
new file mode 100644
index 0000000..f478e1c
--- /dev/null
+++ b/xschem/sch/opamp_openloop.sch

@@ -0,0 +1,150 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1132.5 -137.5 1132.5 -100 { lab=GND}
+N 1132.5 -237.5 1132.5 -197.5 { lab=vss}
+N 1220 -237.5 1220 -197.5 { lab=vdd}
+N 1220 -137.5 1220 -100 { lab=vss}
+N 1530 -250 1530 -210 { lab=vss}
+N 1320 -335 1320 -297.5 { lab=vin}
+N 1630 -250 1630 -210 { lab=vss}
+N 1320 -237.5 1320 -197.5 { lab=vsen}
+N 1320 -137.5 1320 -100 { lab=vcm}
+N 1210 -430 1340 -430 { lab=ve}
+N 1280 -620 1340 -620 { lab=ve}
+N 1270 -620 1270 -430 { lab=ve}
+N 1270 -620 1280 -620 { lab=ve}
+N 1090 -430 1150 -430 { lab=vcm}
+N 1400 -430 1450 -430 { lab=vin}
+N 1450 -430 1510 -430 { lab=vin}
+N 1450 -320 1450 -280 { lab=vss}
+N 1450 -430 1450 -380 { lab=vin}
+N 1630 -350 1630 -310 { lab=#net1}
+N 1670 -350 1670 -330 { lab=vss}
+N 1780 -410 1780 -390 { lab=vout}
+N 1730 -410 1780 -410 { lab=vout}
+N 1780 -330 1780 -300 { lab=vss}
+N 1650 -490 1650 -460 { lab=vdd}
+N 1540 -390 1590 -390 { lab=vcm}
+N 1530 -390 1530 -310 { lab=vcm}
+N 1530 -390 1540 -390 { lab=vcm}
+N 1510 -430 1590 -430 { lab=vin}
+N 1590 -620 1780 -620 { lab=vout}
+N 1780 -620 1780 -410 { lab=vout}
+N 1340 -620 1530 -620 { lab=ve}
+C {vsource.sym} 1132.5 -167.5 0 0 {name=V1 value=DC\{vss\}}
+C {vsource.sym} 1220 -167.5 0 0 {name=V2 value=DC\{vdd\}}
+C {vsource.sym} 1530 -280 0 0 {name=V3 value=DC\{vcm\}}
+C {gnd.sym} 1132.5 -100 0 0 {name=l14 lab=GND}
+C {vsource.sym} 1320 -167.5 0 0 {name=V4 value="sin(0 \{vac\} 1Meg) dc 0 ac 1"}
+C {capa.sym} 1320 -267.5 2 0 {name=C4
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1220 -237.5 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1132.5 -237.5 1 0 {name=l16 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1220 -100 3 0 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1530 -210 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1320 -100 3 0 {name=l20 sig_type=std_logic lab=vcm}
+C {lab_pin.sym} 1320 -335 1 0 {name=l21 sig_type=std_logic lab=vin}
+C {isource.sym} 1630 -280 0 0 {name=I0 value=DC\{iref\}}
+C {lab_pin.sym} 1630 -210 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1320 -225 3 0 {name=l24 sig_type=std_logic lab=vsen}
+C {res.sym} 1180 -430 1 0 {name=R1
+value=500
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1370 -430 1 0 {name=R2
+value=1G
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1560 -620 1 0 {name=R3
+value=5k
+footprint=1206
+device=resistor
+m=1}
+C {lab_pin.sym} 1090 -430 0 0 {name=l25 sig_type=std_logic lab=vcm}
+C {lab_wire.sym} 1252.5 -430 0 0 {name=l26 sig_type=std_logic lab=ve
+
+}
+C {lab_pin.sym} 1450 -280 3 0 {name=l28 sig_type=std_logic lab=vss
+}
+C {capa.sym} 1450 -350 0 0 {name=C5
+m=1
+value=5p
+footprint=1206
+device="ceramic capacitor"}
+C {netlist_not_shown.sym} 1080 -600 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib fs
+
+* OP Parameters & Singals to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[id] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[id] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulation
+.control
+  
+  ac dec 100 1 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1
+  meas ac PM find vp(vout) when vdb(vout)=0
+  print PM*180/PI
+  meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) \{vp(vout)*180/PI\}
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_openloop_ac1.raw
+
+  reset
+  op
+  setplot op1
+  write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_openloop_op1.raw
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} 1670 -330 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {capa.sym} 1780 -360 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1780 -300 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1772.5 -410 0 0 {name=l3 sig_type=std_logic lab=vout
+
+}
+C {lab_pin.sym} 1650 -490 1 0 {name=l4 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1572.5 -390 0 0 {name=l5 sig_type=std_logic lab=vcm
+
+}
+C {lab_wire.sym} 1522.5 -430 0 0 {name=l6 sig_type=std_logic lab=vin
+
+}
+C {opamp.sym} 1660 -410 0 0 {name=x1}

diff --git a/xschem/sch/opamp_openloop_rpad.sch b/xschem/sch/opamp_openloop_rpad.sch
new file mode 100644
index 0000000..f687bb0
--- /dev/null
+++ b/xschem/sch/opamp_openloop_rpad.sch

@@ -0,0 +1,164 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1132.5 -137.5 1132.5 -100 { lab=GND}
+N 1132.5 -237.5 1132.5 -197.5 { lab=vss}
+N 1220 -237.5 1220 -197.5 { lab=vdd}
+N 1220 -137.5 1220 -100 { lab=vss}
+N 1530 -250 1530 -210 { lab=vss}
+N 1320 -335 1320 -297.5 { lab=vin}
+N 1630 -250 1630 -210 { lab=vss}
+N 1320 -237.5 1320 -197.5 { lab=vsen}
+N 1320 -137.5 1320 -100 { lab=vcm}
+N 1210 -430 1340 -430 { lab=ve}
+N 1280 -620 1340 -620 { lab=ve}
+N 1270 -620 1270 -430 { lab=ve}
+N 1270 -620 1280 -620 { lab=ve}
+N 1090 -430 1150 -430 { lab=vcm}
+N 1400 -430 1450 -430 { lab=vin}
+N 1450 -430 1510 -430 { lab=vin}
+N 1450 -320 1450 -280 { lab=vss}
+N 1450 -430 1450 -380 { lab=vin}
+N 1630 -350 1630 -310 { lab=#net1}
+N 1670 -350 1670 -330 { lab=vss}
+N 1920 -410 1920 -390 { lab=vout}
+N 1920 -330 1920 -300 { lab=vss}
+N 1650 -490 1650 -460 { lab=vdd}
+N 1540 -390 1590 -390 { lab=vcm}
+N 1530 -390 1530 -310 { lab=vcm}
+N 1530 -390 1540 -390 { lab=vcm}
+N 1590 -620 1780 -620 { lab=vout}
+N 1920 -620 1920 -410 { lab=vout}
+N 1340 -620 1530 -620 { lab=ve}
+N 1780 -620 1920 -620 { lab=vout}
+N 1820 -410 1920 -410 { lab=vout}
+N 1730 -410 1760 -410 { lab=#net2}
+N 1570 -430 1590 -430 { lab=#net3}
+C {vsource.sym} 1132.5 -167.5 0 0 {name=V1 value=DC\{vss\}}
+C {vsource.sym} 1220 -167.5 0 0 {name=V2 value=DC\{vdd\}}
+C {vsource.sym} 1530 -280 0 0 {name=V3 value=DC\{vcm\}}
+C {gnd.sym} 1132.5 -100 0 0 {name=l14 lab=GND}
+C {vsource.sym} 1320 -167.5 0 0 {name=V4 value="sin(0 \{vac\} 1Meg) dc 0 ac 1"}
+C {capa.sym} 1320 -267.5 2 0 {name=C4
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1220 -237.5 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1132.5 -237.5 1 0 {name=l16 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1220 -100 3 0 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1530 -210 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1320 -100 3 0 {name=l20 sig_type=std_logic lab=vcm}
+C {lab_pin.sym} 1320 -335 1 0 {name=l21 sig_type=std_logic lab=vin}
+C {isource.sym} 1630 -280 0 0 {name=I0 value=DC\{iref\}}
+C {lab_pin.sym} 1630 -210 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1320 -225 3 0 {name=l24 sig_type=std_logic lab=vsen}
+C {res.sym} 1180 -430 1 0 {name=R1
+value=500
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1370 -430 1 0 {name=R2
+value=1G
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1560 -620 1 0 {name=R3
+value=5k
+footprint=1206
+device=resistor
+m=1}
+C {lab_pin.sym} 1090 -430 0 0 {name=l25 sig_type=std_logic lab=vcm}
+C {lab_wire.sym} 1252.5 -430 0 0 {name=l26 sig_type=std_logic lab=ve
+
+}
+C {lab_pin.sym} 1450 -280 3 0 {name=l28 sig_type=std_logic lab=vss
+}
+C {capa.sym} 1450 -350 0 0 {name=C5
+m=1
+value=5p
+footprint=1206
+device="ceramic capacitor"}
+C {netlist_not_shown.sym} 1080 -600 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param iref = 100u
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vcm  = 0.8
+.param vac  = 10m
+.options TEMP = 65.0
+
+* Include Models
+*.lib /home/dhernando/projects/foundry/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
+*.lib  ~/fulgor-opamp-sky130/xschem/sky130.lib TT
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM3.msky130_fd_pr__nfet_01v8[id] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM3.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM3.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM4.msky130_fd_pr__nfet_01v8[id] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM4.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM4.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM5.msky130_fd_pr__pfet_01v8[id] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM5.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM6.msky130_fd_pr__nfet_01v8[id] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM6.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM7.msky130_fd_pr__pfet_01v8[id] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM7.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM7.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM8.msky130_fd_pr__pfet_01v8[id] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM8.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM8.msky130_fd_pr__pfet_01v8[gds]
++ @M.X1.XM9.msky130_fd_pr__nfet_01v8[id] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM9.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM9.msky130_fd_pr__nfet_01v8[gds]
+
+*Simulation
+.control
+  
+  ac dec 100 1 10G
+  setplot ac1
+  meas ac GBW when vdb(vout)=0
+  meas ac DCG find vdb(vout) at=1
+  meas ac PM find vp(vout) when vdb(vout)=0
+  print PM*180/PI
+  meas ac GM find vdb(vout) when vp(vout)=0
+  plot vdb(vout) \{vp(vout)*180/PI\}
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_ac1.raw
+
+  reset
+  op
+  setplot op1
+  write ~/fulgor-opamp-sky130/xschem/sim_results/opamp_openloop_op1.raw
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} 1670 -330 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {capa.sym} 1920 -360 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1920 -300 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1912.5 -410 0 0 {name=l3 sig_type=std_logic lab=vout
+
+}
+C {lab_pin.sym} 1650 -490 1 0 {name=l4 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1572.5 -390 0 0 {name=l5 sig_type=std_logic lab=vcm
+
+}
+C {lab_wire.sym} 1482.5 -430 0 0 {name=l6 sig_type=std_logic lab=vin
+
+}
+C {opamp.sym} 1660 -410 0 0 {name=x1}
+C {res.sym} 1540 -430 1 0 {name=R4
+value=150
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 1790 -410 1 0 {name=R5
+value=150
+footprint=1206
+device=resistor
+m=1}

diff --git a/xschem/sim_results/opamp_closeloop_ac1.raw b/xschem/sim_results/opamp_closeloop_ac1.raw
new file mode 100644
index 0000000..3fab6a6
--- /dev/null
+++ b/xschem/sim_results/opamp_closeloop_ac1.raw
Binary files differ

diff --git a/xschem/sim_results/opamp_closeloop_noise.raw b/xschem/sim_results/opamp_closeloop_noise.raw
new file mode 100644
index 0000000..a9d997e
--- /dev/null
+++ b/xschem/sim_results/opamp_closeloop_noise.raw
Binary files differ

diff --git a/xschem/sim_results/opamp_closeloop_op1.raw b/xschem/sim_results/opamp_closeloop_op1.raw
new file mode 100644
index 0000000..4bc9fbd
--- /dev/null
+++ b/xschem/sim_results/opamp_closeloop_op1.raw
Binary files differ

diff --git a/xschem/sim_results/opamp_closeloop_tran1.raw b/xschem/sim_results/opamp_closeloop_tran1.raw
new file mode 100644
index 0000000..6ad6a87
--- /dev/null
+++ b/xschem/sim_results/opamp_closeloop_tran1.raw
Binary files differ

diff --git a/xschem/sim_results/opamp_openloop_ac1.raw b/xschem/sim_results/opamp_openloop_ac1.raw
new file mode 100644
index 0000000..495da28
--- /dev/null
+++ b/xschem/sim_results/opamp_openloop_ac1.raw
Binary files differ

diff --git a/xschem/sim_results/opamp_openloop_op1.raw b/xschem/sim_results/opamp_openloop_op1.raw
new file mode 100644
index 0000000..bc42c73
--- /dev/null
+++ b/xschem/sim_results/opamp_openloop_op1.raw
Binary files differ

diff --git a/xschem/sky130.lib b/xschem/sky130.lib
new file mode 100644
index 0000000..4e95cf0
--- /dev/null
+++ b/xschem/sky130.lib

@@ -0,0 +1,100 @@
+* Copyright 2020 The SkyWater PDK Authors
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+******* SkyWater sky130 model library *********
+
+* Typical corner (tt)
+.lib tt
+* nfet
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.pm3.spice"
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
+* pfet
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.pm3.spice"
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
+* others
+.include "tt/nonfet.spice"
+.include "../all.spice"
+.include "tt/rf.spice"
+* R+C
+.include "../r+c/res_typical__cap_typical.spice"
+.include "../r+c/res_typical__cap_typical__lin.spice"
+.endl
+
+* Slow-Fast corner (sf)
+.lib sf
+* nfet
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.pm3.spice"
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
+* pfet
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.pm3.spice"
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
+* others
+.include "sf/nonfet.spice"
+.include "../all.spice"
+.include "sf/rf.spice"
+* R+C
+.include "../r+c/res_typical__cap_typical.spice"
+.include "../r+c/res_typical__cap_typical__lin.spice"
+.endl
+
+* Fast-Fast corner (ff)
+.lib ff
+* nfet
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.pm3.spice"
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
+* pfet
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.pm3.spice"
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
+* others 
+.include "ff/nonfet.spice"
+.include "../all.spice"
+.include "ff/rf.spice"
+* R+C
+.include "../r+c/res_typical__cap_typical.spice"
+.include "../r+c/res_typical__cap_typical__lin.spice"
+.endl
+
+* Slow-Slow corner (ss)
+.lib ss
+* nfet
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.pm3.spice"
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
+* pfet
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.pm3.spice"
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
+* others
+.include "ss/nonfet.spice"
+.include "../all.spice"
+.include "ss/rf.spice"
+* R+C
+.include "../r+c/res_typical__cap_typical.spice"
+.include "../r+c/res_typical__cap_typical__lin.spice"
+.endl
+
+* Fast-Slow corner (fs)
+.lib fs
+* nfet
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.pm3.spice"
+.include "../../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
+* pfet
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.pm3.spice"
+.include "../../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
+* others
+.include "fs/nonfet.spice"
+.include "../all.spice"
+.include "fs/rf.spice"
+* R+C
+.include "../r+c/res_typical__cap_typical.spice"
+.include "../r+c/res_typical__cap_typical__lin.spice"
+.endl

diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100644
index 0000000..8e464f9
--- /dev/null
+++ b/xschem/xschemrc

@@ -0,0 +1,6 @@
+#Configure xschem project directory to use sky130 symbols
+set XSCHEM_LIBRARY_PATH {}
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
+append XSCHEM_LIBRARY_PATH :~/skywater_pdk/xschem_sky130
+append XSCHEM_LIBRARY_PATH :~/caravel_fulgor_opamp/xschem/sch
+