Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-019/f32f2e09d5db44ea830be56c75cdff4ba75d2d07^!/.
commit
f32f2e09d5db44ea830be56c75cdff4ba75d2d07
[log] [tgz]
author
Diego Hernando <djhernando96@gmail.com>
Sat Dec 19 00:27:20 2020 -0300
committer
Diego Hernando <djhernando96@gmail.com>
Sat Dec 19 00:27:20 2020 -0300
tree
5851a254bf30cd1db04893b5d8470f3c7d49ec52
parent
a9b995895f7d0ec331b8c8fa45038231be1caccb [diff]
Integrated Ring VCO and divider in Ring OSC. Spice Ring VCO. VCO.mag -> ring_vco.mag

diff --git a/mag/VCO/ring_osc.mag b/mag/VCO/ring_osc.mag
new file mode 100644
index 0000000..fc46a6c
--- /dev/null
+++ b/mag/VCO/ring_osc.mag

@@ -0,0 +1,68 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608348248
+<< nwell >>
+rect -4208 9978 7720 11293
+<< metal1 >>
+rect 5922 12160 6111 12370
+rect 5508 12087 8474 12160
+rect 5331 11745 8474 12087
+rect 5508 11700 8474 11745
+rect -4208 10010 7689 10710
+rect -4144 9957 7593 10010
+rect -4281 8521 -4271 8612
+rect -4133 8521 -4123 8612
+rect 8124 7463 8466 11700
+rect 7366 7121 8466 7463
+<< via1 >>
+rect -4271 8521 -4133 8612
+<< metal2 >>
+rect 5575 14223 5805 15861
+rect -4257 11354 -4151 11364
+rect -4257 11205 -4151 11215
+rect -4251 8622 -4157 11205
+rect -4271 8612 -4133 8622
+rect -4271 8511 -4133 8521
+rect -4251 8487 -4157 8511
+rect -4332 7988 -4252 7998
+rect -4332 7894 -4252 7904
+rect 4885 7568 5059 7627
+rect 2693 7512 7358 7568
+rect 4885 6001 5059 7512
+<< via2 >>
+rect -4257 11215 -4151 11354
+rect -4332 7904 -4252 7988
+<< metal3 >>
+rect -4267 11354 -4141 11359
+rect -4267 11347 -4257 11354
+rect -4551 11225 -4257 11347
+rect -4267 11215 -4257 11225
+rect -4151 11347 -4141 11354
+rect -4151 11225 -1526 11347
+rect -4151 11215 -4141 11225
+rect -4267 11210 -4141 11215
+rect -4502 7988 -4234 7998
+rect -4502 7904 -4332 7988
+rect -4252 7904 -4234 7988
+rect -4502 7900 -4234 7904
+rect -4342 7899 -4242 7900
+use ring_vco  ring_vco_0
+timestamp 1608340973
+transform -1 0 2594 0 1 4659
+box -5124 2462 6897 5532
+use divx32  divx32_0
+timestamp 1608345554
+transform 1 0 -1515 0 -1 11957
+box -296 -3279 7626 1470
+<< labels >>
+rlabel metal3 -4551 11225 -4429 11347 1 vco_out
+rlabel metal3 -4502 7900 -4332 7998 1 enable
+rlabel metal2 4885 6001 5059 7627 1 in
+rlabel metal2 5575 15631 5805 15861 1 out_div
+rlabel space -1793 9857 5758 10767 1 vdd
+rlabel space -1733 13083 5028 13636 1 vdd
+rlabel space -4204 7123 7718 7459 1 vss
+rlabel space -1451 11724 8474 12160 1 vss
+rlabel space 389 14569 3835 15168 1 vss
+<< end >>

diff --git a/mag/VCO/VCO.mag b/mag/VCO/ring_vco.mag
similarity index 99%
rename from mag/VCO/VCO.mag
rename to mag/VCO/ring_vco.mag
index 9e6a33c..695c94c 100644
--- a/mag/VCO/VCO.mag
+++ b/mag/VCO/ring_vco.mag

@@ -1221,19 +1221,6 @@
 rect -4764 2853 -39 2857
 rect -4824 2838 -4764 2848
 rect -99 2847 -39 2853
-use via_li_m1  via_li_m1_4
-array 0 13 72 0 0 74
-timestamp 1607692587
-transform 1 0 5705 0 1 3141
-box 4 0 76 74
-use sky130_fd_pr__nfet_01v8_R7545W  sky130_fd_pr__nfet_01v8_R7545W_0
-timestamp 1608229183
-transform 1 0 5788 0 1 3563
-box -211 -330 211 330
-use sky130_fd_pr__nfet_01v8_9TXQ83  sky130_fd_pr__nfet_01v8_9TXQ83_1
-timestamp 1608229483
-transform 1 0 6580 0 1 3579
-box -211 -264 211 264
 use sky130_fd_pr__nfet_01v8_ZE46K8  sky130_fd_pr__nfet_01v8_ZE46K8_0
 timestamp 1608322001
 transform -1 0 -64 0 -1 3056
@@ -1252,6 +1239,19 @@
 timestamp 1608249442
 transform -1 0 -4795 0 -1 3024
 box -211 -300 211 300
+use via_li_m1  via_li_m1_4
+array 0 13 72 0 0 74
+timestamp 1607692587
+transform 1 0 5705 0 1 3141
+box 4 0 76 74
+use sky130_fd_pr__nfet_01v8_R7545W  sky130_fd_pr__nfet_01v8_R7545W_0
+timestamp 1608229183
+transform 1 0 5788 0 1 3563
+box -211 -330 211 330
+use sky130_fd_pr__nfet_01v8_9TXQ83  sky130_fd_pr__nfet_01v8_9TXQ83_1
+timestamp 1608229483
+transform 1 0 6580 0 1 3579
+box -211 -264 211 264
 use sky130_fd_pr__pfet_01v8_373K6R  sky130_fd_pr__pfet_01v8_373K6R_0
 timestamp 1608255150
 transform 1 0 6580 0 1 4274
@@ -1260,6 +1260,11 @@
 timestamp 1608254796
 transform 1 0 5788 0 1 4431
 box -211 -436 211 459
+use inverter  inverter_1
+array 0 19 430 0 0 936
+timestamp 1608336920
+transform 1 0 935 0 1 3178
+box -5252 188 -4822 1124
 use sky130_fd_pr__pfet_01v8_35M7SP  sky130_fd_pr__pfet_01v8_35M7SP_0
 timestamp 1608253040
 transform 1 0 -4755 0 1 4963
@@ -1282,11 +1287,6 @@
 timestamp 1608325973
 transform 1 0 4710 0 1 4083
 box -267 -910 511 767
-use inverter  inverter_1
-array 0 19 430 0 0 936
-timestamp 1608336920
-transform 1 0 935 0 1 3178
-box -5252 188 -4822 1124
 << labels >>
 rlabel metal1 -5114 2462 -3040 2804 1 vss
 rlabel metal1 -5122 5198 -2718 5516 1 vdd

diff --git a/xschem/ring_vco/ring_vco.sch b/xschem/ring_vco/ring_vco.sch
index f839f88..04f9773 100644
--- a/xschem/ring_vco/ring_vco.sch
+++ b/xschem/ring_vco/ring_vco.sch

@@ -242,15 +242,15 @@
 N 2350 0 2410 -0 { lab=#net1}
 N 2120 -0 2140 0 { lab=#net12}
 N 2150 20 2170 20 { lab=en}
-N 2220 70 2220 80 {}
-N 2120 70 2210 70 {}
-N 2010 50 2120 50 {}
-N 2120 50 2120 70 {}
-N 2140 -20 2170 -20 {}
-N 2310 -0 2350 -0 {}
-N 2220 -80 2220 -70 {}
-N 2140 -20 2140 0 {}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
+N 2220 70 2220 80 { lab=9}
+N 2120 70 2210 70 { lab=vss}
+N 2010 50 2120 50 { lab=vss}
+N 2120 50 2120 70 { lab=vss}
+N 2140 -20 2170 -20 { lab=#net12}
+N 2310 -0 2350 -0 { lab=#net1}
+N 2220 -80 2220 -70 { lab=10}
+N 2140 -20 2140 0 { lab=#net12}
+C {not.sym} 0 0 0 0 {name=x1}
 C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
 C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
 C {gnd.sym} 480 -270 0 0 {name=l1 lab=GND}
@@ -308,11 +308,11 @@
 
 .end
 "}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 110 0 0 0 {name=x2}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 220 0 0 0 {name=x3}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 330 0 0 0 {name=x4}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 440 0 0 0 {name=x5}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 550 0 0 0 {name=x6}
+C {not.sym} 110 0 0 0 {name=x2}
+C {not.sym} 220 0 0 0 {name=x3}
+C {not.sym} 330 0 0 0 {name=x4}
+C {not.sym} 440 0 0 0 {name=x5}
+C {not.sym} 550 0 0 0 {name=x6}
 C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
 C {lab_wire.sym} 2690 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
 C {lab_wire.sym} 2690 120 0 0 {name=l14 sig_type=std_logic lab=vss}
@@ -421,40 +421,40 @@
 C {vsource.sym} 670 -330 0 0 {name=V3 value=DC\{Vin\}}
 C {lab_pin.sym} 670 -270 3 0 {name=l22 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 670 -390 1 0 {name=l23 sig_type=std_logic lab=in}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 660 0 0 0 {name=x7}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 770 0 0 0 {name=x8}
+C {not.sym} 660 0 0 0 {name=x7}
+C {not.sym} 770 0 0 0 {name=x8}
 C {lab_wire.sym} 720 0 0 0 {name=l24 sig_type=std_logic lab=o7}
 C {lab_wire.sym} 830 0 0 0 {name=l25 sig_type=std_logic lab=o8}
 C {lab_wire.sym} -30 50 0 0 {name=l26 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 2560 120 3 0 {name=l27 sig_type=std_logic lab=vss}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 880 0 0 0 {name=x9}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 990 0 0 0 {name=x10}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1100 0 0 0 {name=x11}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1220 0 0 0 {name=x12}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1340 0 0 0 {name=x13}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1460 0 0 0 {name=x14}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1580 0 0 0 {name=x15}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1700 0 0 0 {name=x16}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1820 0 0 0 {name=x17}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1950 0 0 0 {name=x18}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2070 0 0 0 {name=x19}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 770 310 0 0 {name=x21}
+C {not.sym} 880 0 0 0 {name=x9}
+C {not.sym} 990 0 0 0 {name=x10}
+C {not.sym} 1100 0 0 0 {name=x11}
+C {not.sym} 1220 0 0 0 {name=x12}
+C {not.sym} 1340 0 0 0 {name=x13}
+C {not.sym} 1460 0 0 0 {name=x14}
+C {not.sym} 1580 0 0 0 {name=x15}
+C {not.sym} 1700 0 0 0 {name=x16}
+C {not.sym} 1820 0 0 0 {name=x17}
+C {not.sym} 1950 0 0 0 {name=x18}
+C {not.sym} 2070 0 0 0 {name=x19}
+C {FD_v2.sym} 770 310 0 0 {name=x21}
 C {lab_pin.sym} 770 210 1 0 {name=l28 sig_type=std_logic lab=vdd
 }
 C {lab_pin.sym} 770 420 3 0 {name=l29 sig_type=std_logic lab=vss}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 970 310 0 0 {name=x22}
+C {FD_v2.sym} 970 310 0 0 {name=x22}
 C {lab_pin.sym} 970 210 1 0 {name=l30 sig_type=std_logic lab=vdd
 }
 C {lab_pin.sym} 970 420 3 0 {name=l31 sig_type=std_logic lab=vss}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1170 310 0 0 {name=x23}
+C {FD_v2.sym} 1170 310 0 0 {name=x23}
 C {lab_pin.sym} 1170 210 1 0 {name=l32 sig_type=std_logic lab=vdd
 }
 C {lab_pin.sym} 1170 420 3 0 {name=l33 sig_type=std_logic lab=vss}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1370 310 0 0 {name=x24}
+C {FD_v2.sym} 1370 310 0 0 {name=x24}
 C {lab_pin.sym} 1370 210 1 0 {name=l34 sig_type=std_logic lab=vdd
 }
 C {lab_pin.sym} 1370 420 3 0 {name=l35 sig_type=std_logic lab=vss}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1570 310 0 0 {name=x25}
+C {FD_v2.sym} 1570 310 0 0 {name=x25}
 C {lab_pin.sym} 1570 210 1 0 {name=l36 sig_type=std_logic lab=vdd
 }
 C {lab_pin.sym} 1570 420 3 0 {name=l37 sig_type=std_logic lab=vss}
@@ -495,7 +495,7 @@
 spiceprefix=X
 }
 C {lab_wire.sym} 1680 310 0 0 {name=l47 sig_type=std_logic lab=outx32}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym} 2230 0 0 0 {name=x26}
+C {nand.sym} 2230 0 0 0 {name=x26}
 C {vsource.sym} 770 -330 0 0 {name=V4 value="PULSE(0 \{Vdd\} 100ns 1ps 1ps 0.25us 0.5us)"}
 C {lab_pin.sym} 770 -270 3 0 {name=l49 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 770 -390 1 0 {name=l50 sig_type=std_logic lab=en}

diff --git a/xschem/ring_vco/ring_vco_only.spice b/xschem/ring_vco/ring_vco_only.spice
new file mode 100644
index 0000000..7606622
--- /dev/null
+++ b/xschem/ring_vco/ring_vco_only.spice

@@ -0,0 +1,74 @@
+**.subckt ring_vco
+x1 10 out_ring o1 9 vss not
+x2 10 o1 o2 9 vss not
+x3 10 o2 o3 9 vss not
+x4 10 o3 o4 9 vss not
+x5 10 o4 o5 9 vss not
+x6 10 o5 o6 9 vss not
+XM1 out_ring net1 9 vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out_ring net1 10 10 sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
+XM3 out_vco out_ring vss vss sky130_fd_pr__nfet_01v8 W=0.6 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM4 out_vco out_ring vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 10 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 9 in vss vss sky130_fd_pr__nfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM7 5 5 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM8 5 in vss vss sky130_fd_pr__nfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+x7 10 o6 o7 9 vss not
+x8 10 o7 o8 9 vss not
+x9 10 o8 net2 9 vss not
+x10 10 net2 net3 9 vss not
+x11 10 net3 net4 9 vss not
+x12 10 net4 net8 9 vss not
+x13 10 net8 net7 9 vss not
+x14 10 net7 net6 9 vss not
+x15 10 net6 net5 9 vss not
+x16 10 net5 net9 9 vss not
+x17 10 net9 net10 9 vss not
+x18 10 net10 net11 9 vss not
+x19 10 net11 net12 9 vss not
+x26 10 net12 net1 en 9 vss nand
+**.ends
+
+* expanding   symbol:  not.sym # of pins=5
+
+.subckt not  vdd in out vss vbulk
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+*.ipin vbulk
+XM1 out in vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  nand.sym # of pins=6
+
+.subckt nand  vdd A OUT B vss vbulk
+*.opin OUT
+*.ipin vdd
+*.ipin A
+*.ipin B
+*.ipin vss
+*.ipin vbulk
+XM1 net1 B vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 OUT A net1 vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 OUT A vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 OUT B vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+.end