commit ec9b536c863b8b0adc16cd87e7e054f4a1a812e7
author Manar <manarabdelatty@aucegypt.edu> Wed Oct 28 22:24:06 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Oct 28 22:58:30 2020 +0200
tree 88b6b8cd5099a692f6e03717dbdb8cbbea62b3b5
parent d01c63748cd1b4f3b3201504f6d858936a5cd348

Removed storage area from mgmt_core

- commented USE_OPENRAM in defines.v to use 1kb of synthesized memory

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 55d0d2d..1139f1d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -42,7 +42,6 @@
 `include "la_wb.v"
 `include "mprj_ctrl.v"
 `include "convert_gpio_sigs.v"
-`include "mem_synth_wb.v"
 
 module mgmt_soc (
 `ifdef LVS
@@ -141,13 +140,12 @@
     output [31:0] mprj_dat_o
 );
     /* Memory reverted back to 256 words while memory has to be synthesized */
-    parameter [31:0] STACKADDR = (4*(`MEM_WORDS + `MEM_SYNTH_WORDS));       // end of memory
+    parameter [31:0] STACKADDR = (4*(`MEM_WORDS));       // end of memory
     parameter [31:0] PROGADDR_RESET = 32'h 1000_0000; 
     parameter [31:0] PROGADDR_IRQ   = 32'h 0000_0000;
 
     // Slaves Base Addresses
     parameter RAM_BASE_ADR    = 32'h 0000_0000;
-    parameter RAM_SYNTH_BASE_ADR = 32'h 0100_0000;
     parameter FLASH_BASE_ADR  = 32'h 1000_0000;
     parameter UART_BASE_ADR   = 32'h 2000_0000;
     parameter GPIO_BASE_ADR   = 32'h 2100_0000;
@@ -203,7 +201,7 @@
     // Wishbone Interconnect 
     localparam ADR_WIDTH = 32;
     localparam DAT_WIDTH = 32;
-    localparam NUM_SLAVES = 13;
+    localparam NUM_SLAVES = 12;
 
     parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
@@ -217,7 +215,6 @@
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
-        {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}}
     };
 
@@ -233,7 +230,6 @@
         {GPIO_BASE_ADR},
         {UART_BASE_ADR},
         {FLASH_BASE_ADR},
-        {RAM_SYNTH_BASE_ADR},
         {RAM_BASE_ADR}
     };
 
@@ -717,24 +713,6 @@
         .wb_dat_o(mem_dat_o)
     );
 
-    // Wishbone Slave Synthesized RAM
-    wire mem_synth_stb_i;
-    wire mem_synth_ack_o;
-    wire [31:0] mem_synth_dat_o;
-
-    mem_synth_wb soc_mem_synth (
-        .wb_clk_i(wb_clk_i),
-        .wb_rst_i(wb_rst_i),
-        .wb_adr_i(cpu_adr_o), 
-        .wb_dat_i(cpu_dat_o),
-        .wb_sel_i(cpu_sel_o),
-        .wb_we_i(cpu_we_o),
-        .wb_cyc_i(cpu_cyc_o),
-        .wb_stb_i(mem_synth_stb_i),
-        .wb_ack_o(mem_synth_ack_o), 
-        .wb_dat_o(mem_synth_dat_o)
-    );
-
     // Wishbone intercon logic
     wb_intercon #(
         .AW(ADR_WIDTH),
@@ -754,17 +732,17 @@
 		mprj_stb_o, mprj_ctrl_stb_i, la_stb_i, 
 		spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
 		gpio_stb_i, uart_stb_i,
-		spimemio_flash_stb_i, mem_synth_stb_i, mem_stb_i }), 
+		spimemio_flash_stb_i, mem_stb_i }), 
         .wbs_dat_i({ sys_dat_o, spimemio_cfg_dat_o,
 		mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
 		spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
 		gpio_dat_o, uart_dat_o,
-		spimemio_flash_dat_o,mem_synth_dat_o, mem_dat_o }),
+		spimemio_flash_dat_o, mem_dat_o }),
         .wbs_ack_i({ sys_ack_o, spimemio_cfg_ack_o,
 		mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
 		spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
 		gpio_ack_o, uart_ack_o,
-		spimemio_flash_ack_o, mem_synth_ack_o,  mem_ack_o })
+		spimemio_flash_ack_o,  mem_ack_o })
     );
 
 endmodule